diff --git a/bsp/stm32/libraries/Kconfig b/bsp/stm32/libraries/Kconfig
index b7e47866b1a..4e5c98fd098 100644
--- a/bsp/stm32/libraries/Kconfig
+++ b/bsp/stm32/libraries/Kconfig
@@ -47,6 +47,7 @@ config SOC_SERIES_STM32L1
     bool
     select ARCH_ARM_CORTEX_M3
     select SOC_FAMILY_STM32
+    select PKG_USING_STM32L1_HAL_DRIVER
 
 config SOC_SERIES_STM32L4
     bool
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h
deleted file mode 100644
index 9b5af5d0055..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h
+++ /dev/null
@@ -1,7669 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l100xb.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l100xb
-  * @{
-  */
-    
-#ifndef __STM32L100xB_H
-#define __STM32L100xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x28                                                                  */
-  uint32_t RESERVED2;       /*!< Reserved, 0x2C                                                                  */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  uint32_t RESERVED3;       /*!< Reserved, 0x38                                                                  */
-  uint32_t RESERVED4;       /*!< Reserved, 0x3C                                                                  */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  uint32_t RESERVED5;       /*!< Reserved, 0x44                                                                  */
-  uint32_t RESERVED6;       /*!< Reserved, 0x48                                                                  */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x080807FFUL)              /*!< FLASH EEPROM end address (2KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-/* No Internal temperature sensor embedded with STM32L100 devices */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT1
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00001FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 5
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L100xB_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h
deleted file mode 100644
index 8f80f90e52c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h
+++ /dev/null
@@ -1,7817 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l100xba.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l100xba
-  * @{
-  */
-    
-#ifndef __STM32L100xBA_H
-#define __STM32L100xBA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x080807FFUL)              /*!< FLASH EEPROM end address (2KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-/* No Internal temperature sensor embedded with STM32L100 devices */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT2
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 5
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L100xBA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h
deleted file mode 100644
index f0cd00b6292..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h
+++ /dev/null
@@ -1,8415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l100xc.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l100xc
-  * @{
-  */
-    
-#ifndef __STM32L100xC_H
-#define __STM32L100xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08080FFFUL)              /*!< FLASH EEPROM end address (4KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-/* No Internal temperature sensor embedded with STM32L100 devices */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 5
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L100xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h
deleted file mode 100644
index 161dbdd666b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h
+++ /dev/null
@@ -1,7618 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xb.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xb
-  * @{
-  */
-    
-#ifndef __STM32L151xB_H
-#define __STM32L151xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x28                                                                  */
-  uint32_t RESERVED2;       /*!< Reserved, 0x2C                                                                  */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  uint32_t RESERVED3;       /*!< Reserved, 0x38                                                                  */
-  uint32_t RESERVED4;       /*!< Reserved, 0x3C                                                                  */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  uint32_t RESERVED5;       /*!< Reserved, 0x44                                                                  */
-  uint32_t RESERVED6;       /*!< Reserved, 0x48                                                                  */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x08080FFFUL)              /*!< FLASH EEPROM end address (4KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF8007A      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF8007E      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT1
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00001FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 20
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xB_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h
deleted file mode 100644
index 69ea9c20969..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h
+++ /dev/null
@@ -1,7694 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xba.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xba
-  * @{
-  */
-    
-#ifndef __STM32L151xBA_H
-#define __STM32L151xBA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x08080FFFUL)              /*!< FLASH EEPROM end address (4KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF8007A      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF8007E      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT2
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_SPRMOD_Pos                 (8U)                              
-#define FLASH_OBR_SPRMOD_Msk                 (0x1UL << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
-#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 5
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xBA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h
deleted file mode 100644
index 9e04ae25271..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h
+++ /dev/null
@@ -1,8615 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xc.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xc
-  * @{
-  */
-    
-#ifndef __STM32L151xC_H
-#define __STM32L151xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_SPRMOD_Pos                 (8U)                              
-#define FLASH_OBR_SPRMOD_Msk                 (0x1UL << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
-#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h
deleted file mode 100644
index b3427aff5d6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h
+++ /dev/null
@@ -1,8702 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xca.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xca
-  * @{
-  */
-    
-#ifndef __STM32L151xCA_H
-#define __STM32L151xCA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xCA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h
deleted file mode 100644
index f09b8e25d32..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h
+++ /dev/null
@@ -1,9416 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xd.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xd
-  * @{
-  */
-    
-#ifndef __STM32L151xD_H
-#define __STM32L151xD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;  /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;    /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;    /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;    /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;    /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;   /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;      /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define FSMC_BASE             (0x60000000UL)              /*!< FSMC base address */
-#define FSMC_R_BASE           (0xA0000000UL)              /*!< FSMC registers base address */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0805FFFFUL)              /*!< Program end FLASH address for Cat4 */
-#define FLASH_BANK2_BASE      (0x08030000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END       (0x0805FFFFUL)              /*!< Program end FLASH BANK2 address */
-#define FLASH_EEPROM_END      (0x08082FFFUL)              /*!< FLASH EEPROM end address  (12KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define FSMC_BANK1            (FSMC_BASE)                 /*!< FSMC Bank1 base address */
-#define FSMC_BANK1_1          (FSMC_BANK1)                /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000UL)    /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104UL)    /*!< FSMC Bank1E registers base address */
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP3              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U))
-#define OPAMP123_COMMON     ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_OPA3PD_Pos                  (16U)                            
-#define OPAMP_CSR_OPA3PD_Msk                  (0x1UL << OPAMP_CSR_OPA3PD_Pos)   /*!< 0x00010000 */
-#define OPAMP_CSR_OPA3PD                      OPAMP_CSR_OPA3PD_Msk             /*!< OPAMP3 disable */
-#define OPAMP_CSR_S3SEL3_Pos                  (17U)                            
-#define OPAMP_CSR_S3SEL3_Msk                  (0x1UL << OPAMP_CSR_S3SEL3_Pos)   /*!< 0x00020000 */
-#define OPAMP_CSR_S3SEL3                      OPAMP_CSR_S3SEL3_Msk             /*!< Switch 3 for OPAMP3 Enable */
-#define OPAMP_CSR_S4SEL3_Pos                  (18U)                            
-#define OPAMP_CSR_S4SEL3_Msk                  (0x1UL << OPAMP_CSR_S4SEL3_Pos)   /*!< 0x00040000 */
-#define OPAMP_CSR_S4SEL3                      OPAMP_CSR_S4SEL3_Msk             /*!< Switch 4 for OPAMP3 Enable */
-#define OPAMP_CSR_S5SEL3_Pos                  (19U)                            
-#define OPAMP_CSR_S5SEL3_Msk                  (0x1UL << OPAMP_CSR_S5SEL3_Pos)   /*!< 0x00080000 */
-#define OPAMP_CSR_S5SEL3                      OPAMP_CSR_S5SEL3_Msk             /*!< Switch 5 for OPAMP3 Enable */
-#define OPAMP_CSR_S6SEL3_Pos                  (20U)                            
-#define OPAMP_CSR_S6SEL3_Msk                  (0x1UL << OPAMP_CSR_S6SEL3_Pos)   /*!< 0x00100000 */
-#define OPAMP_CSR_S6SEL3                      OPAMP_CSR_S6SEL3_Msk             /*!< Switch 6 for OPAMP3 Enable */
-#define OPAMP_CSR_OPA3CAL_L_Pos               (21U)                            
-#define OPAMP_CSR_OPA3CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */
-#define OPAMP_CSR_OPA3CAL_L                   OPAMP_CSR_OPA3CAL_L_Msk          /*!< OPAMP3 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA3CAL_H_Pos               (22U)                            
-#define OPAMP_CSR_OPA3CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */
-#define OPAMP_CSR_OPA3CAL_H                   OPAMP_CSR_OPA3CAL_H_Msk          /*!< OPAMP3 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA3LPM_Pos                 (23U)                            
-#define OPAMP_CSR_OPA3LPM_Msk                 (0x1UL << OPAMP_CSR_OPA3LPM_Pos)  /*!< 0x00800000 */
-#define OPAMP_CSR_OPA3LPM                     OPAMP_CSR_OPA3LPM_Msk            /*!< OPAMP3 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_ANAWSEL3_Pos                (26U)                            
-#define OPAMP_CSR_ANAWSEL3_Msk                (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */
-#define OPAMP_CSR_ANAWSEL3                    OPAMP_CSR_ANAWSEL3_Msk           /*!< Switch ANA Enable for OPAMP3 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-#define OPAMP_CSR_OPA3CALOUT_Pos              (31U)                            
-#define OPAMP_CSR_OPA3CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */
-#define OPAMP_CSR_OPA3CALOUT                  OPAMP_CSR_OPA3CALOUT_Msk         /*!< OPAMP3 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U)                            
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U)                           
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U)                         
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U)                        
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT4
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCRx register (x=1..4) *******************/
-#define FSMC_BCRx_MBKEN_Pos                 (0U)                               
-#define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
-#define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
-#define FSMC_BCRx_MUXEN_Pos                 (1U)                               
-#define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
-#define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCRx_MTYP_Pos                  (2U)                               
-#define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
-#define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
-#define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
-
-#define FSMC_BCRx_MWID_Pos                  (4U)                               
-#define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
-#define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
-#define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
-
-#define FSMC_BCRx_FACCEN_Pos                (6U)                               
-#define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
-#define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
-#define FSMC_BCRx_BURSTEN_Pos               (8U)                               
-#define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
-#define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
-#define FSMC_BCRx_WAITPOL_Pos               (9U)                               
-#define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
-#define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
-#define FSMC_BCRx_WRAPMOD_Pos               (10U)                              
-#define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
-#define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
-#define FSMC_BCRx_WAITCFG_Pos               (11U)                              
-#define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
-#define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
-#define FSMC_BCRx_WREN_Pos                  (12U)                              
-#define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
-#define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
-#define FSMC_BCRx_WAITEN_Pos                (13U)                              
-#define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
-#define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
-#define FSMC_BCRx_EXTMOD_Pos                (14U)                              
-#define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
-#define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
-#define FSMC_BCRx_ASYNCWAIT_Pos             (15U)                              
-#define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
-#define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
-#define FSMC_BCRx_CPSIZE_Pos                (16U)                              
-#define FSMC_BCRx_CPSIZE_Msk                (0x7UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00070000 */
-#define FSMC_BCRx_CPSIZE                    FSMC_BCRx_CPSIZE_Msk               /*!< Cellular RAM page size */
-#define FSMC_BCRx_CPSIZE_0                  (0x1UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00010000 */
-#define FSMC_BCRx_CPSIZE_1                  (0x2UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00020000 */
-#define FSMC_BCRx_CPSIZE_2                  (0x4UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00040000 */
-#define FSMC_BCRx_CBURSTRW_Pos              (19U)                              
-#define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
-#define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTRx register (x=1..4)  ******************/
-#define FSMC_BTRx_ADDSET_Pos                (0U)                               
-#define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
-#define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
-#define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
-#define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
-#define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
-
-#define FSMC_BTRx_ADDHLD_Pos                (4U)                               
-#define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
-#define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
-#define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
-#define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
-#define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
-
-#define FSMC_BTRx_DATAST_Pos                (8U)                               
-#define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
-#define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
-#define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
-#define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
-#define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
-#define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
-#define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
-#define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
-#define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
-
-#define FSMC_BTRx_BUSTURN_Pos               (16U)                              
-#define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
-#define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
-#define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
-#define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
-#define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
-
-#define FSMC_BTRx_CLKDIV_Pos                (20U)                              
-#define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
-#define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
-#define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
-#define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
-#define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
-
-#define FSMC_BTRx_DATLAT_Pos                (24U)                              
-#define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
-#define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
-#define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
-#define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
-#define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
-
-#define FSMC_BTRx_ACCMOD_Pos                (28U)                              
-#define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
-#define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
-#define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTRx register (x=1..4) ******************/
-#define FSMC_BWTRx_ADDSET_Pos               (0U)                               
-#define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
-#define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
-#define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
-#define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
-#define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
-
-#define FSMC_BWTRx_ADDHLD_Pos               (4U)                               
-#define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
-#define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
-#define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
-#define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
-#define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
-
-#define FSMC_BWTRx_DATAST_Pos               (8U)                               
-#define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
-#define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
-#define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
-#define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
-#define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
-#define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
-#define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
-#define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
-#define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
-
-#define FSMC_BWTRx_BUSTURN_Pos              (16U)                              
-#define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
-#define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
-#define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
-#define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
-#define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
-
-#define FSMC_BWTRx_ACCMOD_Pos               (28U)                              
-#define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
-#define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
-#define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_FSMCRST_Pos             (30U)                              
-#define RCC_AHBRSTR_FSMCRST_Msk             (0x1UL << RCC_AHBRSTR_FSMCRST_Pos)  /*!< 0x40000000 */
-#define RCC_AHBRSTR_FSMCRST                 RCC_AHBRSTR_FSMCRST_Msk            /*!< FSMC reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SDIORST_Pos            (11U)                              
-#define RCC_APB2RSTR_SDIORST_Msk            (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_SDIORST                RCC_APB2RSTR_SDIORST_Msk           /*!< SDIO reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_FSMCEN_Pos               (30U)                              
-#define RCC_AHBENR_FSMCEN_Msk               (0x1UL << RCC_AHBENR_FSMCEN_Pos)    /*!< 0x40000000 */
-#define RCC_AHBENR_FSMCEN                   RCC_AHBENR_FSMCEN_Msk              /*!< FSMC clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SDIOEN_Pos              (11U)                              
-#define RCC_APB2ENR_SDIOEN_Msk              (0x1UL << RCC_APB2ENR_SDIOEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB2ENR_SDIOEN                  RCC_APB2ENR_SDIOEN_Msk             /*!< SDIO clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_FSMCLPEN_Pos           (30U)                              
-#define RCC_AHBLPENR_FSMCLPEN_Msk           (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */
-#define RCC_AHBLPENR_FSMCLPEN               RCC_AHBLPENR_FSMCLPEN_Msk          /*!< FSMC clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SDIOLPEN_Pos          (11U)                              
-#define RCC_APB2LPENR_SDIOLPEN_Msk          (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB2LPENR_SDIOLPEN              RCC_APB2LPENR_SDIOLPEN_Msk         /*!< SDIO clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define SDIO_POWER_PWRCTRL_Pos              (0U)                               
-#define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000001 */
-#define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000002 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define SDIO_CLKCR_CLKDIV_Pos               (0U)                               
-#define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos                (8U)                               
-#define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos               (9U)                               
-#define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos               (10U)                              
-#define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos               (11U)                              
-#define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00000800 */
-#define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos              (13U)                              
-#define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos              (14U)                              
-#define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define SDIO_ARG_CMDARG_Pos                 (0U)                               
-#define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define SDIO_CMD_CMDINDEX_Pos               (0U)                               
-#define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos               (6U)                               
-#define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000040 */
-#define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000080 */
-
-#define SDIO_CMD_WAITINT_Pos                (8U)                               
-#define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos               (9U)                               
-#define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos                 (10U)                              
-#define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos            (11U)                              
-#define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos             (12U)                              
-#define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos                   (13U)                              
-#define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
-#define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos               (14U)                              
-#define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos            (0U)                               
-#define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos          (0U)                               
-#define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos          (0U)                               
-#define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos          (0U)                               
-#define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos          (0U)                               
-#define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos          (0U)                               
-#define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define SDIO_DTIMER_DATATIME_Pos            (0U)                               
-#define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define SDIO_DLEN_DATALENGTH_Pos            (0U)                               
-#define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define SDIO_DCTRL_DTEN_Pos                 (0U)                               
-#define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos                (1U)                               
-#define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos               (2U)                               
-#define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos                (3U)                               
-#define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)                               
-#define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
-
-#define SDIO_DCTRL_RWSTART_Pos              (8U)                               
-#define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos               (9U)                               
-#define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos                (10U)                              
-#define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos               (11U)                              
-#define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos           (0U)                               
-#define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define SDIO_STA_CCRCFAIL_Pos               (0U)                               
-#define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos               (1U)                               
-#define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos               (2U)                               
-#define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos               (3U)                               
-#define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos               (4U)                               
-#define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos                (5U)                               
-#define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos                (6U)                               
-#define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
-#define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos                (7U)                               
-#define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos                (8U)                               
-#define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
-#define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos               (9U)                               
-#define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
-#define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos                (10U)                              
-#define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos                 (11U)                              
-#define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
-#define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos                  (12U)                              
-#define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
-#define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos                  (13U)                              
-#define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
-#define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos               (14U)                              
-#define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos               (15U)                              
-#define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos                (16U)                              
-#define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos                (17U)                              
-#define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos                (18U)                              
-#define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos                (19U)                              
-#define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos                 (20U)                              
-#define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos                 (21U)                              
-#define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos                 (22U)                              
-#define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos               (23U)                              
-#define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define SDIO_ICR_CCRCFAILC_Pos              (0U)                               
-#define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos              (1U)                               
-#define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos              (2U)                               
-#define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos              (3U)                               
-#define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos              (4U)                               
-#define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos               (5U)                               
-#define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos               (6U)                               
-#define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos               (7U)                               
-#define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos               (8U)                               
-#define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos              (9U)                               
-#define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos               (10U)                              
-#define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos                (22U)                              
-#define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos              (23U)                              
-#define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos            (0U)                               
-#define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos            (1U)                               
-#define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos            (2U)                               
-#define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos            (3U)                               
-#define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos            (4U)                               
-#define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos             (5U)                               
-#define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos             (6U)                               
-#define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos             (7U)                               
-#define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos             (8U)                               
-#define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos            (9U)                               
-#define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos             (10U)                              
-#define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos              (11U)                              
-#define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos               (12U)                              
-#define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos               (13U)                              
-#define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos            (14U)                              
-#define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos            (15U)                              
-#define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos             (16U)                              
-#define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos             (17U)                              
-#define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos             (18U)                              
-#define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos             (19U)                              
-#define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos              (20U)                              
-#define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos              (21U)                              
-#define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos              (22U)                              
-#define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos            (23U)                              
-#define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)                               
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define SDIO_FIFO_FIFODATA_Pos              (0U)                               
-#define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2) || \
-                                         ((INSTANCE) == OPAMP3))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/****************************** SDIO Instances *********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xD_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h
deleted file mode 100644
index 5583b59a8b8..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h
+++ /dev/null
@@ -1,8777 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xdx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xdx
-  * @{
-  */
-    
-#ifndef __STM32L151xDX_H
-#define __STM32L151xDX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0806FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0806FFFFUL)              /*!< Program end FLASH address for Cat6 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT6
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFUL << FLASH_WRPR2_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 47  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFUL << FLASH_WRPR4_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 111 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xDX_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h
deleted file mode 100644
index 6985398de89..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h
+++ /dev/null
@@ -1,8777 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xe.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xe
-  * @{
-  */
-    
-#ifndef __STM32L151xE_H
-#define __STM32L151xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0803FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0807FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0807FFFFUL)              /*!< Program end FLASH address for Cat5 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT5
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 127 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h
deleted file mode 100644
index a4cf8615aa5..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h
+++ /dev/null
@@ -1,7772 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xb.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xb
-  * @{
-  */
-    
-#ifndef __STM32L152xB_H
-#define __STM32L152xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x28                                                                  */
-  uint32_t RESERVED2;       /*!< Reserved, 0x2C                                                                  */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  uint32_t RESERVED3;       /*!< Reserved, 0x38                                                                  */
-  uint32_t RESERVED4;       /*!< Reserved, 0x3C                                                                  */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  uint32_t RESERVED5;       /*!< Reserved, 0x44                                                                  */
-  uint32_t RESERVED6;       /*!< Reserved, 0x48                                                                  */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x08080FFFUL)              /*!< FLASH EEPROM end address (4KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF8007A      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF8007E      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT1
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00001FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 20
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xB_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h
deleted file mode 100644
index 12f15e15e85..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h
+++ /dev/null
@@ -1,7833 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xba.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xba
-  * @{
-  */
-    
-#ifndef __STM32L152xBA_H
-#define __STM32L152xBA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-} OB_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0801FFFFUL)              /*!< Program end FLASH address for Cat1 & Cat2 */
-#define FLASH_EEPROM_END      (0x08080FFFUL)              /*!< FLASH EEPROM end address (4KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF8004CUL)                  /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
-#define UID_BASE              (0x1FF80050UL)                  /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF80078      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF8007A      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF8007E      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-/* Catgeroy 1 & 2 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Catgeroy 1 & 2 */
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0x7FFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT2
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_SPRMOD_Pos                 (8U)                              
-#define FLASH_OBR_SPRMOD_Msk                 (0x1UL << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
-#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 5
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x3FCFFFFUL << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x3UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x1UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x2UL << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************************** TIM Instances *********************************/ 
-
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xBA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h
deleted file mode 100644
index b659ccc2912..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h
+++ /dev/null
@@ -1,8769 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xc.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xc
-  * @{
-  */
-    
-#ifndef __STM32L152xC_H
-#define __STM32L152xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_SPRMOD_Pos                 (8U)                              
-#define FLASH_OBR_SPRMOD_Msk                 (0x1UL << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
-#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h
deleted file mode 100644
index 701532dd2ee..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h
+++ /dev/null
@@ -1,8856 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xca.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xca
-  * @{
-  */
-    
-#ifndef __STM32L152xCA_H
-#define __STM32L152xCA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xCA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h
deleted file mode 100644
index bb0ad24c5cf..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h
+++ /dev/null
@@ -1,9570 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xd.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xd
-  * @{
-  */
-    
-#ifndef __STM32L152xD_H
-#define __STM32L152xD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;  /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;    /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;    /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;    /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;    /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;   /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;      /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define FSMC_BASE             (0x60000000UL)              /*!< FSMC base address */
-#define FSMC_R_BASE           (0xA0000000UL)              /*!< FSMC registers base address */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0805FFFFUL)              /*!< Program end FLASH address for Cat4 */
-#define FLASH_BANK2_BASE      (0x08030000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END       (0x0805FFFFUL)              /*!< Program end FLASH BANK2 address */
-#define FLASH_EEPROM_END      (0x08082FFFUL)              /*!< FLASH EEPROM end address  (12KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define FSMC_BANK1            (FSMC_BASE)                 /*!< FSMC Bank1 base address */
-#define FSMC_BANK1_1          (FSMC_BANK1)                /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000UL)    /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104UL)    /*!< FSMC Bank1E registers base address */
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP3              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U))
-#define OPAMP123_COMMON     ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_OPA3PD_Pos                  (16U)                            
-#define OPAMP_CSR_OPA3PD_Msk                  (0x1UL << OPAMP_CSR_OPA3PD_Pos)   /*!< 0x00010000 */
-#define OPAMP_CSR_OPA3PD                      OPAMP_CSR_OPA3PD_Msk             /*!< OPAMP3 disable */
-#define OPAMP_CSR_S3SEL3_Pos                  (17U)                            
-#define OPAMP_CSR_S3SEL3_Msk                  (0x1UL << OPAMP_CSR_S3SEL3_Pos)   /*!< 0x00020000 */
-#define OPAMP_CSR_S3SEL3                      OPAMP_CSR_S3SEL3_Msk             /*!< Switch 3 for OPAMP3 Enable */
-#define OPAMP_CSR_S4SEL3_Pos                  (18U)                            
-#define OPAMP_CSR_S4SEL3_Msk                  (0x1UL << OPAMP_CSR_S4SEL3_Pos)   /*!< 0x00040000 */
-#define OPAMP_CSR_S4SEL3                      OPAMP_CSR_S4SEL3_Msk             /*!< Switch 4 for OPAMP3 Enable */
-#define OPAMP_CSR_S5SEL3_Pos                  (19U)                            
-#define OPAMP_CSR_S5SEL3_Msk                  (0x1UL << OPAMP_CSR_S5SEL3_Pos)   /*!< 0x00080000 */
-#define OPAMP_CSR_S5SEL3                      OPAMP_CSR_S5SEL3_Msk             /*!< Switch 5 for OPAMP3 Enable */
-#define OPAMP_CSR_S6SEL3_Pos                  (20U)                            
-#define OPAMP_CSR_S6SEL3_Msk                  (0x1UL << OPAMP_CSR_S6SEL3_Pos)   /*!< 0x00100000 */
-#define OPAMP_CSR_S6SEL3                      OPAMP_CSR_S6SEL3_Msk             /*!< Switch 6 for OPAMP3 Enable */
-#define OPAMP_CSR_OPA3CAL_L_Pos               (21U)                            
-#define OPAMP_CSR_OPA3CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */
-#define OPAMP_CSR_OPA3CAL_L                   OPAMP_CSR_OPA3CAL_L_Msk          /*!< OPAMP3 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA3CAL_H_Pos               (22U)                            
-#define OPAMP_CSR_OPA3CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */
-#define OPAMP_CSR_OPA3CAL_H                   OPAMP_CSR_OPA3CAL_H_Msk          /*!< OPAMP3 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA3LPM_Pos                 (23U)                            
-#define OPAMP_CSR_OPA3LPM_Msk                 (0x1UL << OPAMP_CSR_OPA3LPM_Pos)  /*!< 0x00800000 */
-#define OPAMP_CSR_OPA3LPM                     OPAMP_CSR_OPA3LPM_Msk            /*!< OPAMP3 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_ANAWSEL3_Pos                (26U)                            
-#define OPAMP_CSR_ANAWSEL3_Msk                (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */
-#define OPAMP_CSR_ANAWSEL3                    OPAMP_CSR_ANAWSEL3_Msk           /*!< Switch ANA Enable for OPAMP3 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-#define OPAMP_CSR_OPA3CALOUT_Pos              (31U)                            
-#define OPAMP_CSR_OPA3CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */
-#define OPAMP_CSR_OPA3CALOUT                  OPAMP_CSR_OPA3CALOUT_Msk         /*!< OPAMP3 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U)                            
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U)                           
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U)                         
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U)                        
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT4
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCRx register (x=1..4) *******************/
-#define FSMC_BCRx_MBKEN_Pos                 (0U)                               
-#define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
-#define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
-#define FSMC_BCRx_MUXEN_Pos                 (1U)                               
-#define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
-#define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCRx_MTYP_Pos                  (2U)                               
-#define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
-#define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
-#define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
-
-#define FSMC_BCRx_MWID_Pos                  (4U)                               
-#define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
-#define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
-#define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
-
-#define FSMC_BCRx_FACCEN_Pos                (6U)                               
-#define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
-#define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
-#define FSMC_BCRx_BURSTEN_Pos               (8U)                               
-#define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
-#define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
-#define FSMC_BCRx_WAITPOL_Pos               (9U)                               
-#define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
-#define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
-#define FSMC_BCRx_WRAPMOD_Pos               (10U)                              
-#define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
-#define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
-#define FSMC_BCRx_WAITCFG_Pos               (11U)                              
-#define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
-#define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
-#define FSMC_BCRx_WREN_Pos                  (12U)                              
-#define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
-#define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
-#define FSMC_BCRx_WAITEN_Pos                (13U)                              
-#define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
-#define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
-#define FSMC_BCRx_EXTMOD_Pos                (14U)                              
-#define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
-#define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
-#define FSMC_BCRx_ASYNCWAIT_Pos             (15U)                              
-#define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
-#define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
-#define FSMC_BCRx_CPSIZE_Pos                (16U)                              
-#define FSMC_BCRx_CPSIZE_Msk                (0x7UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00070000 */
-#define FSMC_BCRx_CPSIZE                    FSMC_BCRx_CPSIZE_Msk               /*!< Cellular RAM page size */
-#define FSMC_BCRx_CPSIZE_0                  (0x1UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00010000 */
-#define FSMC_BCRx_CPSIZE_1                  (0x2UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00020000 */
-#define FSMC_BCRx_CPSIZE_2                  (0x4UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00040000 */
-#define FSMC_BCRx_CBURSTRW_Pos              (19U)                              
-#define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
-#define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTRx register (x=1..4)  ******************/
-#define FSMC_BTRx_ADDSET_Pos                (0U)                               
-#define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
-#define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
-#define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
-#define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
-#define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
-
-#define FSMC_BTRx_ADDHLD_Pos                (4U)                               
-#define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
-#define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
-#define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
-#define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
-#define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
-
-#define FSMC_BTRx_DATAST_Pos                (8U)                               
-#define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
-#define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
-#define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
-#define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
-#define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
-#define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
-#define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
-#define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
-#define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
-
-#define FSMC_BTRx_BUSTURN_Pos               (16U)                              
-#define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
-#define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
-#define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
-#define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
-#define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
-
-#define FSMC_BTRx_CLKDIV_Pos                (20U)                              
-#define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
-#define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
-#define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
-#define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
-#define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
-
-#define FSMC_BTRx_DATLAT_Pos                (24U)                              
-#define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
-#define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
-#define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
-#define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
-#define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
-
-#define FSMC_BTRx_ACCMOD_Pos                (28U)                              
-#define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
-#define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
-#define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTRx register (x=1..4) ******************/
-#define FSMC_BWTRx_ADDSET_Pos               (0U)                               
-#define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
-#define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
-#define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
-#define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
-#define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
-
-#define FSMC_BWTRx_ADDHLD_Pos               (4U)                               
-#define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
-#define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
-#define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
-#define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
-#define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
-
-#define FSMC_BWTRx_DATAST_Pos               (8U)                               
-#define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
-#define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
-#define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
-#define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
-#define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
-#define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
-#define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
-#define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
-#define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
-
-#define FSMC_BWTRx_BUSTURN_Pos              (16U)                              
-#define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
-#define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
-#define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
-#define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
-#define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
-
-#define FSMC_BWTRx_ACCMOD_Pos               (28U)                              
-#define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
-#define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
-#define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_FSMCRST_Pos             (30U)                              
-#define RCC_AHBRSTR_FSMCRST_Msk             (0x1UL << RCC_AHBRSTR_FSMCRST_Pos)  /*!< 0x40000000 */
-#define RCC_AHBRSTR_FSMCRST                 RCC_AHBRSTR_FSMCRST_Msk            /*!< FSMC reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SDIORST_Pos            (11U)                              
-#define RCC_APB2RSTR_SDIORST_Msk            (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_SDIORST                RCC_APB2RSTR_SDIORST_Msk           /*!< SDIO reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_FSMCEN_Pos               (30U)                              
-#define RCC_AHBENR_FSMCEN_Msk               (0x1UL << RCC_AHBENR_FSMCEN_Pos)    /*!< 0x40000000 */
-#define RCC_AHBENR_FSMCEN                   RCC_AHBENR_FSMCEN_Msk              /*!< FSMC clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SDIOEN_Pos              (11U)                              
-#define RCC_APB2ENR_SDIOEN_Msk              (0x1UL << RCC_APB2ENR_SDIOEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB2ENR_SDIOEN                  RCC_APB2ENR_SDIOEN_Msk             /*!< SDIO clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_FSMCLPEN_Pos           (30U)                              
-#define RCC_AHBLPENR_FSMCLPEN_Msk           (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */
-#define RCC_AHBLPENR_FSMCLPEN               RCC_AHBLPENR_FSMCLPEN_Msk          /*!< FSMC clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SDIOLPEN_Pos          (11U)                              
-#define RCC_APB2LPENR_SDIOLPEN_Msk          (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB2LPENR_SDIOLPEN              RCC_APB2LPENR_SDIOLPEN_Msk         /*!< SDIO clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define SDIO_POWER_PWRCTRL_Pos              (0U)                               
-#define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000001 */
-#define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000002 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define SDIO_CLKCR_CLKDIV_Pos               (0U)                               
-#define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos                (8U)                               
-#define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos               (9U)                               
-#define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos               (10U)                              
-#define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos               (11U)                              
-#define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00000800 */
-#define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos              (13U)                              
-#define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos              (14U)                              
-#define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define SDIO_ARG_CMDARG_Pos                 (0U)                               
-#define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define SDIO_CMD_CMDINDEX_Pos               (0U)                               
-#define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos               (6U)                               
-#define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000040 */
-#define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000080 */
-
-#define SDIO_CMD_WAITINT_Pos                (8U)                               
-#define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos               (9U)                               
-#define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos                 (10U)                              
-#define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos            (11U)                              
-#define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos             (12U)                              
-#define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos                   (13U)                              
-#define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
-#define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos               (14U)                              
-#define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos            (0U)                               
-#define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos          (0U)                               
-#define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos          (0U)                               
-#define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos          (0U)                               
-#define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos          (0U)                               
-#define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos          (0U)                               
-#define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define SDIO_DTIMER_DATATIME_Pos            (0U)                               
-#define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define SDIO_DLEN_DATALENGTH_Pos            (0U)                               
-#define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define SDIO_DCTRL_DTEN_Pos                 (0U)                               
-#define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos                (1U)                               
-#define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos               (2U)                               
-#define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos                (3U)                               
-#define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)                               
-#define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
-
-#define SDIO_DCTRL_RWSTART_Pos              (8U)                               
-#define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos               (9U)                               
-#define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos                (10U)                              
-#define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos               (11U)                              
-#define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos           (0U)                               
-#define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define SDIO_STA_CCRCFAIL_Pos               (0U)                               
-#define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos               (1U)                               
-#define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos               (2U)                               
-#define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos               (3U)                               
-#define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos               (4U)                               
-#define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos                (5U)                               
-#define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos                (6U)                               
-#define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
-#define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos                (7U)                               
-#define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos                (8U)                               
-#define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
-#define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos               (9U)                               
-#define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
-#define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos                (10U)                              
-#define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos                 (11U)                              
-#define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
-#define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos                  (12U)                              
-#define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
-#define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos                  (13U)                              
-#define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
-#define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos               (14U)                              
-#define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos               (15U)                              
-#define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos                (16U)                              
-#define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos                (17U)                              
-#define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos                (18U)                              
-#define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos                (19U)                              
-#define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos                 (20U)                              
-#define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos                 (21U)                              
-#define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos                 (22U)                              
-#define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos               (23U)                              
-#define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define SDIO_ICR_CCRCFAILC_Pos              (0U)                               
-#define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos              (1U)                               
-#define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos              (2U)                               
-#define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos              (3U)                               
-#define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos              (4U)                               
-#define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos               (5U)                               
-#define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos               (6U)                               
-#define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos               (7U)                               
-#define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos               (8U)                               
-#define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos              (9U)                               
-#define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos               (10U)                              
-#define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos                (22U)                              
-#define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos              (23U)                              
-#define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos            (0U)                               
-#define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos            (1U)                               
-#define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos            (2U)                               
-#define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos            (3U)                               
-#define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos            (4U)                               
-#define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos             (5U)                               
-#define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos             (6U)                               
-#define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos             (7U)                               
-#define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos             (8U)                               
-#define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos            (9U)                               
-#define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos             (10U)                              
-#define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos              (11U)                              
-#define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos               (12U)                              
-#define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos               (13U)                              
-#define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos            (14U)                              
-#define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos            (15U)                              
-#define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos             (16U)                              
-#define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos             (17U)                              
-#define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos             (18U)                              
-#define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos             (19U)                              
-#define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos              (20U)                              
-#define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos              (21U)                              
-#define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos              (22U)                              
-#define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos            (23U)                              
-#define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)                               
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define SDIO_FIFO_FIFODATA_Pos              (0U)                               
-#define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2) || \
-                                         ((INSTANCE) == OPAMP3))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/****************************** SDIO Instances *********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xD_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h
deleted file mode 100644
index 1eaf3af587e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h
+++ /dev/null
@@ -1,8931 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xdx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xdx
-  * @{
-  */
-    
-#ifndef __STM32L152xDX_H
-#define __STM32L152xDX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0806FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0806FFFFUL)              /*!< Program end FLASH address for Cat6 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT6
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFUL << FLASH_WRPR2_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 47  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFUL << FLASH_WRPR4_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 111 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xDX_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h
deleted file mode 100644
index 9589a790d21..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h
+++ /dev/null
@@ -1,8931 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xe.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xe
-  * @{
-  */
-    
-#ifndef __STM32L152xE_H
-#define __STM32L152xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0803FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0807FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0807FFFFUL)              /*!< Program end FLASH address for Cat5 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT5
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 127 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h
deleted file mode 100644
index 7ae05e8192b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h
+++ /dev/null
@@ -1,8911 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l162xc.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l162xc
-  * @{
-  */
-    
-#ifndef __STM32L162xC_H
-#define __STM32L162xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define AES_BASE              (0x50060000UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos                       (0U)                               
-#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
-#define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos                 (1U)                               
-#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
-#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
-#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos                     (3U)                               
-#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
-#define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
-#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos                    (5U)                               
-#define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
-#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
-#define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos                     (7U)                               
-#define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
-#define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos                     (8U)                               
-#define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
-#define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
-#define AES_CR_CCIE_Pos                     (9U)                               
-#define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
-#define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos                    (10U)                              
-#define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
-#define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos                  (11U)                              
-#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
-#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos                 (12U)                              
-#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos                      (0U)                               
-#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
-#define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos                    (1U)                               
-#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
-#define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos                    (2U)                               
-#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
-#define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos                        (0U)                               
-#define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
-#define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos                       (0U)                               
-#define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
-#define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos                       (0U)                               
-#define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos                       (0U)                               
-#define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos                       (0U)                               
-#define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos                       (0U)                               
-#define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos                        (0U)                               
-#define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos                        (0U)                               
-#define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos                        (0U)                               
-#define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos                        (0U)                               
-#define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-#define FLASH_SR_RDERR_Pos                   (13U)                             
-#define FLASH_SR_RDERR_Msk                   (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
-#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_SPRMOD_Pos                 (8U)                              
-#define FLASH_OBR_SPRMOD_Msk                 (0x1UL << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
-#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0x7UL << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_AESRST_Pos              (27U)                              
-#define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
-#define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_AESEN_Pos                (27U)                              
-#define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
-#define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_AESLPEN_Pos            (27U)                              
-#define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/****************************** AES Instances *********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L162xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h
deleted file mode 100644
index 39441737f65..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h
+++ /dev/null
@@ -1,8998 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l162xca.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l162xca
-  * @{
-  */
-    
-#ifndef __STM32L162xCA_H
-#define __STM32L162xCA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0803FFFFUL)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      (0x08081FFFUL)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define AES_BASE              (0x50060000UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos                       (0U)                               
-#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
-#define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos                 (1U)                               
-#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
-#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
-#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos                     (3U)                               
-#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
-#define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
-#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos                    (5U)                               
-#define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
-#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
-#define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos                     (7U)                               
-#define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
-#define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos                     (8U)                               
-#define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
-#define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
-#define AES_CR_CCIE_Pos                     (9U)                               
-#define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
-#define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos                    (10U)                              
-#define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
-#define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos                  (11U)                              
-#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
-#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos                 (12U)                              
-#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos                      (0U)                               
-#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
-#define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos                    (1U)                               
-#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
-#define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos                    (2U)                               
-#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
-#define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos                        (0U)                               
-#define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
-#define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos                       (0U)                               
-#define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
-#define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos                       (0U)                               
-#define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos                       (0U)                               
-#define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos                       (0U)                               
-#define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos                       (0U)                               
-#define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos                        (0U)                               
-#define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos                        (0U)                               
-#define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos                        (0U)                               
-#define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos                        (0U)                               
-#define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT3
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_AESRST_Pos              (27U)                              
-#define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
-#define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_AESEN_Pos                (27U)                              
-#define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
-#define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_AESLPEN_Pos            (27U)                              
-#define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/****************************** AES Instances *********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L162xCA_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h
deleted file mode 100644
index f86f329bd47..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h
+++ /dev/null
@@ -1,9712 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l162xd.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l162xd
-  * @{
-  */
-    
-#ifndef __STM32L162xD_H
-#define __STM32L162xD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
-} FSMC_Bank1_TypeDef; 
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-  
-typedef struct
-{
-  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
-  __I uint32_t  RESPCMD;  /*!< SDIO command response register, Address offset: 0x10 */
-  __I uint32_t  RESP1;    /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __I uint32_t  RESP2;    /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __I uint32_t  RESP3;    /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __I uint32_t  RESP4;    /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
-  __I uint32_t  DCOUNT;   /*!< SDIO data counter register,     Address offset: 0x30 */
-  __I uint32_t  STA;      /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
-  __I uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define FSMC_BASE             (0x60000000UL)              /*!< FSMC base address */
-#define FSMC_R_BASE           (0xA0000000UL)              /*!< FSMC registers base address */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             (0x0805FFFFUL)              /*!< Program end FLASH address for Cat4 */
-#define FLASH_BANK2_BASE      (0x08030000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END       (0x0805FFFFUL)              /*!< Program end FLASH BANK2 address */
-#define FLASH_EEPROM_END      (0x08082FFFUL)              /*!< FLASH EEPROM end address  (12KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define AES_BASE              (0x50060000UL)
-#define FSMC_BANK1            (FSMC_BASE)                 /*!< FSMC Bank1 base address */
-#define FSMC_BANK1_1          (FSMC_BANK1)                /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000UL)    /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104UL)    /*!< FSMC Bank1E registers base address */
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP3              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U))
-#define OPAMP123_COMMON     ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos                       (0U)                               
-#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
-#define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos                 (1U)                               
-#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
-#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
-#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos                     (3U)                               
-#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
-#define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
-#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos                    (5U)                               
-#define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
-#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
-#define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos                     (7U)                               
-#define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
-#define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos                     (8U)                               
-#define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
-#define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
-#define AES_CR_CCIE_Pos                     (9U)                               
-#define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
-#define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos                    (10U)                              
-#define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
-#define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos                  (11U)                              
-#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
-#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos                 (12U)                              
-#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos                      (0U)                               
-#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
-#define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos                    (1U)                               
-#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
-#define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos                    (2U)                               
-#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
-#define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos                        (0U)                               
-#define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
-#define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos                       (0U)                               
-#define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
-#define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos                       (0U)                               
-#define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos                       (0U)                               
-#define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos                       (0U)                               
-#define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos                       (0U)                               
-#define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos                        (0U)                               
-#define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos                        (0U)                               
-#define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos                        (0U)                               
-#define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos                        (0U)                               
-#define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_OPA3PD_Pos                  (16U)                            
-#define OPAMP_CSR_OPA3PD_Msk                  (0x1UL << OPAMP_CSR_OPA3PD_Pos)   /*!< 0x00010000 */
-#define OPAMP_CSR_OPA3PD                      OPAMP_CSR_OPA3PD_Msk             /*!< OPAMP3 disable */
-#define OPAMP_CSR_S3SEL3_Pos                  (17U)                            
-#define OPAMP_CSR_S3SEL3_Msk                  (0x1UL << OPAMP_CSR_S3SEL3_Pos)   /*!< 0x00020000 */
-#define OPAMP_CSR_S3SEL3                      OPAMP_CSR_S3SEL3_Msk             /*!< Switch 3 for OPAMP3 Enable */
-#define OPAMP_CSR_S4SEL3_Pos                  (18U)                            
-#define OPAMP_CSR_S4SEL3_Msk                  (0x1UL << OPAMP_CSR_S4SEL3_Pos)   /*!< 0x00040000 */
-#define OPAMP_CSR_S4SEL3                      OPAMP_CSR_S4SEL3_Msk             /*!< Switch 4 for OPAMP3 Enable */
-#define OPAMP_CSR_S5SEL3_Pos                  (19U)                            
-#define OPAMP_CSR_S5SEL3_Msk                  (0x1UL << OPAMP_CSR_S5SEL3_Pos)   /*!< 0x00080000 */
-#define OPAMP_CSR_S5SEL3                      OPAMP_CSR_S5SEL3_Msk             /*!< Switch 5 for OPAMP3 Enable */
-#define OPAMP_CSR_S6SEL3_Pos                  (20U)                            
-#define OPAMP_CSR_S6SEL3_Msk                  (0x1UL << OPAMP_CSR_S6SEL3_Pos)   /*!< 0x00100000 */
-#define OPAMP_CSR_S6SEL3                      OPAMP_CSR_S6SEL3_Msk             /*!< Switch 6 for OPAMP3 Enable */
-#define OPAMP_CSR_OPA3CAL_L_Pos               (21U)                            
-#define OPAMP_CSR_OPA3CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */
-#define OPAMP_CSR_OPA3CAL_L                   OPAMP_CSR_OPA3CAL_L_Msk          /*!< OPAMP3 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA3CAL_H_Pos               (22U)                            
-#define OPAMP_CSR_OPA3CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */
-#define OPAMP_CSR_OPA3CAL_H                   OPAMP_CSR_OPA3CAL_H_Msk          /*!< OPAMP3 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA3LPM_Pos                 (23U)                            
-#define OPAMP_CSR_OPA3LPM_Msk                 (0x1UL << OPAMP_CSR_OPA3LPM_Pos)  /*!< 0x00800000 */
-#define OPAMP_CSR_OPA3LPM                     OPAMP_CSR_OPA3LPM_Msk            /*!< OPAMP3 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_ANAWSEL3_Pos                (26U)                            
-#define OPAMP_CSR_ANAWSEL3_Msk                (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */
-#define OPAMP_CSR_ANAWSEL3                    OPAMP_CSR_ANAWSEL3_Msk           /*!< Switch ANA Enable for OPAMP3 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-#define OPAMP_CSR_OPA3CALOUT_Pos              (31U)                            
-#define OPAMP_CSR_OPA3CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */
-#define OPAMP_CSR_OPA3CALOUT                  OPAMP_CSR_OPA3CALOUT_Msk         /*!< OPAMP3 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U)                            
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U)                           
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U)                         
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U)                        
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */
-#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT4
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Flexible Static Memory Controller                    */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCRx register (x=1..4) *******************/
-#define FSMC_BCRx_MBKEN_Pos                 (0U)                               
-#define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
-#define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
-#define FSMC_BCRx_MUXEN_Pos                 (1U)                               
-#define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
-#define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
-
-#define FSMC_BCRx_MTYP_Pos                  (2U)                               
-#define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
-#define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
-#define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
-#define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
-
-#define FSMC_BCRx_MWID_Pos                  (4U)                               
-#define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
-#define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
-#define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
-
-#define FSMC_BCRx_FACCEN_Pos                (6U)                               
-#define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
-#define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
-#define FSMC_BCRx_BURSTEN_Pos               (8U)                               
-#define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
-#define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
-#define FSMC_BCRx_WAITPOL_Pos               (9U)                               
-#define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
-#define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
-#define FSMC_BCRx_WRAPMOD_Pos               (10U)                              
-#define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
-#define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
-#define FSMC_BCRx_WAITCFG_Pos               (11U)                              
-#define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
-#define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
-#define FSMC_BCRx_WREN_Pos                  (12U)                              
-#define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
-#define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
-#define FSMC_BCRx_WAITEN_Pos                (13U)                              
-#define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
-#define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
-#define FSMC_BCRx_EXTMOD_Pos                (14U)                              
-#define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
-#define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
-#define FSMC_BCRx_ASYNCWAIT_Pos             (15U)                              
-#define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
-#define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
-#define FSMC_BCRx_CPSIZE_Pos                (16U)                              
-#define FSMC_BCRx_CPSIZE_Msk                (0x7UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00070000 */
-#define FSMC_BCRx_CPSIZE                    FSMC_BCRx_CPSIZE_Msk               /*!< Cellular RAM page size */
-#define FSMC_BCRx_CPSIZE_0                  (0x1UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00010000 */
-#define FSMC_BCRx_CPSIZE_1                  (0x2UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00020000 */
-#define FSMC_BCRx_CPSIZE_2                  (0x4UL << FSMC_BCRx_CPSIZE_Pos)     /*!< 0x00040000 */
-#define FSMC_BCRx_CBURSTRW_Pos              (19U)                              
-#define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
-#define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
-
-/******************  Bit definition for FSMC_BTRx register (x=1..4)  ******************/
-#define FSMC_BTRx_ADDSET_Pos                (0U)                               
-#define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
-#define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
-#define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
-#define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
-#define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
-
-#define FSMC_BTRx_ADDHLD_Pos                (4U)                               
-#define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
-#define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
-#define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
-#define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
-#define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
-
-#define FSMC_BTRx_DATAST_Pos                (8U)                               
-#define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
-#define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
-#define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
-#define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
-#define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
-#define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
-#define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
-#define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
-#define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
-
-#define FSMC_BTRx_BUSTURN_Pos               (16U)                              
-#define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
-#define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
-#define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
-#define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
-#define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
-
-#define FSMC_BTRx_CLKDIV_Pos                (20U)                              
-#define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
-#define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
-#define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
-#define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
-#define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
-
-#define FSMC_BTRx_DATLAT_Pos                (24U)                              
-#define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
-#define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
-#define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
-#define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
-#define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
-#define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
-
-#define FSMC_BTRx_ACCMOD_Pos                (28U)                              
-#define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
-#define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
-#define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTRx register (x=1..4) ******************/
-#define FSMC_BWTRx_ADDSET_Pos               (0U)                               
-#define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
-#define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
-#define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
-#define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
-#define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
-
-#define FSMC_BWTRx_ADDHLD_Pos               (4U)                               
-#define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
-#define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
-#define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
-#define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
-#define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
-
-#define FSMC_BWTRx_DATAST_Pos               (8U)                               
-#define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
-#define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
-#define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
-#define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
-#define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
-#define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
-#define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
-#define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
-#define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
-
-#define FSMC_BWTRx_BUSTURN_Pos              (16U)                              
-#define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
-#define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
-#define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
-#define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
-#define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
-
-#define FSMC_BWTRx_ACCMOD_Pos               (28U)                              
-#define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
-#define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
-#define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_AESRST_Pos              (27U)                              
-#define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
-#define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
-#define RCC_AHBRSTR_FSMCRST_Pos             (30U)                              
-#define RCC_AHBRSTR_FSMCRST_Msk             (0x1UL << RCC_AHBRSTR_FSMCRST_Pos)  /*!< 0x40000000 */
-#define RCC_AHBRSTR_FSMCRST                 RCC_AHBRSTR_FSMCRST_Msk            /*!< FSMC reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SDIORST_Pos            (11U)                              
-#define RCC_APB2RSTR_SDIORST_Msk            (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_SDIORST                RCC_APB2RSTR_SDIORST_Msk           /*!< SDIO reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_AESEN_Pos                (27U)                              
-#define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
-#define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
-#define RCC_AHBENR_FSMCEN_Pos               (30U)                              
-#define RCC_AHBENR_FSMCEN_Msk               (0x1UL << RCC_AHBENR_FSMCEN_Pos)    /*!< 0x40000000 */
-#define RCC_AHBENR_FSMCEN                   RCC_AHBENR_FSMCEN_Msk              /*!< FSMC clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SDIOEN_Pos              (11U)                              
-#define RCC_APB2ENR_SDIOEN_Msk              (0x1UL << RCC_APB2ENR_SDIOEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB2ENR_SDIOEN                  RCC_APB2ENR_SDIOEN_Msk             /*!< SDIO clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_AESLPEN_Pos            (27U)                              
-#define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
-#define RCC_AHBLPENR_FSMCLPEN_Pos           (30U)                              
-#define RCC_AHBLPENR_FSMCLPEN_Msk           (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */
-#define RCC_AHBLPENR_FSMCLPEN               RCC_AHBLPENR_FSMCLPEN_Msk          /*!< FSMC clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SDIOLPEN_Pos          (11U)                              
-#define RCC_APB2LPENR_SDIOLPEN_Msk          (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB2LPENR_SDIOLPEN              RCC_APB2LPENR_SDIOLPEN_Msk         /*!< SDIO clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define SDIO_POWER_PWRCTRL_Pos              (0U)                               
-#define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000001 */
-#define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000002 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define SDIO_CLKCR_CLKDIV_Pos               (0U)                               
-#define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos                (8U)                               
-#define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos               (9U)                               
-#define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos               (10U)                              
-#define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos               (11U)                              
-#define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00000800 */
-#define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos              (13U)                              
-#define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos              (14U)                              
-#define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define SDIO_ARG_CMDARG_Pos                 (0U)                               
-#define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define SDIO_CMD_CMDINDEX_Pos               (0U)                               
-#define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos               (6U)                               
-#define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000040 */
-#define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x00000080 */
-
-#define SDIO_CMD_WAITINT_Pos                (8U)                               
-#define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos               (9U)                               
-#define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos                 (10U)                              
-#define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos            (11U)                              
-#define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos             (12U)                              
-#define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos                   (13U)                              
-#define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
-#define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos               (14U)                              
-#define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos            (0U)                               
-#define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos          (0U)                               
-#define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos          (0U)                               
-#define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos          (0U)                               
-#define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos          (0U)                               
-#define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos          (0U)                               
-#define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define SDIO_DTIMER_DATATIME_Pos            (0U)                               
-#define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define SDIO_DLEN_DATALENGTH_Pos            (0U)                               
-#define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define SDIO_DCTRL_DTEN_Pos                 (0U)                               
-#define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos                (1U)                               
-#define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos               (2U)                               
-#define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos                (3U)                               
-#define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)                               
-#define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
-
-#define SDIO_DCTRL_RWSTART_Pos              (8U)                               
-#define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos               (9U)                               
-#define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos                (10U)                              
-#define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos               (11U)                              
-#define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos           (0U)                               
-#define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define SDIO_STA_CCRCFAIL_Pos               (0U)                               
-#define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos               (1U)                               
-#define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos               (2U)                               
-#define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos               (3U)                               
-#define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos               (4U)                               
-#define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos                (5U)                               
-#define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos                (6U)                               
-#define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
-#define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos                (7U)                               
-#define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos                (8U)                               
-#define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
-#define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos               (9U)                               
-#define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
-#define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos                (10U)                              
-#define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos                 (11U)                              
-#define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
-#define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos                  (12U)                              
-#define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
-#define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos                  (13U)                              
-#define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
-#define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos               (14U)                              
-#define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos               (15U)                              
-#define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos                (16U)                              
-#define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos                (17U)                              
-#define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos                (18U)                              
-#define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos                (19U)                              
-#define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos                 (20U)                              
-#define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos                 (21U)                              
-#define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos                 (22U)                              
-#define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos               (23U)                              
-#define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define SDIO_ICR_CCRCFAILC_Pos              (0U)                               
-#define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos              (1U)                               
-#define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos              (2U)                               
-#define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos              (3U)                               
-#define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos              (4U)                               
-#define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos               (5U)                               
-#define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos               (6U)                               
-#define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos               (7U)                               
-#define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos               (8U)                               
-#define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos              (9U)                               
-#define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos               (10U)                              
-#define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos                (22U)                              
-#define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos              (23U)                              
-#define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos            (0U)                               
-#define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos            (1U)                               
-#define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos            (2U)                               
-#define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos            (3U)                               
-#define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos            (4U)                               
-#define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos             (5U)                               
-#define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos             (6U)                               
-#define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos             (7U)                               
-#define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos             (8U)                               
-#define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos            (9U)                               
-#define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos             (10U)                              
-#define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos              (11U)                              
-#define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos               (12U)                              
-#define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos               (13U)                              
-#define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos            (14U)                              
-#define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos            (15U)                              
-#define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos             (16U)                              
-#define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos             (17U)                              
-#define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos             (18U)                              
-#define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos             (19U)                              
-#define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos              (20U)                              
-#define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos              (21U)                              
-#define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos              (22U)                              
-#define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos            (23U)                              
-#define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)                               
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define SDIO_FIFO_FIFODATA_Pos              (0U)                               
-#define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/****************************** AES Instances *********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2) || \
-                                         ((INSTANCE) == OPAMP3))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/****************************** SDIO Instances *********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L162xD_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h
deleted file mode 100644
index eda15e0f20c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h
+++ /dev/null
@@ -1,9073 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l162xdx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l162xdx
-  * @{
-  */
-    
-#ifndef __STM32L162xDX_H
-#define __STM32L162xDX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0802FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0806FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0806FFFFUL)              /*!< Program end FLASH address for Cat6 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define AES_BASE              (0x50060000UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos                       (0U)                               
-#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
-#define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos                 (1U)                               
-#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
-#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
-#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos                     (3U)                               
-#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
-#define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
-#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos                    (5U)                               
-#define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
-#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
-#define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos                     (7U)                               
-#define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
-#define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos                     (8U)                               
-#define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
-#define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
-#define AES_CR_CCIE_Pos                     (9U)                               
-#define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
-#define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos                    (10U)                              
-#define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
-#define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos                  (11U)                              
-#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
-#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos                 (12U)                              
-#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos                      (0U)                               
-#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
-#define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos                    (1U)                               
-#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
-#define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos                    (2U)                               
-#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
-#define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos                        (0U)                               
-#define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
-#define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos                       (0U)                               
-#define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
-#define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos                       (0U)                               
-#define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos                       (0U)                               
-#define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos                       (0U)                               
-#define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos                       (0U)                               
-#define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos                        (0U)                               
-#define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos                        (0U)                               
-#define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos                        (0U)                               
-#define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos                        (0U)                               
-#define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT6
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFUL << FLASH_WRPR2_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 47  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFUL << FLASH_WRPR4_WRP_Pos)  /*!< 0x0000FFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 111 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_AESRST_Pos              (27U)                              
-#define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
-#define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_AESEN_Pos                (27U)                              
-#define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
-#define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_AESLPEN_Pos            (27U)                              
-#define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/****************************** AES Instances *********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L162xDX_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h
deleted file mode 100644
index 689cfcec59b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h
+++ /dev/null
@@ -1,9073 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l162xe.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral�s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l162xe
-  * @{
-  */
-    
-#ifndef __STM32L162xE_H
-#define __STM32L162xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief AES hardware accelerator
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
-} AES_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
-  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */ 
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 
-} OPAMP_Common_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            (0x08000000UL)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     (FLASH_BASE + 0x80000UL)    /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             (0x20000000UL)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           (0x40000000UL)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          (0x22000000UL)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        (0x42000000UL)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      (0x08040000UL)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       (0x0803FFFFUL)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       (0x0807FFFFUL)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_END             (0x0807FFFFUL)              /*!< Program end FLASH address for Cat5 */
-#define FLASH_EEPROM_END      (0x08083FFFUL)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04UL)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CUL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000UL)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400UL)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800UL)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000UL)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400UL)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800UL)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00UL)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800UL)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
-#define OB_BASE               (0x1FF80000UL)                  /*!< FLASH Option Bytes base address */
-#define FLASHSIZE_BASE        (0x1FF800CCUL)                  /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define UID_BASE              (0x1FF800D0UL)                  /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000UL)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400UL)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058UL)
-#define AES_BASE              (0x50060000UL)
-#define DBGMCU_BASE           (0xE0042000UL)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-/* Legacy define */
-#define DAC                 DAC1
-
-#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
-#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
-
-#define RI                  ((RI_TypeDef *) RI_BASE)
-
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
-#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
-/* Legacy defines */
-#define ADC                 ADC1_COMMON
-
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define AES                 ((AES_TypeDef *) AES_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-  /** @addtogroup Hardware_Constant_Definition
-    * @{
-    */
-#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
-
-  /**
-    * @}
-    */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-#define VREFINT_CAL_ADDR_CMSIS                    0x1FF800F8      /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV).                      */
-#define TEMPSENSOR_CAL1_ADDR_CMSIS                0x1FF800FA      /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR_CMSIS                0x1FF800FE      /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos                       (0U)                              
-#define ADC_SR_AWD_Msk                       (0x1UL << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
-#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOCS_Pos                      (1U)                              
-#define ADC_SR_EOCS_Msk                      (0x1UL << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
-#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos                      (2U)                              
-#define ADC_SR_JEOS_Msk                      (0x1UL << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
-#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos                     (3U)                              
-#define ADC_SR_JSTRT_Msk                     (0x1UL << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
-#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos                      (4U)                              
-#define ADC_SR_STRT_Msk                      (0x1UL << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
-#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
-#define ADC_SR_OVR_Pos                       (5U)                              
-#define ADC_SR_OVR_Msk                       (0x1UL << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
-#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
-#define ADC_SR_ADONS_Pos                     (6U)                              
-#define ADC_SR_ADONS_Msk                     (0x1UL << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
-#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
-#define ADC_SR_RCNR_Pos                      (8U)                              
-#define ADC_SR_RCNR_Msk                      (0x1UL << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
-#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
-#define ADC_SR_JCNR_Pos                      (9U)                              
-#define ADC_SR_JCNR_Msk                      (0x1UL << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
-#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
-
-/* Legacy defines */
-#define  ADC_SR_EOC                          (ADC_SR_EOCS)
-#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos                    (0U)                              
-#define ADC_CR1_AWDCH_Msk                    (0x1FUL << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
-#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0                      (0x01UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1                      (0x02UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2                      (0x04UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3                      (0x08UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4                      (0x10UL << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
-
-#define ADC_CR1_EOCSIE_Pos                   (5U)                              
-#define ADC_CR1_EOCSIE_Msk                   (0x1UL << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
-#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos                    (6U)                              
-#define ADC_CR1_AWDIE_Msk                    (0x1UL << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
-#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos                   (7U)                              
-#define ADC_CR1_JEOSIE_Msk                   (0x1UL << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos                     (8U)                              
-#define ADC_CR1_SCAN_Msk                     (0x1UL << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
-#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos                   (9U)                              
-#define ADC_CR1_AWDSGL_Msk                   (0x1UL << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos                    (10U)                             
-#define ADC_CR1_JAUTO_Msk                    (0x1UL << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
-#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos                   (11U)                             
-#define ADC_CR1_DISCEN_Msk                   (0x1UL << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
-#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos                  (12U)                             
-#define ADC_CR1_JDISCEN_Msk                  (0x1UL << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos                  (13U)                             
-#define ADC_CR1_DISCNUM_Msk                  (0x7UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0                    (0x1UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1                    (0x2UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2                    (0x4UL << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
-
-#define ADC_CR1_PDD_Pos                      (16U)                             
-#define ADC_CR1_PDD_Msk                      (0x1UL << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
-#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
-#define ADC_CR1_PDI_Pos                      (17U)                             
-#define ADC_CR1_PDI_Msk                      (0x1UL << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
-#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
-
-#define ADC_CR1_JAWDEN_Pos                   (22U)                             
-#define ADC_CR1_JAWDEN_Msk                   (0x1UL << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos                    (23U)                             
-#define ADC_CR1_AWDEN_Msk                    (0x1UL << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
-#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CR1_RES_Pos                      (24U)                             
-#define ADC_CR1_RES_Msk                      (0x3UL << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
-#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
-#define ADC_CR1_RES_0                        (0x1UL << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
-#define ADC_CR1_RES_1                        (0x2UL << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
-
-#define ADC_CR1_OVRIE_Pos                    (26U)                             
-#define ADC_CR1_OVRIE_Msk                    (0x1UL << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
-#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
-
-/* Legacy defines */
-#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
-#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
-
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos                     (0U)                              
-#define ADC_CR2_ADON_Msk                     (0x1UL << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
-#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
-#define ADC_CR2_CONT_Pos                     (1U)                              
-#define ADC_CR2_CONT_Msk                     (0x1UL << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
-#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CFG_Pos                      (2U)                              
-#define ADC_CR2_CFG_Msk                      (0x1UL << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
-#define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
-
-#define ADC_CR2_DELS_Pos                     (4U)                              
-#define ADC_CR2_DELS_Msk                     (0x7UL << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
-#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
-#define ADC_CR2_DELS_0                       (0x1UL << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
-#define ADC_CR2_DELS_1                       (0x2UL << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
-#define ADC_CR2_DELS_2                       (0x4UL << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
-
-#define ADC_CR2_DMA_Pos                      (8U)                              
-#define ADC_CR2_DMA_Msk                      (0x1UL << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
-#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
-#define ADC_CR2_DDS_Pos                      (9U)                              
-#define ADC_CR2_DDS_Msk                      (0x1UL << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
-#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
-#define ADC_CR2_EOCS_Pos                     (10U)                             
-#define ADC_CR2_EOCS_Msk                     (0x1UL << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
-#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
-#define ADC_CR2_ALIGN_Pos                    (11U)                             
-#define ADC_CR2_ALIGN_Msk                    (0x1UL << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
-#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos                  (16U)                             
-#define ADC_CR2_JEXTSEL_Msk                  (0xFUL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0                    (0x1UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1                    (0x2UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2                    (0x4UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3                    (0x8UL << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
-
-#define ADC_CR2_JEXTEN_Pos                   (20U)                             
-#define ADC_CR2_JEXTEN_Msk                   (0x3UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
-#define ADC_CR2_JEXTEN_0                     (0x1UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1                     (0x2UL << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
-
-#define ADC_CR2_JSWSTART_Pos                 (22U)                             
-#define ADC_CR2_JSWSTART_Msk                 (0x1UL << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
-
-#define ADC_CR2_EXTSEL_Pos                   (24U)                             
-#define ADC_CR2_EXTSEL_Msk                   (0xFUL << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0                     (0x1UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1                     (0x2UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2                     (0x4UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3                     (0x8UL << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
-
-#define ADC_CR2_EXTEN_Pos                    (28U)                             
-#define ADC_CR2_EXTEN_Msk                    (0x3UL << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
-#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
-#define ADC_CR2_EXTEN_0                      (0x1UL << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1                      (0x2UL << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
-
-#define ADC_CR2_SWSTART_Pos                  (30U)                             
-#define ADC_CR2_SWSTART_Msk                  (0x1UL << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
-#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP20_Pos                  (0U)                              
-#define ADC_SMPR1_SMP20_Msk                  (0x7UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
-#define ADC_SMPR1_SMP20_0                    (0x1UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR1_SMP20_1                    (0x2UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR1_SMP20_2                    (0x4UL << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP21_Pos                  (3U)                              
-#define ADC_SMPR1_SMP21_Msk                  (0x7UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
-#define ADC_SMPR1_SMP21_0                    (0x1UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR1_SMP21_1                    (0x2UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR1_SMP21_2                    (0x4UL << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP22_Pos                  (6U)                              
-#define ADC_SMPR1_SMP22_Msk                  (0x7UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
-#define ADC_SMPR1_SMP22_0                    (0x1UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR1_SMP22_1                    (0x2UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR1_SMP22_2                    (0x4UL << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP23_Pos                  (9U)                              
-#define ADC_SMPR1_SMP23_Msk                  (0x7UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
-#define ADC_SMPR1_SMP23_0                    (0x1UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR1_SMP23_1                    (0x2UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR1_SMP23_2                    (0x4UL << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP24_Pos                  (12U)                             
-#define ADC_SMPR1_SMP24_Msk                  (0x7UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
-#define ADC_SMPR1_SMP24_0                    (0x1UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR1_SMP24_1                    (0x2UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR1_SMP24_2                    (0x4UL << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP25_Pos                  (15U)                             
-#define ADC_SMPR1_SMP25_Msk                  (0x7UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
-#define ADC_SMPR1_SMP25_0                    (0x1UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR1_SMP25_1                    (0x2UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR1_SMP25_2                    (0x4UL << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP26_Pos                  (18U)                             
-#define ADC_SMPR1_SMP26_Msk                  (0x7UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
-#define ADC_SMPR1_SMP26_0                    (0x1UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR1_SMP26_1                    (0x2UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR1_SMP26_2                    (0x4UL << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP27_Pos                  (21U)                             
-#define ADC_SMPR1_SMP27_Msk                  (0x7UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP27                      ADC_SMPR1_SMP27_Msk               /*!< ADC channel 27 sampling time selection */
-#define ADC_SMPR1_SMP27_0                    (0x1UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR1_SMP27_1                    (0x2UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR1_SMP27_2                    (0x4UL << ADC_SMPR1_SMP27_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR1_SMP28_Pos                  (24U)                             
-#define ADC_SMPR1_SMP28_Msk                  (0x7UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR1_SMP28                      ADC_SMPR1_SMP28_Msk               /*!< ADC channel 28 sampling time selection */
-#define ADC_SMPR1_SMP28_0                    (0x1UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR1_SMP28_1                    (0x2UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR1_SMP28_2                    (0x4UL << ADC_SMPR1_SMP28_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR1_SMP29_Pos                  (27U)                             
-#define ADC_SMPR1_SMP29_Msk                  (0x7UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR1_SMP29                      ADC_SMPR1_SMP29_Msk               /*!< ADC channel 29 sampling time selection */
-#define ADC_SMPR1_SMP29_0                    (0x1UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR1_SMP29_1                    (0x2UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR1_SMP29_2                    (0x4UL << ADC_SMPR1_SMP29_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP10_Pos                  (0U)                              
-#define ADC_SMPR2_SMP10_Msk                  (0x7UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR2_SMP10_0                    (0x1UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR2_SMP10_1                    (0x2UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR2_SMP10_2                    (0x4UL << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP11_Pos                  (3U)                              
-#define ADC_SMPR2_SMP11_Msk                  (0x7UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR2_SMP11_0                    (0x1UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR2_SMP11_1                    (0x2UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR2_SMP11_2                    (0x4UL << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP12_Pos                  (6U)                              
-#define ADC_SMPR2_SMP12_Msk                  (0x7UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR2_SMP12_0                    (0x1UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
-#define ADC_SMPR2_SMP12_1                    (0x2UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
-#define ADC_SMPR2_SMP12_2                    (0x4UL << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP13_Pos                  (9U)                              
-#define ADC_SMPR2_SMP13_Msk                  (0x7UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR2_SMP13_0                    (0x1UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
-#define ADC_SMPR2_SMP13_1                    (0x2UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
-#define ADC_SMPR2_SMP13_2                    (0x4UL << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP14_Pos                  (12U)                             
-#define ADC_SMPR2_SMP14_Msk                  (0x7UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
-#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR2_SMP14_0                    (0x1UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
-#define ADC_SMPR2_SMP14_1                    (0x2UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
-#define ADC_SMPR2_SMP14_2                    (0x4UL << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP15_Pos                  (15U)                             
-#define ADC_SMPR2_SMP15_Msk                  (0x7UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
-#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP15_0                    (0x1UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
-#define ADC_SMPR2_SMP15_1                    (0x2UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
-#define ADC_SMPR2_SMP15_2                    (0x4UL << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP16_Pos                  (18U)                             
-#define ADC_SMPR2_SMP16_Msk                  (0x7UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR2_SMP16_0                    (0x1UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
-#define ADC_SMPR2_SMP16_1                    (0x2UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
-#define ADC_SMPR2_SMP16_2                    (0x4UL << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP17_Pos                  (21U)                             
-#define ADC_SMPR2_SMP17_Msk                  (0x7UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR2_SMP17_0                    (0x1UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
-#define ADC_SMPR2_SMP17_1                    (0x2UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
-#define ADC_SMPR2_SMP17_2                    (0x4UL << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP18_Pos                  (24U)                             
-#define ADC_SMPR2_SMP18_Msk                  (0x7UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
-#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
-#define ADC_SMPR2_SMP18_0                    (0x1UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
-#define ADC_SMPR2_SMP18_1                    (0x2UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
-#define ADC_SMPR2_SMP18_2                    (0x4UL << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP19_Pos                  (27U)                             
-#define ADC_SMPR2_SMP19_Msk                  (0x7UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
-#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
-#define ADC_SMPR2_SMP19_0                    (0x1UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
-#define ADC_SMPR2_SMP19_1                    (0x2UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
-#define ADC_SMPR2_SMP19_2                    (0x4UL << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define ADC_SMPR3_SMP0_Pos                   (0U)                              
-#define ADC_SMPR3_SMP0_Msk                   (0x7UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
-#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR3_SMP0_0                     (0x1UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
-#define ADC_SMPR3_SMP0_1                     (0x2UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
-#define ADC_SMPR3_SMP0_2                     (0x4UL << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
- 
-#define ADC_SMPR3_SMP1_Pos                   (3U)                              
-#define ADC_SMPR3_SMP1_Msk                   (0x7UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
-#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR3_SMP1_0                     (0x1UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
-#define ADC_SMPR3_SMP1_1                     (0x2UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
-#define ADC_SMPR3_SMP1_2                     (0x4UL << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
-
-#define ADC_SMPR3_SMP2_Pos                   (6U)                              
-#define ADC_SMPR3_SMP2_Msk                   (0x7UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
-#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR3_SMP2_0                     (0x1UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
-#define ADC_SMPR3_SMP2_1                     (0x2UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
-#define ADC_SMPR3_SMP2_2                     (0x4UL << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
-
-#define ADC_SMPR3_SMP3_Pos                   (9U)                              
-#define ADC_SMPR3_SMP3_Msk                   (0x7UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
-#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR3_SMP3_0                     (0x1UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
-#define ADC_SMPR3_SMP3_1                     (0x2UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
-#define ADC_SMPR3_SMP3_2                     (0x4UL << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
-
-#define ADC_SMPR3_SMP4_Pos                   (12U)                             
-#define ADC_SMPR3_SMP4_Msk                   (0x7UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
-#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR3_SMP4_0                     (0x1UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
-#define ADC_SMPR3_SMP4_1                     (0x2UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
-#define ADC_SMPR3_SMP4_2                     (0x4UL << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
-
-#define ADC_SMPR3_SMP5_Pos                   (15U)                             
-#define ADC_SMPR3_SMP5_Msk                   (0x7UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
-#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR3_SMP5_0                     (0x1UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
-#define ADC_SMPR3_SMP5_1                     (0x2UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
-#define ADC_SMPR3_SMP5_2                     (0x4UL << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
-
-#define ADC_SMPR3_SMP6_Pos                   (18U)                             
-#define ADC_SMPR3_SMP6_Msk                   (0x7UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
-#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR3_SMP6_0                     (0x1UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
-#define ADC_SMPR3_SMP6_1                     (0x2UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
-#define ADC_SMPR3_SMP6_2                     (0x4UL << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
-
-#define ADC_SMPR3_SMP7_Pos                   (21U)                             
-#define ADC_SMPR3_SMP7_Msk                   (0x7UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
-#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR3_SMP7_0                     (0x1UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
-#define ADC_SMPR3_SMP7_1                     (0x2UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
-#define ADC_SMPR3_SMP7_2                     (0x4UL << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
-
-#define ADC_SMPR3_SMP8_Pos                   (24U)                             
-#define ADC_SMPR3_SMP8_Msk                   (0x7UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
-#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR3_SMP8_0                     (0x1UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
-#define ADC_SMPR3_SMP8_1                     (0x2UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
-#define ADC_SMPR3_SMP8_2                     (0x4UL << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
-
-#define ADC_SMPR3_SMP9_Pos                   (27U)                             
-#define ADC_SMPR3_SMP9_Msk                   (0x7UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
-#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR3_SMP9_0                     (0x1UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
-#define ADC_SMPR3_SMP9_1                     (0x2UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
-#define ADC_SMPR3_SMP9_2                     (0x4UL << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos               (0U)                              
-#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos               (0U)                              
-#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos               (0U)                              
-#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos               (0U)                              
-#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos                       (0U)                              
-#define ADC_HTR_HT_Msk                       (0xFFFUL << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
-#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos                       (0U)                              
-#define ADC_LTR_LT_Msk                       (0xFFFUL << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
-#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_L_Pos                       (20U)                             
-#define ADC_SQR1_L_Msk                       (0x1FUL << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
-#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0                         (0x01UL << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
-#define ADC_SQR1_L_1                         (0x02UL << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
-#define ADC_SQR1_L_2                         (0x04UL << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
-#define ADC_SQR1_L_3                         (0x08UL << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
-#define ADC_SQR1_L_4                         (0x10UL << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
-
-#define ADC_SQR1_SQ28_Pos                    (15U)                             
-#define ADC_SQR1_SQ28_Msk                    (0x1FUL << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
-#define ADC_SQR1_SQ28_0                      (0x01UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
-#define ADC_SQR1_SQ28_1                      (0x02UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
-#define ADC_SQR1_SQ28_2                      (0x04UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
-#define ADC_SQR1_SQ28_3                      (0x08UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
-#define ADC_SQR1_SQ28_4                      (0x10UL << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR1_SQ27_Pos                    (10U)                             
-#define ADC_SQR1_SQ27_Msk                    (0x1FUL << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
-#define ADC_SQR1_SQ27_0                      (0x01UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
-#define ADC_SQR1_SQ27_1                      (0x02UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
-#define ADC_SQR1_SQ27_2                      (0x04UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
-#define ADC_SQR1_SQ27_3                      (0x08UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
-#define ADC_SQR1_SQ27_4                      (0x10UL << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ26_Pos                    (5U)                              
-#define ADC_SQR1_SQ26_Msk                    (0x1FUL << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
-#define ADC_SQR1_SQ26_0                      (0x01UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
-#define ADC_SQR1_SQ26_1                      (0x02UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
-#define ADC_SQR1_SQ26_2                      (0x04UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
-#define ADC_SQR1_SQ26_3                      (0x08UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
-#define ADC_SQR1_SQ26_4                      (0x10UL << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ25_Pos                    (0U)                              
-#define ADC_SQR1_SQ25_Msk                    (0x1FUL << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
-#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
-#define ADC_SQR1_SQ25_0                      (0x01UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
-#define ADC_SQR1_SQ25_1                      (0x02UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
-#define ADC_SQR1_SQ25_2                      (0x04UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
-#define ADC_SQR1_SQ25_3                      (0x08UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
-#define ADC_SQR1_SQ25_4                      (0x10UL << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ19_Pos                    (0U)                              
-#define ADC_SQR2_SQ19_Msk                    (0x1FUL << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
-#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
-#define ADC_SQR2_SQ19_0                      (0x01UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
-#define ADC_SQR2_SQ19_1                      (0x02UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
-#define ADC_SQR2_SQ19_2                      (0x04UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
-#define ADC_SQR2_SQ19_3                      (0x08UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
-#define ADC_SQR2_SQ19_4                      (0x10UL << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ20_Pos                    (5U)                              
-#define ADC_SQR2_SQ20_Msk                    (0x1FUL << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
-#define ADC_SQR2_SQ20_0                      (0x01UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
-#define ADC_SQR2_SQ20_1                      (0x02UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
-#define ADC_SQR2_SQ20_2                      (0x04UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
-#define ADC_SQR2_SQ20_3                      (0x08UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
-#define ADC_SQR2_SQ20_4                      (0x10UL << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ21_Pos                    (10U)                             
-#define ADC_SQR2_SQ21_Msk                    (0x1FUL << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
-#define ADC_SQR2_SQ21_0                      (0x01UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
-#define ADC_SQR2_SQ21_1                      (0x02UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
-#define ADC_SQR2_SQ21_2                      (0x04UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
-#define ADC_SQR2_SQ21_3                      (0x08UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
-#define ADC_SQR2_SQ21_4                      (0x10UL << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ22_Pos                    (15U)                             
-#define ADC_SQR2_SQ22_Msk                    (0x1FUL << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
-#define ADC_SQR2_SQ22_0                      (0x01UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
-#define ADC_SQR2_SQ22_1                      (0x02UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
-#define ADC_SQR2_SQ22_2                      (0x04UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
-#define ADC_SQR2_SQ22_3                      (0x08UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
-#define ADC_SQR2_SQ22_4                      (0x10UL << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ23_Pos                    (20U)                             
-#define ADC_SQR2_SQ23_Msk                    (0x1FUL << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
-#define ADC_SQR2_SQ23_0                      (0x01UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
-#define ADC_SQR2_SQ23_1                      (0x02UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
-#define ADC_SQR2_SQ23_2                      (0x04UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
-#define ADC_SQR2_SQ23_3                      (0x08UL << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
-#define ADC_SQR2_SQ23_4                      (0x10UL << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ24_Pos                    (25U)                             
-#define ADC_SQR2_SQ24_Msk                    (0x1FUL << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
-#define ADC_SQR2_SQ24_0                      (0x01UL << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
-#define ADC_SQR2_SQ24_1                      (0x02UL << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
-#define ADC_SQR2_SQ24_2                      (0x04UL << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
-#define ADC_SQR2_SQ24_3                      (0x08UL << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
-#define ADC_SQR2_SQ24_4                      (0x10UL << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ13_Pos                    (0U)                              
-#define ADC_SQR3_SQ13_Msk                    (0x1FUL << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
-#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR3_SQ13_0                      (0x01UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
-#define ADC_SQR3_SQ13_1                      (0x02UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
-#define ADC_SQR3_SQ13_2                      (0x04UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
-#define ADC_SQR3_SQ13_3                      (0x08UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
-#define ADC_SQR3_SQ13_4                      (0x10UL << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ14_Pos                    (5U)                              
-#define ADC_SQR3_SQ14_Msk                    (0x1FUL << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
-#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR3_SQ14_0                      (0x01UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
-#define ADC_SQR3_SQ14_1                      (0x02UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
-#define ADC_SQR3_SQ14_2                      (0x04UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
-#define ADC_SQR3_SQ14_3                      (0x08UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
-#define ADC_SQR3_SQ14_4                      (0x10UL << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ15_Pos                    (10U)                             
-#define ADC_SQR3_SQ15_Msk                    (0x1FUL << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
-#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR3_SQ15_0                      (0x01UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
-#define ADC_SQR3_SQ15_1                      (0x02UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
-#define ADC_SQR3_SQ15_2                      (0x04UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
-#define ADC_SQR3_SQ15_3                      (0x08UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
-#define ADC_SQR3_SQ15_4                      (0x10UL << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ16_Pos                    (15U)                             
-#define ADC_SQR3_SQ16_Msk                    (0x1FUL << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR3_SQ16_0                      (0x01UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
-#define ADC_SQR3_SQ16_1                      (0x02UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
-#define ADC_SQR3_SQ16_2                      (0x04UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
-#define ADC_SQR3_SQ16_3                      (0x08UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
-#define ADC_SQR3_SQ16_4                      (0x10UL << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ17_Pos                    (20U)                             
-#define ADC_SQR3_SQ17_Msk                    (0x1FUL << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
-#define ADC_SQR3_SQ17_0                      (0x01UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
-#define ADC_SQR3_SQ17_1                      (0x02UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
-#define ADC_SQR3_SQ17_2                      (0x04UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
-#define ADC_SQR3_SQ17_3                      (0x08UL << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
-#define ADC_SQR3_SQ17_4                      (0x10UL << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ18_Pos                    (25U)                             
-#define ADC_SQR3_SQ18_Msk                    (0x1FUL << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
-#define ADC_SQR3_SQ18_0                      (0x01UL << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
-#define ADC_SQR3_SQ18_1                      (0x02UL << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
-#define ADC_SQR3_SQ18_2                      (0x04UL << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
-#define ADC_SQR3_SQ18_3                      (0x08UL << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
-#define ADC_SQR3_SQ18_4                      (0x10UL << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define ADC_SQR4_SQ7_Pos                     (0U)                              
-#define ADC_SQR4_SQ7_Msk                     (0x1FUL << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
-#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR4_SQ7_0                       (0x01UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
-#define ADC_SQR4_SQ7_1                       (0x02UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
-#define ADC_SQR4_SQ7_2                       (0x04UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
-#define ADC_SQR4_SQ7_3                       (0x08UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
-#define ADC_SQR4_SQ7_4                       (0x10UL << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR4_SQ8_Pos                     (5U)                              
-#define ADC_SQR4_SQ8_Msk                     (0x1FUL << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR4_SQ8_0                       (0x01UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
-#define ADC_SQR4_SQ8_1                       (0x02UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
-#define ADC_SQR4_SQ8_2                       (0x04UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
-#define ADC_SQR4_SQ8_3                       (0x08UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
-#define ADC_SQR4_SQ8_4                       (0x10UL << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR4_SQ9_Pos                     (10U)                             
-#define ADC_SQR4_SQ9_Msk                     (0x1FUL << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR4_SQ9_0                       (0x01UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
-#define ADC_SQR4_SQ9_1                       (0x02UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
-#define ADC_SQR4_SQ9_2                       (0x04UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
-#define ADC_SQR4_SQ9_3                       (0x08UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
-#define ADC_SQR4_SQ9_4                       (0x10UL << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR4_SQ10_Pos                    (15U)                             
-#define ADC_SQR4_SQ10_Msk                    (0x1FUL << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
-#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR4_SQ10_0                      (0x01UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
-#define ADC_SQR4_SQ10_1                      (0x02UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
-#define ADC_SQR4_SQ10_2                      (0x04UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
-#define ADC_SQR4_SQ10_3                      (0x08UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
-#define ADC_SQR4_SQ10_4                      (0x10UL << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
-
-#define ADC_SQR4_SQ11_Pos                    (20U)                             
-#define ADC_SQR4_SQ11_Msk                    (0x1FUL << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
-#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
-#define ADC_SQR4_SQ11_0                      (0x01UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
-#define ADC_SQR4_SQ11_1                      (0x02UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
-#define ADC_SQR4_SQ11_2                      (0x04UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
-#define ADC_SQR4_SQ11_3                      (0x08UL << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
-#define ADC_SQR4_SQ11_4                      (0x10UL << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
-
-#define ADC_SQR4_SQ12_Pos                    (25U)                             
-#define ADC_SQR4_SQ12_Msk                    (0x1FUL << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
-#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR4_SQ12_0                      (0x01UL << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
-#define ADC_SQR4_SQ12_1                      (0x02UL << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
-#define ADC_SQR4_SQ12_2                      (0x04UL << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
-#define ADC_SQR4_SQ12_3                      (0x08UL << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
-#define ADC_SQR4_SQ12_4                      (0x10UL << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define ADC_SQR5_SQ1_Pos                     (0U)                              
-#define ADC_SQR5_SQ1_Msk                     (0x1FUL << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
-#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR5_SQ1_0                       (0x01UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
-#define ADC_SQR5_SQ1_1                       (0x02UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
-#define ADC_SQR5_SQ1_2                       (0x04UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
-#define ADC_SQR5_SQ1_3                       (0x08UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
-#define ADC_SQR5_SQ1_4                       (0x10UL << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
-
-#define ADC_SQR5_SQ2_Pos                     (5U)                              
-#define ADC_SQR5_SQ2_Msk                     (0x1FUL << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
-#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR5_SQ2_0                       (0x01UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
-#define ADC_SQR5_SQ2_1                       (0x02UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
-#define ADC_SQR5_SQ2_2                       (0x04UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
-#define ADC_SQR5_SQ2_3                       (0x08UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
-#define ADC_SQR5_SQ2_4                       (0x10UL << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
-
-#define ADC_SQR5_SQ3_Pos                     (10U)                             
-#define ADC_SQR5_SQ3_Msk                     (0x1FUL << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
-#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR5_SQ3_0                       (0x01UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
-#define ADC_SQR5_SQ3_1                       (0x02UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
-#define ADC_SQR5_SQ3_2                       (0x04UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
-#define ADC_SQR5_SQ3_3                       (0x08UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
-#define ADC_SQR5_SQ3_4                       (0x10UL << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
-
-#define ADC_SQR5_SQ4_Pos                     (15U)                             
-#define ADC_SQR5_SQ4_Msk                     (0x1FUL << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
-#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR5_SQ4_0                       (0x01UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
-#define ADC_SQR5_SQ4_1                       (0x02UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
-#define ADC_SQR5_SQ4_2                       (0x04UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
-#define ADC_SQR5_SQ4_3                       (0x08UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
-#define ADC_SQR5_SQ4_4                       (0x10UL << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
-
-#define ADC_SQR5_SQ5_Pos                     (20U)                             
-#define ADC_SQR5_SQ5_Msk                     (0x1FUL << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
-#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR5_SQ5_0                       (0x01UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
-#define ADC_SQR5_SQ5_1                       (0x02UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
-#define ADC_SQR5_SQ5_2                       (0x04UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
-#define ADC_SQR5_SQ5_3                       (0x08UL << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
-#define ADC_SQR5_SQ5_4                       (0x10UL << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
-
-#define ADC_SQR5_SQ6_Pos                     (25U)                             
-#define ADC_SQR5_SQ6_Msk                     (0x1FUL << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
-#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR5_SQ6_0                       (0x01UL << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
-#define ADC_SQR5_SQ6_1                       (0x02UL << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
-#define ADC_SQR5_SQ6_2                       (0x04UL << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
-#define ADC_SQR5_SQ6_3                       (0x08UL << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
-#define ADC_SQR5_SQ6_4                       (0x10UL << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos                    (0U)                              
-#define ADC_JSQR_JSQ1_Msk                    (0x1FUL << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0                      (0x01UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1                      (0x02UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2                      (0x04UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3                      (0x08UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4                      (0x10UL << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos                    (5U)                              
-#define ADC_JSQR_JSQ2_Msk                    (0x1FUL << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0                      (0x01UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1                      (0x02UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2                      (0x04UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3                      (0x08UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4                      (0x10UL << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos                    (10U)                             
-#define ADC_JSQR_JSQ3_Msk                    (0x1FUL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0                      (0x01UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1                      (0x02UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2                      (0x04UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3                      (0x08UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4                      (0x10UL << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos                    (15U)                             
-#define ADC_JSQR_JSQ4_Msk                    (0x1FUL << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0                      (0x01UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1                      (0x02UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2                      (0x04UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3                      (0x08UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4                      (0x10UL << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos                      (20U)                             
-#define ADC_JSQR_JL_Msk                      (0x3UL << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
-#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0                        (0x1UL << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
-#define ADC_JSQR_JL_1                        (0x2UL << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos                   (0U)                              
-#define ADC_JDR1_JDATA_Msk                   (0xFFFFUL << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos                   (0U)                              
-#define ADC_JDR2_JDATA_Msk                   (0xFFFFUL << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos                   (0U)                              
-#define ADC_JDR3_JDATA_Msk                   (0xFFFFUL << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos                   (0U)                              
-#define ADC_JDR4_JDATA_Msk                   (0xFFFFUL << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                      (0U)                              
-#define ADC_DR_DATA_Msk                      (0xFFFFUL << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
-#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define ADC_SMPR0_SMP30_Pos                  (0U)                              
-#define ADC_SMPR0_SMP30_Msk                  (0x7UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000007 */
-#define ADC_SMPR0_SMP30                      ADC_SMPR0_SMP30_Msk               /*!< ADC channel 30 sampling time selection */
-#define ADC_SMPR0_SMP30_0                    (0x1UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000001 */
-#define ADC_SMPR0_SMP30_1                    (0x2UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000002 */
-#define ADC_SMPR0_SMP30_2                    (0x4UL << ADC_SMPR0_SMP30_Pos)     /*!< 0x00000004 */
- 
-#define ADC_SMPR0_SMP31_Pos                  (3U)                              
-#define ADC_SMPR0_SMP31_Msk                  (0x7UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000038 */
-#define ADC_SMPR0_SMP31                      ADC_SMPR0_SMP31_Msk               /*!< ADC channel 31 sampling time selection */
-#define ADC_SMPR0_SMP31_0                    (0x1UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000008 */
-#define ADC_SMPR0_SMP31_1                    (0x2UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000010 */
-#define ADC_SMPR0_SMP31_2                    (0x4UL << ADC_SMPR0_SMP31_Pos)     /*!< 0x00000020 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos                     (0U)                              
-#define ADC_CSR_AWD1_Msk                     (0x1UL << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
-#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
-#define ADC_CSR_EOCS1_Pos                    (1U)                              
-#define ADC_CSR_EOCS1_Msk                    (0x1UL << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
-#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
-#define ADC_CSR_JEOS1_Pos                    (2U)                              
-#define ADC_CSR_JEOS1_Msk                    (0x1UL << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
-#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
-#define ADC_CSR_JSTRT1_Pos                   (3U)                              
-#define ADC_CSR_JSTRT1_Msk                   (0x1UL << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
-#define ADC_CSR_STRT1_Pos                    (4U)                              
-#define ADC_CSR_STRT1_Msk                    (0x1UL << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
-#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
-#define ADC_CSR_OVR1_Pos                     (5U)                              
-#define ADC_CSR_OVR1_Msk                     (0x1UL << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
-#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
-#define ADC_CSR_ADONS1_Pos                   (6U)                              
-#define ADC_CSR_ADONS1_Msk                   (0x1UL << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
-#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
-
-/* Legacy defines */
-#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
-#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_ADCPRE_Pos                   (16U)                             
-#define ADC_CCR_ADCPRE_Msk                   (0x3UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
-#define ADC_CCR_ADCPRE_0                     (0x1UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1                     (0x2UL << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
-#define ADC_CCR_TSVREFE_Pos                  (23U)                             
-#define ADC_CCR_TSVREFE_Msk                  (0x1UL << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos                       (0U)                               
-#define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)            /*!< 0x00000001 */
-#define AES_CR_EN                           AES_CR_EN_Msk                      /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos                 (1U)                               
-#define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000006 */
-#define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                /*!< Data type selection */
-#define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)      /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos                     (3U)                               
-#define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)          /*!< 0x00000018 */
-#define AES_CR_MODE                         AES_CR_MODE_Msk                    /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)          /*!< 0x00000008 */
-#define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)          /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos                    (5U)                               
-#define AES_CR_CHMOD_Msk                    (0x3UL << AES_CR_CHMOD_Pos)         /*!< 0x00000060 */
-#define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                   /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0                      (0x1UL << AES_CR_CHMOD_Pos)         /*!< 0x00000020 */
-#define AES_CR_CHMOD_1                      (0x2UL << AES_CR_CHMOD_Pos)         /*!< 0x00000040 */
-
-#define AES_CR_CCFC_Pos                     (7U)                               
-#define AES_CR_CCFC_Msk                     (0x1UL << AES_CR_CCFC_Pos)          /*!< 0x00000080 */
-#define AES_CR_CCFC                         AES_CR_CCFC_Msk                    /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos                     (8U)                               
-#define AES_CR_ERRC_Msk                     (0x1UL << AES_CR_ERRC_Pos)          /*!< 0x00000100 */
-#define AES_CR_ERRC                         AES_CR_ERRC_Msk                    /*!< Error Clear */
-#define AES_CR_CCIE_Pos                     (9U)                               
-#define AES_CR_CCIE_Msk                     (0x1UL << AES_CR_CCIE_Pos)          /*!< 0x00000200 */
-#define AES_CR_CCIE                         AES_CR_CCIE_Msk                    /*!< Computation Complete Interrupt Enable */
-#define AES_CR_ERRIE_Pos                    (10U)                              
-#define AES_CR_ERRIE_Msk                    (0x1UL << AES_CR_ERRIE_Pos)         /*!< 0x00000400 */
-#define AES_CR_ERRIE                        AES_CR_ERRIE_Msk                   /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos                  (11U)                              
-#define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)       /*!< 0x00000800 */
-#define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                 /*!< DMA ENable managing the data input phase */
-#define AES_CR_DMAOUTEN_Pos                 (12U)                              
-#define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)      /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                /*!< DMA Enable managing the data output phase */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos                      (0U)                               
-#define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)           /*!< 0x00000001 */
-#define AES_SR_CCF                          AES_SR_CCF_Msk                     /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos                    (1U)                               
-#define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)         /*!< 0x00000002 */
-#define AES_SR_RDERR                        AES_SR_RDERR_Msk                   /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos                    (2U)                               
-#define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)         /*!< 0x00000004 */
-#define AES_SR_WRERR                        AES_SR_WRERR_Msk                   /*!< Write Error Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos                        (0U)                               
-#define AES_DINR_Msk                        (0xFFFFUL << AES_DINR_Pos)          /*!< 0x0000FFFF */
-#define AES_DINR                            AES_DINR_Msk                       /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos                       (0U)                               
-#define AES_DOUTR_Msk                       (0xFFFFUL << AES_DOUTR_Pos)         /*!< 0x0000FFFF */
-#define AES_DOUTR                           AES_DOUTR_Msk                      /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos                       (0U)                               
-#define AES_KEYR0_Msk                       (0xFFFFUL << AES_KEYR0_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR0                           AES_KEYR0_Msk                      /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos                       (0U)                               
-#define AES_KEYR1_Msk                       (0xFFFFUL << AES_KEYR1_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR1                           AES_KEYR1_Msk                      /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos                       (0U)                               
-#define AES_KEYR2_Msk                       (0xFFFFUL << AES_KEYR2_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR2                           AES_KEYR2_Msk                      /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos                       (0U)                               
-#define AES_KEYR3_Msk                       (0xFFFFUL << AES_KEYR3_Pos)         /*!< 0x0000FFFF */
-#define AES_KEYR3                           AES_KEYR3_Msk                      /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_IVR0 register  *******************/
-#define AES_IVR0_Pos                        (0U)                               
-#define AES_IVR0_Msk                        (0xFFFFUL << AES_IVR0_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR0                            AES_IVR0_Msk                       /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register  *******************/
-#define AES_IVR1_Pos                        (0U)                               
-#define AES_IVR1_Msk                        (0xFFFFUL << AES_IVR1_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR1                            AES_IVR1_Msk                       /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register  *******************/
-#define AES_IVR2_Pos                        (0U)                               
-#define AES_IVR2_Msk                        (0xFFFFUL << AES_IVR2_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR2                            AES_IVR2_Msk                       /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register  *******************/
-#define AES_IVR3_Pos                        (0U)                               
-#define AES_IVR3_Msk                        (0xFFFFUL << AES_IVR3_Pos)          /*!< 0x0000FFFF */
-#define AES_IVR3                            AES_IVR3_Msk                       /*!< AES Initialization Vector Register 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
-#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
-#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
-#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
-#define COMP_CSR_CMP1EN_Pos                 (4U)                               
-#define COMP_CSR_CMP1EN_Msk                 (0x1UL << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
-#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
-#define COMP_CSR_CMP1OUT_Pos                (7U)                               
-#define COMP_CSR_CMP1OUT_Msk                (0x1UL << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
-#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
-#define COMP_CSR_SPEED_Pos                  (12U)                              
-#define COMP_CSR_SPEED_Msk                  (0x1UL << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
-#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
-#define COMP_CSR_CMP2OUT_Pos                (13U)                              
-#define COMP_CSR_CMP2OUT_Msk                (0x1UL << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
-#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
-
-#define COMP_CSR_WNDWE_Pos                  (17U)                              
-#define COMP_CSR_WNDWE_Msk                  (0x1UL << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
-#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_INSEL_Pos                  (18U)                              
-#define COMP_CSR_INSEL_Msk                  (0x7UL << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
-#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
-#define COMP_CSR_INSEL_0                    (0x1UL << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
-#define COMP_CSR_INSEL_1                    (0x2UL << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
-#define COMP_CSR_INSEL_2                    (0x4UL << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
-#define COMP_CSR_OUTSEL_Pos                 (21U)                              
-#define COMP_CSR_OUTSEL_Msk                 (0x7UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
-#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
-#define COMP_CSR_OUTSEL_0                   (0x1UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
-#define COMP_CSR_OUTSEL_1                   (0x2UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
-#define COMP_CSR_OUTSEL_2                   (0x4UL << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
-
-/* Bits present in COMP register but not related to comparator */
-/* (or partially related to comparator, in addition to other peripherals) */
-#define COMP_CSR_SW1_Pos                    (5U)                               
-#define COMP_CSR_SW1_Msk                    (0x1UL << COMP_CSR_SW1_Pos)         /*!< 0x00000020 */
-#define COMP_CSR_SW1                        COMP_CSR_SW1_Msk                   /*!< SW1 analog switch enable */
-#define COMP_CSR_VREFOUTEN_Pos              (16U)                              
-#define COMP_CSR_VREFOUTEN_Msk              (0x1UL << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
-#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
-
-#define COMP_CSR_FCH3_Pos                   (26U)                              
-#define COMP_CSR_FCH3_Msk                   (0x1UL << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
-#define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
-#define COMP_CSR_FCH8_Pos                   (27U)                              
-#define COMP_CSR_FCH8_Msk                   (0x1UL << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
-#define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
-#define COMP_CSR_RCH13_Pos                  (28U)                              
-#define COMP_CSR_RCH13_Msk                  (0x1UL << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
-#define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
-
-#define COMP_CSR_CAIE_Pos                   (29U)                              
-#define COMP_CSR_CAIE_Msk                   (0x1UL << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
-#define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
-#define COMP_CSR_CAIF_Pos                   (30U)                              
-#define COMP_CSR_CAIF_Msk                   (0x1UL << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
-#define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
-#define COMP_CSR_TSUSP_Pos                  (31U)                              
-#define COMP_CSR_TSUSP_Msk                  (0x1UL << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
-#define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD_Pos                  (0U)                             
-#define OPAMP_CSR_OPA1PD_Msk                  (0x1UL << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
-#define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1_Pos                  (1U)                             
-#define OPAMP_CSR_S3SEL1_Msk                  (0x1UL << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
-#define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1_Pos                  (2U)                             
-#define OPAMP_CSR_S4SEL1_Msk                  (0x1UL << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
-#define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1_Pos                  (3U)                             
-#define OPAMP_CSR_S5SEL1_Msk                  (0x1UL << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
-#define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1_Pos                  (4U)                             
-#define OPAMP_CSR_S6SEL1_Msk                  (0x1UL << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
-#define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L_Pos               (5U)                             
-#define OPAMP_CSR_OPA1CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
-#define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H_Pos               (6U)                             
-#define OPAMP_CSR_OPA1CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
-#define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM_Pos                 (7U)                             
-#define OPAMP_CSR_OPA1LPM_Msk                 (0x1UL << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
-#define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD_Pos                  (8U)                             
-#define OPAMP_CSR_OPA2PD_Msk                  (0x1UL << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
-#define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2_Pos                  (9U)                             
-#define OPAMP_CSR_S3SEL2_Msk                  (0x1UL << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
-#define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2_Pos                  (10U)                            
-#define OPAMP_CSR_S4SEL2_Msk                  (0x1UL << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
-#define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2_Pos                  (11U)                            
-#define OPAMP_CSR_S5SEL2_Msk                  (0x1UL << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
-#define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2_Pos                  (12U)                            
-#define OPAMP_CSR_S6SEL2_Msk                  (0x1UL << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
-#define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L_Pos               (13U)                            
-#define OPAMP_CSR_OPA2CAL_L_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
-#define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H_Pos               (14U)                            
-#define OPAMP_CSR_OPA2CAL_H_Msk               (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
-#define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM_Pos                 (15U)                            
-#define OPAMP_CSR_OPA2LPM_Msk                 (0x1UL << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
-#define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1_Pos                (24U)                            
-#define OPAMP_CSR_ANAWSEL1_Msk                (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
-#define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2_Pos                (25U)                            
-#define OPAMP_CSR_ANAWSEL2_Msk                (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
-#define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2_Pos                  (27U)                            
-#define OPAMP_CSR_S7SEL2_Msk                  (0x1UL << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
-#define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE_Pos               (28U)                            
-#define OPAMP_CSR_AOP_RANGE_Msk               (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
-#define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
-#define OPAMP_CSR_OPA1CALOUT_Pos              (29U)                            
-#define OPAMP_CSR_OPA1CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
-#define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT_Pos              (30U)                            
-#define OPAMP_CSR_OPA2CALOUT_Msk              (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
-#define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)                             
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)                            
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)                            
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)                           
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER_Pos                 (31U)                            
-#define OPAMP_OTR_OT_USER_Msk                 (0x1UL << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
-#define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)                          
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)                         
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)                         
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)                        
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos                       (0U)                               
-#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos                     (0U)                               
-#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
-#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos                    (0U)                               
-#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
-#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos                      (0U)                               
-#define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
-#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos                    (1U)                               
-#define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
-#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos                     (2U)                               
-#define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
-#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos                    (3U)                               
-#define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
-#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos                    (6U)                               
-#define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos                    (8U)                               
-#define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos                   (12U)                              
-#define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
-#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos                (13U)                              
-#define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
-#define DAC_CR_EN2_Pos                      (16U)                              
-#define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
-#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos                    (17U)                              
-#define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
-#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos                     (18U)                              
-#define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
-#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos                    (19U)                              
-#define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
-#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos                    (22U)                              
-#define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos                    (24U)                              
-#define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos                   (28U)                              
-#define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
-#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos                (29U)                              
-#define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)                               
-#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)                               
-#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos            (0U)                               
-#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos            (4U)                               
-#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos             (0U)                               
-#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos            (0U)                               
-#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos            (16U)                              
-#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos            (4U)                               
-#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos            (20U)                              
-#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos             (0U)                               
-#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos             (8U)                               
-#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos               (0U)                               
-#define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos               (0U)                               
-#define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos                  (13U)                              
-#define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos                  (29U)                              
-#define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)                          
-#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)                         
-#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0                   (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1                   (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2                   (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3                   (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4                   (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5                   (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6                   (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7                   (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8                   (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9                   (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10                  (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11                  (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12                  (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13                  (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14                  (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15                  (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)                          
-#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos                   (1U)                          
-#define DBGMCU_CR_DBG_STOP_Msk                   (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)                          
-#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)                          
-#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)                          
-#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0                   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)                          
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)                         
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)                         
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)                         
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)                        
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)                          
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos                    (0U)                               
-#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
-#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos                   (1U)                               
-#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
-#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos                   (2U)                               
-#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
-#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos                   (3U)                               
-#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
-#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos                    (4U)                               
-#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
-#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos                   (5U)                               
-#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
-#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos                   (6U)                               
-#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
-#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos                   (7U)                               
-#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
-#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos                    (8U)                               
-#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
-#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos                   (9U)                               
-#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
-#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos                   (10U)                              
-#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
-#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos                   (11U)                              
-#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
-#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos                    (12U)                              
-#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
-#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos                   (13U)                              
-#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
-#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos                   (14U)                              
-#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
-#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos                   (15U)                              
-#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
-#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos                    (16U)                              
-#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
-#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos                   (17U)                              
-#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
-#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos                   (18U)                              
-#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
-#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos                   (19U)                              
-#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
-#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos                    (20U)                              
-#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
-#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos                   (21U)                              
-#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
-#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos                   (22U)                              
-#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
-#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos                   (23U)                              
-#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
-#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos                    (24U)                              
-#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
-#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos                   (25U)                              
-#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
-#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos                   (26U)                              
-#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
-#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos                   (27U)                              
-#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
-#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos                  (0U)                               
-#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos                 (1U)                               
-#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos                 (2U)                               
-#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos                 (3U)                               
-#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos                  (4U)                               
-#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos                 (5U)                               
-#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos                 (6U)                               
-#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos                 (7U)                               
-#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos                  (8U)                               
-#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos                 (9U)                               
-#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos                 (10U)                              
-#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos                 (11U)                              
-#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos                  (12U)                              
-#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos                 (13U)                              
-#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos                 (14U)                              
-#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos                 (15U)                              
-#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos                  (16U)                              
-#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos                 (17U)                              
-#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos                 (18U)                              
-#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos                 (19U)                              
-#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos                  (20U)                              
-#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos                 (21U)                              
-#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos                 (22U)                              
-#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos                 (23U)                              
-#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos                  (24U)                              
-#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos                 (25U)                              
-#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos                 (26U)                              
-#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos                 (27U)                              
-#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define DMA_CCR_EN_Pos                      (0U)                               
-#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
-#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
-#define DMA_CCR_TCIE_Pos                    (1U)                               
-#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
-#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos                    (2U)                               
-#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
-#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos                    (3U)                               
-#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
-#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos                     (4U)                               
-#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
-#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos                    (5U)                               
-#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
-#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
-#define DMA_CCR_PINC_Pos                    (6U)                               
-#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
-#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos                    (7U)                               
-#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
-#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos                   (8U)                               
-#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
-#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos                   (10U)                              
-#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos                      (12U)                              
-#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
-#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
-#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos                 (14U)                              
-#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
-
-/******************  Bit definition generic for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos                   (0U)                               
-#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define DMA_CNDTR1_NDT_Pos                  (0U)                               
-#define DMA_CNDTR1_NDT_Msk                  (0xFFFFUL << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define DMA_CNDTR2_NDT_Pos                  (0U)                               
-#define DMA_CNDTR2_NDT_Msk                  (0xFFFFUL << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define DMA_CNDTR3_NDT_Pos                  (0U)                               
-#define DMA_CNDTR3_NDT_Msk                  (0xFFFFUL << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define DMA_CNDTR4_NDT_Pos                  (0U)                               
-#define DMA_CNDTR4_NDT_Msk                  (0xFFFFUL << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define DMA_CNDTR5_NDT_Pos                  (0U)                               
-#define DMA_CNDTR5_NDT_Msk                  (0xFFFFUL << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define DMA_CNDTR6_NDT_Pos                  (0U)                               
-#define DMA_CNDTR6_NDT_Msk                  (0xFFFFUL << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define DMA_CNDTR7_NDT_Pos                  (0U)                               
-#define DMA_CNDTR7_NDT_Msk                  (0xFFFFUL << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
-#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
-
-/******************  Bit definition generic for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos                     (0U)                               
-#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define DMA_CPAR1_PA_Pos                    (0U)                               
-#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define DMA_CPAR2_PA_Pos                    (0U)                               
-#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define DMA_CPAR3_PA_Pos                    (0U)                               
-#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define DMA_CPAR4_PA_Pos                    (0U)                               
-#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define DMA_CPAR5_PA_Pos                    (0U)                               
-#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define DMA_CPAR6_PA_Pos                    (0U)                               
-#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define DMA_CPAR7_PA_Pos                    (0U)                               
-#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
-
-/******************  Bit definition generic for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos                     (0U)                               
-#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define DMA_CMAR1_MA_Pos                    (0U)                               
-#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define DMA_CMAR2_MA_Pos                    (0U)                               
-#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define DMA_CMAR3_MA_Pos                    (0U)                               
-#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define DMA_CMAR4_MA_Pos                    (0U)                               
-#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define DMA_CMAR5_MA_Pos                    (0U)                               
-#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define DMA_CMAR6_MA_Pos                    (0U)                               
-#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define DMA_CMAR7_MA_Pos                    (0U)                               
-#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
-#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos                    (0U)                               
-#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos                    (1U)                               
-#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos                    (2U)                               
-#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos                    (3U)                               
-#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos                    (4U)                               
-#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos                    (5U)                               
-#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos                    (6U)                               
-#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos                    (7U)                               
-#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos                    (8U)                               
-#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos                    (9U)                               
-#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos                   (10U)                              
-#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos                   (11U)                              
-#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos                   (12U)                              
-#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos                   (13U)                              
-#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos                   (14U)                              
-#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos                   (15U)                              
-#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos                   (16U)                              
-#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos                   (17U)                              
-#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos                   (18U)                              
-#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos                   (19U)                              
-#define EXTI_IMR_MR19_Msk                   (0x1UL << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos                   (20U)                              
-#define EXTI_IMR_MR20_Msk                   (0x1UL << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos                   (21U)                              
-#define EXTI_IMR_MR21_Msk                   (0x1UL << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos                   (22U)                              
-#define EXTI_IMR_MR22_Msk                   (0x1UL << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23_Pos                   (23U)                              
-#define EXTI_IMR_MR23_Msk                   (0x1UL << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_IMR_IM0 EXTI_IMR_MR0
-#define  EXTI_IMR_IM1 EXTI_IMR_MR1
-#define  EXTI_IMR_IM2 EXTI_IMR_MR2
-#define  EXTI_IMR_IM3 EXTI_IMR_MR3
-#define  EXTI_IMR_IM4 EXTI_IMR_MR4
-#define  EXTI_IMR_IM5 EXTI_IMR_MR5
-#define  EXTI_IMR_IM6 EXTI_IMR_MR6
-#define  EXTI_IMR_IM7 EXTI_IMR_MR7
-#define  EXTI_IMR_IM8 EXTI_IMR_MR8
-#define  EXTI_IMR_IM9 EXTI_IMR_MR9
-#define  EXTI_IMR_IM10 EXTI_IMR_MR10
-#define  EXTI_IMR_IM11 EXTI_IMR_MR11
-#define  EXTI_IMR_IM12 EXTI_IMR_MR12
-#define  EXTI_IMR_IM13 EXTI_IMR_MR13
-#define  EXTI_IMR_IM14 EXTI_IMR_MR14
-#define  EXTI_IMR_IM15 EXTI_IMR_MR15
-#define  EXTI_IMR_IM16 EXTI_IMR_MR16
-#define  EXTI_IMR_IM17 EXTI_IMR_MR17
-#define  EXTI_IMR_IM18 EXTI_IMR_MR18
-#define  EXTI_IMR_IM19 EXTI_IMR_MR19
-#define  EXTI_IMR_IM20 EXTI_IMR_MR20
-#define  EXTI_IMR_IM21 EXTI_IMR_MR21
-#define  EXTI_IMR_IM22 EXTI_IMR_MR22
-/* Category 3, 4 & 5 */
-#define  EXTI_IMR_IM23 EXTI_IMR_MR23
-#define EXTI_IMR_IM_Pos                     (0U)                               
-#define EXTI_IMR_IM_Msk                     (0xFFFFFFUL << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
-#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos                    (0U)                               
-#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
-#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos                    (1U)                               
-#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
-#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos                    (2U)                               
-#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
-#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos                    (3U)                               
-#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
-#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos                    (4U)                               
-#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
-#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos                    (5U)                               
-#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
-#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos                    (6U)                               
-#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
-#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos                    (7U)                               
-#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
-#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos                    (8U)                               
-#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
-#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos                    (9U)                               
-#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
-#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos                   (10U)                              
-#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
-#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos                   (11U)                              
-#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
-#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos                   (12U)                              
-#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
-#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos                   (13U)                              
-#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
-#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos                   (14U)                              
-#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
-#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos                   (15U)                              
-#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
-#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos                   (16U)                              
-#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
-#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos                   (17U)                              
-#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
-#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos                   (18U)                              
-#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos                   (19U)                              
-#define EXTI_EMR_MR19_Msk                   (0x1UL << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos                   (20U)                              
-#define EXTI_EMR_MR20_Msk                   (0x1UL << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
-#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos                   (21U)                              
-#define EXTI_EMR_MR21_Msk                   (0x1UL << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
-#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos                   (22U)                              
-#define EXTI_EMR_MR22_Msk                   (0x1UL << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
-#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23_Pos                   (23U)                              
-#define EXTI_EMR_MR23_Msk                   (0x1UL << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
-#define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
-
-/* References Defines */
-#define  EXTI_EMR_EM0 EXTI_EMR_MR0
-#define  EXTI_EMR_EM1 EXTI_EMR_MR1
-#define  EXTI_EMR_EM2 EXTI_EMR_MR2
-#define  EXTI_EMR_EM3 EXTI_EMR_MR3
-#define  EXTI_EMR_EM4 EXTI_EMR_MR4
-#define  EXTI_EMR_EM5 EXTI_EMR_MR5
-#define  EXTI_EMR_EM6 EXTI_EMR_MR6
-#define  EXTI_EMR_EM7 EXTI_EMR_MR7
-#define  EXTI_EMR_EM8 EXTI_EMR_MR8
-#define  EXTI_EMR_EM9 EXTI_EMR_MR9
-#define  EXTI_EMR_EM10 EXTI_EMR_MR10
-#define  EXTI_EMR_EM11 EXTI_EMR_MR11
-#define  EXTI_EMR_EM12 EXTI_EMR_MR12
-#define  EXTI_EMR_EM13 EXTI_EMR_MR13
-#define  EXTI_EMR_EM14 EXTI_EMR_MR14
-#define  EXTI_EMR_EM15 EXTI_EMR_MR15
-#define  EXTI_EMR_EM16 EXTI_EMR_MR16
-#define  EXTI_EMR_EM17 EXTI_EMR_MR17
-#define  EXTI_EMR_EM18 EXTI_EMR_MR18
-#define  EXTI_EMR_EM19 EXTI_EMR_MR19
-#define  EXTI_EMR_EM20 EXTI_EMR_MR20
-#define  EXTI_EMR_EM21 EXTI_EMR_MR21
-#define  EXTI_EMR_EM22 EXTI_EMR_MR22
-#define  EXTI_EMR_EM23 EXTI_EMR_MR23
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos                   (0U)                               
-#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos                   (1U)                               
-#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos                   (2U)                               
-#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos                   (3U)                               
-#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos                   (4U)                               
-#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos                   (5U)                               
-#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos                   (6U)                               
-#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos                   (7U)                               
-#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos                   (8U)                               
-#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos                   (9U)                               
-#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos                  (10U)                              
-#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos                  (11U)                              
-#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos                  (12U)                              
-#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos                  (13U)                              
-#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos                  (14U)                              
-#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos                  (15U)                              
-#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos                  (16U)                              
-#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos                  (17U)                              
-#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos                  (18U)                              
-#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos                  (19U)                              
-#define EXTI_RTSR_TR19_Msk                  (0x1UL << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos                  (20U)                              
-#define EXTI_RTSR_TR20_Msk                  (0x1UL << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos                  (21U)                              
-#define EXTI_RTSR_TR21_Msk                  (0x1UL << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos                  (22U)                              
-#define EXTI_RTSR_TR22_Msk                  (0x1UL << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23_Pos                  (23U)                              
-#define EXTI_RTSR_TR23_Msk                  (0x1UL << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
-#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
-#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
-#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
-#define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos                   (0U)                               
-#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
-#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos                   (1U)                               
-#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
-#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos                   (2U)                               
-#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
-#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos                   (3U)                               
-#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
-#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos                   (4U)                               
-#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
-#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos                   (5U)                               
-#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
-#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos                   (6U)                               
-#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
-#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos                   (7U)                               
-#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
-#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos                   (8U)                               
-#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
-#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos                   (9U)                               
-#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
-#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos                  (10U)                              
-#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
-#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos                  (11U)                              
-#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
-#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos                  (12U)                              
-#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
-#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos                  (13U)                              
-#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
-#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos                  (14U)                              
-#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
-#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos                  (15U)                              
-#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
-#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos                  (16U)                              
-#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
-#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos                  (17U)                              
-#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
-#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos                  (18U)                              
-#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos                  (19U)                              
-#define EXTI_FTSR_TR19_Msk                  (0x1UL << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos                  (20U)                              
-#define EXTI_FTSR_TR20_Msk                  (0x1UL << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
-#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos                  (21U)                              
-#define EXTI_FTSR_TR21_Msk                  (0x1UL << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
-#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos                  (22U)                              
-#define EXTI_FTSR_TR22_Msk                  (0x1UL << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
-#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23_Pos                  (23U)                              
-#define EXTI_FTSR_TR23_Msk                  (0x1UL << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
-#define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
-
-/* References Defines */
-#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos               (0U)                               
-#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos               (1U)                               
-#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos               (2U)                               
-#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos               (3U)                               
-#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos               (4U)                               
-#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos               (5U)                               
-#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos               (6U)                               
-#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos               (7U)                               
-#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos               (8U)                               
-#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos               (9U)                               
-#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos              (10U)                              
-#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos              (11U)                              
-#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos              (12U)                              
-#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos              (13U)                              
-#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos              (14U)                              
-#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos              (15U)                              
-#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos              (16U)                              
-#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos              (17U)                              
-#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos              (18U)                              
-#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos              (19U)                              
-#define EXTI_SWIER_SWIER19_Msk              (0x1UL << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos              (20U)                              
-#define EXTI_SWIER_SWIER20_Msk              (0x1UL << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos              (21U)                              
-#define EXTI_SWIER_SWIER21_Msk              (0x1UL << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos              (22U)                              
-#define EXTI_SWIER_SWIER22_Msk              (0x1UL << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23_Pos              (23U)                              
-#define EXTI_SWIER_SWIER23_Msk              (0x1UL << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
-#define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
-
-/* References Defines */
-#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos                     (0U)                               
-#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
-#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos                     (1U)                               
-#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
-#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos                     (2U)                               
-#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
-#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos                     (3U)                               
-#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
-#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos                     (4U)                               
-#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
-#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos                     (5U)                               
-#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
-#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos                     (6U)                               
-#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
-#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos                     (7U)                               
-#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
-#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos                     (8U)                               
-#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
-#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos                     (9U)                               
-#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
-#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos                    (10U)                              
-#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
-#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos                    (11U)                              
-#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
-#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos                    (12U)                              
-#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
-#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos                    (13U)                              
-#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
-#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos                    (14U)                              
-#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
-#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos                    (15U)                              
-#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
-#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos                    (16U)                              
-#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
-#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos                    (17U)                              
-#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
-#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos                    (18U)                              
-#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos                    (19U)                              
-#define EXTI_PR_PR19_Msk                    (0x1UL << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos                    (20U)                              
-#define EXTI_PR_PR20_Msk                    (0x1UL << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
-#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos                    (21U)                              
-#define EXTI_PR_PR21_Msk                    (0x1UL << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
-#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos                    (22U)                              
-#define EXTI_PR_PR22_Msk                    (0x1UL << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
-#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23_Pos                    (23U)                              
-#define EXTI_PR_PR23_Msk                    (0x1UL << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
-#define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
-
-/* References Defines */
-#define  EXTI_PR_PIF0 EXTI_PR_PR0
-#define  EXTI_PR_PIF1 EXTI_PR_PR1
-#define  EXTI_PR_PIF2 EXTI_PR_PR2
-#define  EXTI_PR_PIF3 EXTI_PR_PR3
-#define  EXTI_PR_PIF4 EXTI_PR_PR4
-#define  EXTI_PR_PIF5 EXTI_PR_PR5
-#define  EXTI_PR_PIF6 EXTI_PR_PR6
-#define  EXTI_PR_PIF7 EXTI_PR_PR7
-#define  EXTI_PR_PIF8 EXTI_PR_PR8
-#define  EXTI_PR_PIF9 EXTI_PR_PR9
-#define  EXTI_PR_PIF10 EXTI_PR_PR10
-#define  EXTI_PR_PIF11 EXTI_PR_PR11
-#define  EXTI_PR_PIF12 EXTI_PR_PR12
-#define  EXTI_PR_PIF13 EXTI_PR_PR13
-#define  EXTI_PR_PIF14 EXTI_PR_PR14
-#define  EXTI_PR_PIF15 EXTI_PR_PR15
-#define  EXTI_PR_PIF16 EXTI_PR_PR16
-#define  EXTI_PR_PIF17 EXTI_PR_PR17
-#define  EXTI_PR_PIF18 EXTI_PR_PR18
-#define  EXTI_PR_PIF19 EXTI_PR_PR19
-#define  EXTI_PR_PIF20 EXTI_PR_PR20
-#define  EXTI_PR_PIF21 EXTI_PR_PR21
-#define  EXTI_PR_PIF22 EXTI_PR_PR22
-#define  EXTI_PR_PIF23 EXTI_PR_PR23
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
- */
-#define FLASH_CUT5
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY_Pos                (0U)                              
-#define FLASH_ACR_LATENCY_Msk                (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
-#define FLASH_ACR_PRFTEN_Pos                 (1U)                              
-#define FLASH_ACR_PRFTEN_Msk                 (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_ACC64_Pos                  (2U)                              
-#define FLASH_ACR_ACC64_Msk                  (0x1UL << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
-#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
-#define FLASH_ACR_SLEEP_PD_Pos               (3U)                              
-#define FLASH_ACR_SLEEP_PD_Msk               (0x1UL << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
-#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD_Pos                 (4U)                              
-#define FLASH_ACR_RUN_PD_Msk                 (0x1UL << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
-#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK_Pos                (0U)                              
-#define FLASH_PECR_PELOCK_Msk                (0x1UL << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
-#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK_Pos               (1U)                              
-#define FLASH_PECR_PRGLOCK_Msk               (0x1UL << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
-#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK_Pos               (2U)                              
-#define FLASH_PECR_OPTLOCK_Msk               (0x1UL << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
-#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG_Pos                  (3U)                              
-#define FLASH_PECR_PROG_Msk                  (0x1UL << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
-#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
-#define FLASH_PECR_DATA_Pos                  (4U)                              
-#define FLASH_PECR_DATA_Msk                  (0x1UL << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
-#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
-#define FLASH_PECR_FTDW_Pos                  (8U)                              
-#define FLASH_PECR_FTDW_Msk                  (0x1UL << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
-#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE_Pos                 (9U)                              
-#define FLASH_PECR_ERASE_Msk                 (0x1UL << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
-#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
-#define FLASH_PECR_FPRG_Pos                  (10U)                             
-#define FLASH_PECR_FPRG_Msk                  (0x1UL << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
-#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK_Pos            (15U)                             
-#define FLASH_PECR_PARALLBANK_Msk            (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
-#define FLASH_PECR_PARALLBANK                FLASH_PECR_PARALLBANK_Msk         /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE_Pos                 (16U)                             
-#define FLASH_PECR_EOPIE_Msk                 (0x1UL << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
-#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE_Pos                 (17U)                             
-#define FLASH_PECR_ERRIE_Msk                 (0x1UL << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
-#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)                             
-#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
-#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR_Pos              (0U)                              
-#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR_Pos              (0U)                              
-#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)                              
-#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)                              
-#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY_Pos                     (0U)                              
-#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
-#define FLASH_SR_EOP_Pos                     (1U)                              
-#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
-#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
-#define FLASH_SR_ENDHV_Pos                   (2U)                              
-#define FLASH_SR_ENDHV_Msk                   (0x1UL << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
-#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
-#define FLASH_SR_READY_Pos                   (3U)                              
-#define FLASH_SR_READY_Msk                   (0x1UL << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
-#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR_Pos                  (8U)                              
-#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
-#define FLASH_SR_PGAERR_Pos                  (9U)                              
-#define FLASH_SR_PGAERR_Msk                  (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
-#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR_Pos                  (10U)                             
-#define FLASH_SR_SIZERR_Msk                  (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
-#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
-#define FLASH_SR_OPTVERR_Pos                 (11U)                             
-#define FLASH_SR_OPTVERR_Msk                 (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
-#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
-#define FLASH_SR_OPTVERRUSR_Pos              (12U)                             
-#define FLASH_SR_OPTVERRUSR_Msk              (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
-#define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define FLASH_OBR_RDPRT_Pos                  (0U)                              
-#define FLASH_OBR_RDPRT_Msk                  (0xFFUL << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
-#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
-#define FLASH_OBR_BOR_LEV_Pos                (16U)                             
-#define FLASH_OBR_BOR_LEV_Msk                (0xFUL << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
-#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OBR_USER_Pos                   (20U)                             
-#define FLASH_OBR_USER_Msk                   (0xFUL << FLASH_OBR_USER_Pos)      /*!< 0x00F00000 */
-#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW_Pos                (20U)                             
-#define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
-#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
-#define FLASH_OBR_nRST_STOP_Pos              (21U)                             
-#define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
-#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos             (22U)                             
-#define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
-#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
-#define FLASH_OBR_nRST_BFB2_Pos              (23U)                             
-#define FLASH_OBR_nRST_BFB2_Msk              (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */
-#define FLASH_OBR_nRST_BFB2                  FLASH_OBR_nRST_BFB2_Msk           /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR1_WRP_Pos                  (0U)                              
-#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
-#define FLASH_WRPR2_WRP_Pos                  (0U)                              
-#define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */             
-#define FLASH_WRPR3_WRP_Pos                  (0U)                              
-#define FLASH_WRPR3_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR3_WRP                      FLASH_WRPR3_WRP_Msk               /*!< Write Protect sectors 64 to 95  */ 
-#define FLASH_WRPR4_WRP_Pos                  (0U)                              
-#define FLASH_WRPR4_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR4_WRP                      FLASH_WRPR4_WRP_Msk               /*!< Write Protect sectors 96 to 127 */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos                (0U)                              
-#define GPIO_MODER_MODER0_Msk                (0x3UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk             
-#define GPIO_MODER_MODER0_0                  (0x1UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1                  (0x2UL << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_MODER_MODER1_Pos                (2U)                              
-#define GPIO_MODER_MODER1_Msk                (0x3UL << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk             
-#define GPIO_MODER_MODER1_0                  (0x1UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1                  (0x2UL << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_MODER_MODER2_Pos                (4U)                              
-#define GPIO_MODER_MODER2_Msk                (0x3UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk             
-#define GPIO_MODER_MODER2_0                  (0x1UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1                  (0x2UL << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_MODER_MODER3_Pos                (6U)                              
-#define GPIO_MODER_MODER3_Msk                (0x3UL << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk             
-#define GPIO_MODER_MODER3_0                  (0x1UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1                  (0x2UL << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_MODER_MODER4_Pos                (8U)                              
-#define GPIO_MODER_MODER4_Msk                (0x3UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk             
-#define GPIO_MODER_MODER4_0                  (0x1UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1                  (0x2UL << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_MODER_MODER5_Pos                (10U)                             
-#define GPIO_MODER_MODER5_Msk                (0x3UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk             
-#define GPIO_MODER_MODER5_0                  (0x1UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1                  (0x2UL << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_MODER_MODER6_Pos                (12U)                             
-#define GPIO_MODER_MODER6_Msk                (0x3UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk             
-#define GPIO_MODER_MODER6_0                  (0x1UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1                  (0x2UL << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_MODER_MODER7_Pos                (14U)                             
-#define GPIO_MODER_MODER7_Msk                (0x3UL << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk             
-#define GPIO_MODER_MODER7_0                  (0x1UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1                  (0x2UL << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_MODER_MODER8_Pos                (16U)                             
-#define GPIO_MODER_MODER8_Msk                (0x3UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk             
-#define GPIO_MODER_MODER8_0                  (0x1UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1                  (0x2UL << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_MODER_MODER9_Pos                (18U)                             
-#define GPIO_MODER_MODER9_Msk                (0x3UL << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk             
-#define GPIO_MODER_MODER9_0                  (0x1UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1                  (0x2UL << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_MODER_MODER10_Pos               (20U)                             
-#define GPIO_MODER_MODER10_Msk               (0x3UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
-#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk            
-#define GPIO_MODER_MODER10_0                 (0x1UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1                 (0x2UL << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_MODER_MODER11_Pos               (22U)                             
-#define GPIO_MODER_MODER11_Msk               (0x3UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk            
-#define GPIO_MODER_MODER11_0                 (0x1UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1                 (0x2UL << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_MODER_MODER12_Pos               (24U)                             
-#define GPIO_MODER_MODER12_Msk               (0x3UL << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
-#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk            
-#define GPIO_MODER_MODER12_0                 (0x1UL << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1                 (0x2UL << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_MODER_MODER13_Pos               (26U)                             
-#define GPIO_MODER_MODER13_Msk               (0x3UL << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk            
-#define GPIO_MODER_MODER13_0                 (0x1UL << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1                 (0x2UL << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_MODER_MODER14_Pos               (28U)                             
-#define GPIO_MODER_MODER14_Msk               (0x3UL << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
-#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk            
-#define GPIO_MODER_MODER14_0                 (0x1UL << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1                 (0x2UL << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
-
-#define GPIO_MODER_MODER15_Pos               (30U)                             
-#define GPIO_MODER_MODER15_Msk               (0x3UL << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk            
-#define GPIO_MODER_MODER15_0                 (0x1UL << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1                 (0x2UL << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0                     (0x00000001U)                     
-#define GPIO_OTYPER_OT_1                     (0x00000002U)                     
-#define GPIO_OTYPER_OT_2                     (0x00000004U)                     
-#define GPIO_OTYPER_OT_3                     (0x00000008U)                     
-#define GPIO_OTYPER_OT_4                     (0x00000010U)                     
-#define GPIO_OTYPER_OT_5                     (0x00000020U)                     
-#define GPIO_OTYPER_OT_6                     (0x00000040U)                     
-#define GPIO_OTYPER_OT_7                     (0x00000080U)                     
-#define GPIO_OTYPER_OT_8                     (0x00000100U)                     
-#define GPIO_OTYPER_OT_9                     (0x00000200U)                     
-#define GPIO_OTYPER_OT_10                    (0x00000400U)                     
-#define GPIO_OTYPER_OT_11                    (0x00000800U)                     
-#define GPIO_OTYPER_OT_12                    (0x00001000U)                     
-#define GPIO_OTYPER_OT_13                    (0x00002000U)                     
-#define GPIO_OTYPER_OT_14                    (0x00004000U)                     
-#define GPIO_OTYPER_OT_15                    (0x00008000U)                     
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)                              
-#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
-#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk        
-#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
-#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
-
-#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)                              
-#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
-#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk        
-#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
-#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
-
-#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)                              
-#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
-#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk        
-#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
-#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
-
-#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)                              
-#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
-#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk        
-#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
-#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
-
-#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)                              
-#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
-#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk        
-#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
-#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
-
-#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)                             
-#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
-#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk        
-#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
-#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
-
-#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)                             
-#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
-#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk        
-#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
-#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
-
-#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)                             
-#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
-#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk        
-#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
-#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
-
-#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)                             
-#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
-#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk        
-#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
-#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
-
-#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)                             
-#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
-#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk        
-#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
-#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
-
-#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)                             
-#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
-#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk       
-#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
-#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
-
-#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)                             
-#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
-#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk       
-#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
-#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
-
-#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)                             
-#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
-#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk       
-#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
-#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)                             
-#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
-#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk       
-#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
-#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)                             
-#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
-#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk       
-#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
-#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
-
-#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)                             
-#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
-#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk       
-#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
-#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0_Pos                (0U)                              
-#define GPIO_PUPDR_PUPDR0_Msk                (0x3UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk             
-#define GPIO_PUPDR_PUPDR0_0                  (0x1UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPDR0_1                  (0x2UL << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
-
-#define GPIO_PUPDR_PUPDR1_Pos                (2U)                              
-#define GPIO_PUPDR_PUPDR1_Msk                (0x3UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk             
-#define GPIO_PUPDR_PUPDR1_0                  (0x1UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPDR1_1                  (0x2UL << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
-
-#define GPIO_PUPDR_PUPDR2_Pos                (4U)                              
-#define GPIO_PUPDR_PUPDR2_Msk                (0x3UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk             
-#define GPIO_PUPDR_PUPDR2_0                  (0x1UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPDR2_1                  (0x2UL << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
-
-#define GPIO_PUPDR_PUPDR3_Pos                (6U)                              
-#define GPIO_PUPDR_PUPDR3_Msk                (0x3UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk             
-#define GPIO_PUPDR_PUPDR3_0                  (0x1UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPDR3_1                  (0x2UL << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
-
-#define GPIO_PUPDR_PUPDR4_Pos                (8U)                              
-#define GPIO_PUPDR_PUPDR4_Msk                (0x3UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk             
-#define GPIO_PUPDR_PUPDR4_0                  (0x1UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPDR4_1                  (0x2UL << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
-
-#define GPIO_PUPDR_PUPDR5_Pos                (10U)                             
-#define GPIO_PUPDR_PUPDR5_Msk                (0x3UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk             
-#define GPIO_PUPDR_PUPDR5_0                  (0x1UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPDR5_1                  (0x2UL << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
-
-#define GPIO_PUPDR_PUPDR6_Pos                (12U)                             
-#define GPIO_PUPDR_PUPDR6_Msk                (0x3UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk             
-#define GPIO_PUPDR_PUPDR6_0                  (0x1UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPDR6_1                  (0x2UL << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
-
-#define GPIO_PUPDR_PUPDR7_Pos                (14U)                             
-#define GPIO_PUPDR_PUPDR7_Msk                (0x3UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk             
-#define GPIO_PUPDR_PUPDR7_0                  (0x1UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPDR7_1                  (0x2UL << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
-
-#define GPIO_PUPDR_PUPDR8_Pos                (16U)                             
-#define GPIO_PUPDR_PUPDR8_Msk                (0x3UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk             
-#define GPIO_PUPDR_PUPDR8_0                  (0x1UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPDR8_1                  (0x2UL << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
-
-#define GPIO_PUPDR_PUPDR9_Pos                (18U)                             
-#define GPIO_PUPDR_PUPDR9_Msk                (0x3UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk             
-#define GPIO_PUPDR_PUPDR9_0                  (0x1UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPDR9_1                  (0x2UL << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
-
-#define GPIO_PUPDR_PUPDR10_Pos               (20U)                             
-#define GPIO_PUPDR_PUPDR10_Msk               (0x3UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk            
-#define GPIO_PUPDR_PUPDR10_0                 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPDR10_1                 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
-
-#define GPIO_PUPDR_PUPDR11_Pos               (22U)                             
-#define GPIO_PUPDR_PUPDR11_Msk               (0x3UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk            
-#define GPIO_PUPDR_PUPDR11_0                 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPDR11_1                 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
-
-#define GPIO_PUPDR_PUPDR12_Pos               (24U)                             
-#define GPIO_PUPDR_PUPDR12_Msk               (0x3UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk            
-#define GPIO_PUPDR_PUPDR12_0                 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPDR12_1                 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
-
-#define GPIO_PUPDR_PUPDR13_Pos               (26U)                             
-#define GPIO_PUPDR_PUPDR13_Msk               (0x3UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk            
-#define GPIO_PUPDR_PUPDR13_0                 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPDR13_1                 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
-
-#define GPIO_PUPDR_PUPDR14_Pos               (28U)                             
-#define GPIO_PUPDR_PUPDR14_Msk               (0x3UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk            
-#define GPIO_PUPDR_PUPDR14_0                 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPDR14_1                 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPDR15_Pos               (30U)                             
-#define GPIO_PUPDR_PUPDR15_Msk               (0x3UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk            
-#define GPIO_PUPDR_PUPDR15_0                 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPDR15_1                 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       (0x00000001U)                     
-#define GPIO_IDR_IDR_1                       (0x00000002U)                     
-#define GPIO_IDR_IDR_2                       (0x00000004U)                     
-#define GPIO_IDR_IDR_3                       (0x00000008U)                     
-#define GPIO_IDR_IDR_4                       (0x00000010U)                     
-#define GPIO_IDR_IDR_5                       (0x00000020U)                     
-#define GPIO_IDR_IDR_6                       (0x00000040U)                     
-#define GPIO_IDR_IDR_7                       (0x00000080U)                     
-#define GPIO_IDR_IDR_8                       (0x00000100U)                     
-#define GPIO_IDR_IDR_9                       (0x00000200U)                     
-#define GPIO_IDR_IDR_10                      (0x00000400U)                     
-#define GPIO_IDR_IDR_11                      (0x00000800U)                     
-#define GPIO_IDR_IDR_12                      (0x00001000U)                     
-#define GPIO_IDR_IDR_13                      (0x00002000U)                     
-#define GPIO_IDR_IDR_14                      (0x00004000U)                     
-#define GPIO_IDR_IDR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       (0x00000001U)                     
-#define GPIO_ODR_ODR_1                       (0x00000002U)                     
-#define GPIO_ODR_ODR_2                       (0x00000004U)                     
-#define GPIO_ODR_ODR_3                       (0x00000008U)                     
-#define GPIO_ODR_ODR_4                       (0x00000010U)                     
-#define GPIO_ODR_ODR_5                       (0x00000020U)                     
-#define GPIO_ODR_ODR_6                       (0x00000040U)                     
-#define GPIO_ODR_ODR_7                       (0x00000080U)                     
-#define GPIO_ODR_ODR_8                       (0x00000100U)                     
-#define GPIO_ODR_ODR_9                       (0x00000200U)                     
-#define GPIO_ODR_ODR_10                      (0x00000400U)                     
-#define GPIO_ODR_ODR_11                      (0x00000800U)                     
-#define GPIO_ODR_ODR_12                      (0x00001000U)                     
-#define GPIO_ODR_ODR_13                      (0x00002000U)                     
-#define GPIO_ODR_ODR_14                      (0x00004000U)                     
-#define GPIO_ODR_ODR_15                      (0x00008000U)                     
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0                       (0x00000001U)                     
-#define GPIO_BSRR_BS_1                       (0x00000002U)                     
-#define GPIO_BSRR_BS_2                       (0x00000004U)                     
-#define GPIO_BSRR_BS_3                       (0x00000008U)                     
-#define GPIO_BSRR_BS_4                       (0x00000010U)                     
-#define GPIO_BSRR_BS_5                       (0x00000020U)                     
-#define GPIO_BSRR_BS_6                       (0x00000040U)                     
-#define GPIO_BSRR_BS_7                       (0x00000080U)                     
-#define GPIO_BSRR_BS_8                       (0x00000100U)                     
-#define GPIO_BSRR_BS_9                       (0x00000200U)                     
-#define GPIO_BSRR_BS_10                      (0x00000400U)                     
-#define GPIO_BSRR_BS_11                      (0x00000800U)                     
-#define GPIO_BSRR_BS_12                      (0x00001000U)                     
-#define GPIO_BSRR_BS_13                      (0x00002000U)                     
-#define GPIO_BSRR_BS_14                      (0x00004000U)                     
-#define GPIO_BSRR_BS_15                      (0x00008000U)                     
-#define GPIO_BSRR_BR_0                       (0x00010000U)                     
-#define GPIO_BSRR_BR_1                       (0x00020000U)                     
-#define GPIO_BSRR_BR_2                       (0x00040000U)                     
-#define GPIO_BSRR_BR_3                       (0x00080000U)                     
-#define GPIO_BSRR_BR_4                       (0x00100000U)                     
-#define GPIO_BSRR_BR_5                       (0x00200000U)                     
-#define GPIO_BSRR_BR_6                       (0x00400000U)                     
-#define GPIO_BSRR_BR_7                       (0x00800000U)                     
-#define GPIO_BSRR_BR_8                       (0x01000000U)                     
-#define GPIO_BSRR_BR_9                       (0x02000000U)                     
-#define GPIO_BSRR_BR_10                      (0x04000000U)                     
-#define GPIO_BSRR_BR_11                      (0x08000000U)                     
-#define GPIO_BSRR_BR_12                      (0x10000000U)                     
-#define GPIO_BSRR_BR_13                      (0x20000000U)                     
-#define GPIO_BSRR_BR_14                      (0x40000000U)                     
-#define GPIO_BSRR_BR_15                      (0x80000000U)                     
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0_Pos                   (0U)                              
-#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
-#define GPIO_LCKR_LCK1_Pos                   (1U)                              
-#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
-#define GPIO_LCKR_LCK2_Pos                   (2U)                              
-#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
-#define GPIO_LCKR_LCK3_Pos                   (3U)                              
-#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
-#define GPIO_LCKR_LCK4_Pos                   (4U)                              
-#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
-#define GPIO_LCKR_LCK5_Pos                   (5U)                              
-#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
-#define GPIO_LCKR_LCK6_Pos                   (6U)                              
-#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
-#define GPIO_LCKR_LCK7_Pos                   (7U)                              
-#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
-#define GPIO_LCKR_LCK8_Pos                   (8U)                              
-#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
-#define GPIO_LCKR_LCK9_Pos                   (9U)                              
-#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
-#define GPIO_LCKR_LCK10_Pos                  (10U)                             
-#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
-#define GPIO_LCKR_LCK11_Pos                  (11U)                             
-#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
-#define GPIO_LCKR_LCK12_Pos                  (12U)                             
-#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
-#define GPIO_LCKR_LCK13_Pos                  (13U)                             
-#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
-#define GPIO_LCKR_LCK14_Pos                  (14U)                             
-#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
-#define GPIO_LCKR_LCK15_Pos                  (15U)                             
-#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
-#define GPIO_LCKR_LCKK_Pos                   (16U)                             
-#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFSEL0_Msk                  (0xFUL << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
-#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFSEL1_Msk                  (0xFUL << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
-#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFSEL2_Msk                  (0xFUL << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
-#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFSEL3_Msk                  (0xFUL << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
-#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFSEL4_Msk                  (0xFUL << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
-#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFSEL5_Msk                  (0xFUL << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
-#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFSEL6_Msk                  (0xFUL << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
-#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFSEL7_Msk                  (0xFUL << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
-#define GPIO_AFRH_AFSEL8_Msk                  (0xFUL << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
-#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
-#define GPIO_AFRH_AFSEL9_Msk                  (0xFUL << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
-#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
-#define GPIO_AFRH_AFSEL10_Msk                  (0xFUL << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
-#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
-#define GPIO_AFRH_AFSEL11_Msk                  (0xFUL << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
-#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
-#define GPIO_AFRH_AFSEL12_Msk                  (0xFUL << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
-#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
-#define GPIO_AFRH_AFSEL13_Msk                  (0xFUL << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
-#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
-#define GPIO_AFRH_AFSEL14_Msk                  (0xFUL << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
-#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
-#define GPIO_AFRH_AFSEL15_Msk                  (0xFUL << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0                        (0x00000001U)                     
-#define GPIO_BRR_BR_1                        (0x00000002U)                     
-#define GPIO_BRR_BR_2                        (0x00000004U)                     
-#define GPIO_BRR_BR_3                        (0x00000008U)                     
-#define GPIO_BRR_BR_4                        (0x00000010U)                     
-#define GPIO_BRR_BR_5                        (0x00000020U)                     
-#define GPIO_BRR_BR_6                        (0x00000040U)                     
-#define GPIO_BRR_BR_7                        (0x00000080U)                     
-#define GPIO_BRR_BR_8                        (0x00000100U)                     
-#define GPIO_BRR_BR_9                        (0x00000200U)                     
-#define GPIO_BRR_BR_10                       (0x00000400U)                     
-#define GPIO_BRR_BR_11                       (0x00000800U)                     
-#define GPIO_BRR_BR_12                       (0x00001000U)                     
-#define GPIO_BRR_BR_13                       (0x00002000U)                     
-#define GPIO_BRR_BR_14                       (0x00004000U)                     
-#define GPIO_BRR_BR_15                       (0x00008000U)                     
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos                      (0U)                               
-#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
-#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos                   (1U)                               
-#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
-#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos                 (3U)                               
-#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos                   (4U)                               
-#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
-#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos                   (5U)                               
-#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
-#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos                    (6U)                               
-#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
-#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos               (7U)                               
-#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos                   (8U)                               
-#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
-#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
-#define I2C_CR1_STOP_Pos                    (9U)                               
-#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
-#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos                     (10U)                              
-#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
-#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos                     (11U)                              
-#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
-#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos                     (12U)                              
-#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
-#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos                   (13U)                              
-#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
-#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos                   (15U)                              
-#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
-#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos                    (0U)                               
-#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
-#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos                 (8U)                               
-#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
-#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos                 (9U)                               
-#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos                 (10U)                              
-#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos                   (11U)                              
-#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
-#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos                    (12U)                              
-#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
-#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
-#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos                   (0U)                               
-#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
-#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos                   (1U)                               
-#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
-#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos                   (2U)                               
-#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
-#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos                   (3U)                               
-#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
-#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos                   (4U)                               
-#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
-#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos                   (5U)                               
-#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
-#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos                   (6U)                               
-#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
-#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos                   (7U)                               
-#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
-#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos                   (8U)                               
-#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
-#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos                   (9U)                               
-#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
-#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos                (15U)                              
-#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos                 (0U)                               
-#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos                   (1U)                               
-#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
-#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos                       (0U)                               
-#define I2C_DR_DR_Msk                       (0xFFUL << I2C_DR_DR_Pos)           /*!< 0x000000FF */
-#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos                      (0U)                               
-#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
-#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos                    (1U)                               
-#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
-#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos                     (2U)                               
-#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
-#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos                   (3U)                               
-#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
-#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos                   (4U)                               
-#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
-#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos                    (6U)                               
-#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
-#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos                     (7U)                               
-#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
-#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos                    (8U)                               
-#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
-#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos                    (9U)                               
-#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
-#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos                      (10U)                              
-#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
-#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos                     (11U)                              
-#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
-#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos                  (12U)                              
-#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
-#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos                 (14U)                              
-#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos                (15U)                              
-#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos                     (0U)                               
-#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
-#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos                    (1U)                               
-#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
-#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos                     (2U)                               
-#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
-#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos                 (4U)                               
-#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
-#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               
-#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos                 (6U)                               
-#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos                   (7U)                               
-#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
-#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos                     (8U)                               
-#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
-#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos                     (0U)                               
-#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
-#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos                    (14U)                              
-#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
-#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos                      (15U)                              
-#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
-#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos                 (0U)                               
-#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
-#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos                     (0U)                               
-#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos                      (0U)                               
-#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
-#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
-#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
-#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos                     (0U)                               
-#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
-#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos                     (0U)                               
-#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
-#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos                     (1U)                               
-#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
-#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN_Pos           (0U)                                        
-#define LCD_CR_LCDEN_Msk           (0x1UL << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
-#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
-#define LCD_CR_VSEL_Pos            (1U)                                        
-#define LCD_CR_VSEL_Msk            (0x1UL << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
-#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY_Pos            (2U)                                        
-#define LCD_CR_DUTY_Msk            (0x7UL << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
-#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              (0x1UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
-#define LCD_CR_DUTY_1              (0x2UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
-#define LCD_CR_DUTY_2              (0x4UL << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
-
-#define LCD_CR_BIAS_Pos            (5U)                                        
-#define LCD_CR_BIAS_Msk            (0x3UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
-#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              (0x1UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
-#define LCD_CR_BIAS_1              (0x2UL << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
-
-#define LCD_CR_MUX_SEG_Pos         (7U)                                        
-#define LCD_CR_MUX_SEG_Msk         (0x1UL << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
-#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD_Pos             (0U)                                        
-#define LCD_FCR_HD_Msk             (0x1UL << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
-#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE_Pos          (1U)                                        
-#define LCD_FCR_SOFIE_Msk          (0x1UL << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
-#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE_Pos          (3U)                                        
-#define LCD_FCR_UDDIE_Msk          (0x1UL << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
-#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON_Pos            (4U)                                        
-#define LCD_FCR_PON_Msk            (0x7UL << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
-#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              (0x1UL << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
-#define LCD_FCR_PON_1              (0x2UL << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
-#define LCD_FCR_PON_2              (0x4UL << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
-
-#define LCD_FCR_DEAD_Pos           (7U)                                        
-#define LCD_FCR_DEAD_Msk           (0x7UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
-#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             (0x1UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
-#define LCD_FCR_DEAD_1             (0x2UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
-#define LCD_FCR_DEAD_2             (0x4UL << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
-
-#define LCD_FCR_CC_Pos             (10U)                                       
-#define LCD_FCR_CC_Msk             (0x7UL << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
-#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               (0x1UL << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
-#define LCD_FCR_CC_1               (0x2UL << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
-#define LCD_FCR_CC_2               (0x4UL << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
-
-#define LCD_FCR_BLINKF_Pos         (13U)                                       
-#define LCD_FCR_BLINKF_Msk         (0x7UL << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
-#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           (0x1UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
-#define LCD_FCR_BLINKF_1           (0x2UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
-#define LCD_FCR_BLINKF_2           (0x4UL << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
-
-#define LCD_FCR_BLINK_Pos          (16U)                                       
-#define LCD_FCR_BLINK_Msk          (0x3UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
-#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            (0x1UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
-#define LCD_FCR_BLINK_1            (0x2UL << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
-
-#define LCD_FCR_DIV_Pos            (18U)                                       
-#define LCD_FCR_DIV_Msk            (0xFUL << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
-#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS_Pos             (22U)                                       
-#define LCD_FCR_PS_Msk             (0xFUL << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
-#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS_Pos             (0U)                                        
-#define LCD_SR_ENS_Msk             (0x1UL << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
-#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
-#define LCD_SR_SOF_Pos             (1U)                                        
-#define LCD_SR_SOF_Msk             (0x1UL << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
-#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR_Pos             (2U)                                        
-#define LCD_SR_UDR_Msk             (0x1UL << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
-#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
-#define LCD_SR_UDD_Pos             (3U)                                        
-#define LCD_SR_UDD_Msk             (0x1UL << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
-#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY_Pos             (4U)                                        
-#define LCD_SR_RDY_Msk             (0x1UL << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
-#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR_Pos           (5U)                                        
-#define LCD_SR_FCRSR_Msk           (0x1UL << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
-#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC_Pos           (1U)                                        
-#define LCD_CLR_SOFC_Msk           (0x1UL << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
-#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC_Pos           (3U)                                        
-#define LCD_CLR_UDDC_Msk           (0x1UL << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
-#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
-#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
-#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR_Pos                   (0U)                               
-#define PWR_CR_LPSDSR_Msk                   (0x1UL << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
-#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS_Pos                     (1U)                               
-#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
-#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos                     (2U)                               
-#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
-#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos                     (3U)                               
-#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
-#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos                     (4U)                               
-#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
-#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos                      (5U)                               
-#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
-#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
-#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
-#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
-
-#define PWR_CR_DBP_Pos                      (8U)                               
-#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
-#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP_Pos                      (9U)                               
-#define PWR_CR_ULP_Msk                      (0x1UL << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
-#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU_Pos                      (10U)                              
-#define PWR_CR_FWU_Msk                      (0x1UL << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
-#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
-
-#define PWR_CR_VOS_Pos                      (11U)                              
-#define PWR_CR_VOS_Msk                      (0x3UL << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
-#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        (0x1UL << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
-#define PWR_CR_VOS_1                        (0x2UL << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
-#define PWR_CR_LPRUN_Pos                    (14U)                              
-#define PWR_CR_LPRUN_Msk                    (0x1UL << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
-#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos                     (0U)                               
-#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
-#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos                     (1U)                               
-#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
-#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos                    (2U)                               
-#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
-#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF_Pos             (3U)                               
-#define PWR_CSR_VREFINTRDYF_Msk             (0x1UL << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
-#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF_Pos                    (4U)                               
-#define PWR_CSR_VOSF_Msk                    (0x1UL << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
-#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF_Pos                  (5U)                               
-#define PWR_CSR_REGLPF_Msk                  (0x1UL << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
-#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1_Pos                   (8U)                               
-#define PWR_CSR_EWUP1_Msk                   (0x1UL << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
-#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2_Pos                   (9U)                               
-#define PWR_CSR_EWUP2_Msk                   (0x1UL << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
-#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3_Pos                   (10U)                              
-#define PWR_CSR_EWUP3_Msk                   (0x1UL << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
-#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                    (0U)                               
-#define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
-#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos                   (1U)                               
-#define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
-
-#define RCC_CR_MSION_Pos                    (8U)                               
-#define RCC_CR_MSION_Msk                    (0x1UL << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
-#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY_Pos                   (9U)                               
-#define RCC_CR_MSIRDY_Msk                   (0x1UL << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
-#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
-
-#define RCC_CR_HSEON_Pos                    (16U)                              
-#define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
-#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos                   (17U)                              
-#define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
-#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos                   (18U)                              
-#define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
-
-#define RCC_CR_PLLON_Pos                    (24U)                              
-#define RCC_CR_PLLON_Msk                    (0x1UL << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
-#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos                   (25U)                              
-#define RCC_CR_PLLRDY_Msk                   (0x1UL << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
-#define RCC_CR_CSSON_Pos                    (28U)                              
-#define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
-#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
-
-#define RCC_CR_RTCPRE_Pos                   (29U)                              
-#define RCC_CR_RTCPRE_Msk                   (0x3UL << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
-#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
-#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
-#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL_Pos                (0U)                               
-#define RCC_ICSCR_HSICAL_Msk                (0xFFUL << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
-#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM_Pos               (8U)                               
-#define RCC_ICSCR_HSITRIM_Msk               (0x1FUL << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
-#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE_Pos              (13U)                              
-#define RCC_ICSCR_MSIRANGE_Msk              (0x7UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
-#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                (0x0UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
-#define RCC_ICSCR_MSIRANGE_1                (0x1UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
-#define RCC_ICSCR_MSIRANGE_2                (0x2UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
-#define RCC_ICSCR_MSIRANGE_3                (0x3UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
-#define RCC_ICSCR_MSIRANGE_4                (0x4UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
-#define RCC_ICSCR_MSIRANGE_5                (0x5UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
-#define RCC_ICSCR_MSIRANGE_6                (0x6UL << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
-#define RCC_ICSCR_MSICAL_Pos                (16U)                              
-#define RCC_ICSCR_MSICAL_Msk                (0xFFUL << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
-#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM_Pos               (24U)                              
-#define RCC_ICSCR_MSITRIM_Msk               (0xFFUL << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
-#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define RCC_CFGR_SW_Pos                     (0U)                               
-#define RCC_CFGR_SW_Msk                     (0x3UL << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
-#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       (0x1UL << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                       (0x2UL << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
-
-/*!< SW configuration */
-#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
-
-#define RCC_CFGR_SWS_Pos                    (2U)                               
-#define RCC_CFGR_SWS_Msk                    (0x3UL << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
-#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      (0x1UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                      (0x2UL << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
-
-#define RCC_CFGR_HPRE_Pos                   (4U)                               
-#define RCC_CFGR_HPRE_Msk                   (0xFUL << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     (0x1UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                     (0x2UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                     (0x4UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                     (0x8UL << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE1_Pos                  (8U)                               
-#define RCC_CFGR_PPRE1_Msk                  (0x7UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    (0x1UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                    (0x2UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                    (0x4UL << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_PPRE2_Pos                  (11U)                              
-#define RCC_CFGR_PPRE2_Msk                  (0x7UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    (0x1UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                    (0x2UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                    (0x4UL << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC_Pos                 (16U)                              
-#define RCC_CFGR_PLLSRC_Msk                 (0x1UL << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL_Pos                 (18U)                              
-#define RCC_CFGR_PLLMUL_Msk                 (0xFUL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   (0x1UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_PLLMUL_1                   (0x2UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_PLLMUL_2                   (0x4UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
-#define RCC_CFGR_PLLMUL_3                   (0x8UL << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV_Pos                 (22U)                              
-#define RCC_CFGR_PLLDIV_Msk                 (0x3UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   (0x1UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV_1                   (0x2UL << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
-
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
-#define RCC_CFGR_PLLDIV2_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV2_Msk                (0x1UL << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
-#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3_Pos                (23U)                              
-#define RCC_CFGR_PLLDIV3_Msk                (0x1UL << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
-#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4_Pos                (22U)                              
-#define RCC_CFGR_PLLDIV4_Msk                (0x3UL << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
-#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
-
-
-#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
-#define RCC_CFGR_MCOSEL_Msk                 (0x7UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   (0x1UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                   (0x2UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                   (0x4UL << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
-#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)                              
-#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
-#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
-#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)                              
-#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
-#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
-#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)                              
-#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
-#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
-#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)                              
-#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
-#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
-
-#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
-#define RCC_CFGR_MCOPRE_Msk                 (0x7UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define RCC_CFGR_MCOPRE_0                   (0x1UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                   (0x2UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                   (0x4UL << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
-
-/*!< MCO Prescaler configuration */ 
-#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
- 
-/* Legacy aliases */
-#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
-#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
-#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
-#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
-#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
-#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
-#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
-#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
-#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
-#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
-#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
-#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
-#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define RCC_CIR_LSIRDYF_Pos                 (0U)                               
-#define RCC_CIR_LSIRDYF_Msk                 (0x1UL << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos                 (1U)                               
-#define RCC_CIR_LSERDYF_Msk                 (0x1UL << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos                 (2U)                               
-#define RCC_CIR_HSIRDYF_Msk                 (0x1UL << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos                 (3U)                               
-#define RCC_CIR_HSERDYF_Msk                 (0x1UL << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos                 (4U)                               
-#define RCC_CIR_PLLRDYF_Msk                 (0x1UL << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_MSIRDYF_Pos                 (5U)                               
-#define RCC_CIR_MSIRDYF_Msk                 (0x1UL << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
-#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
-#define RCC_CIR_LSECSSF_Pos                 (6U)                               
-#define RCC_CIR_LSECSSF_Msk                 (0x1UL << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
-#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
-#define RCC_CIR_CSSF_Pos                    (7U)                               
-#define RCC_CIR_CSSF_Msk                    (0x1UL << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
-#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
-
-#define RCC_CIR_LSIRDYIE_Pos                (8U)                               
-#define RCC_CIR_LSIRDYIE_Msk                (0x1UL << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos                (9U)                               
-#define RCC_CIR_LSERDYIE_Msk                (0x1UL << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos                (10U)                              
-#define RCC_CIR_HSIRDYIE_Msk                (0x1UL << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos                (11U)                              
-#define RCC_CIR_HSERDYIE_Msk                (0x1UL << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos                (12U)                              
-#define RCC_CIR_PLLRDYIE_Msk                (0x1UL << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_MSIRDYIE_Pos                (13U)                              
-#define RCC_CIR_MSIRDYIE_Msk                (0x1UL << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
-#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
-#define RCC_CIR_LSECSSIE_Pos                (14U)                              
-#define RCC_CIR_LSECSSIE_Msk                (0x1UL << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
-#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
-
-#define RCC_CIR_LSIRDYC_Pos                 (16U)                              
-#define RCC_CIR_LSIRDYC_Msk                 (0x1UL << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos                 (17U)                              
-#define RCC_CIR_LSERDYC_Msk                 (0x1UL << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos                 (18U)                              
-#define RCC_CIR_HSIRDYC_Msk                 (0x1UL << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos                 (19U)                              
-#define RCC_CIR_HSERDYC_Msk                 (0x1UL << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos                 (20U)                              
-#define RCC_CIR_PLLRDYC_Msk                 (0x1UL << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_MSIRDYC_Pos                 (21U)                              
-#define RCC_CIR_MSIRDYC_Msk                 (0x1UL << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
-#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
-#define RCC_CIR_LSECSSC_Pos                 (22U)                              
-#define RCC_CIR_LSECSSC_Msk                 (0x1UL << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
-#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
-#define RCC_CIR_CSSC_Pos                    (23U)                              
-#define RCC_CIR_CSSC_Msk                    (0x1UL << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
-#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define RCC_AHBRSTR_GPIOARST_Pos            (0U)                               
-#define RCC_AHBRSTR_GPIOARST_Msk            (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
-#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)                               
-#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
-#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)                               
-#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
-#define RCC_AHBRSTR_GPIODRST_Pos            (3U)                               
-#define RCC_AHBRSTR_GPIODRST_Msk            (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
-#define RCC_AHBRSTR_GPIOERST_Pos            (4U)                               
-#define RCC_AHBRSTR_GPIOERST_Msk            (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
-#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)                               
-#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
-#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
-#define RCC_AHBRSTR_GPIOFRST_Pos            (6U)                               
-#define RCC_AHBRSTR_GPIOFRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */
-#define RCC_AHBRSTR_GPIOFRST                RCC_AHBRSTR_GPIOFRST_Msk           /*!< GPIO port F reset */
-#define RCC_AHBRSTR_GPIOGRST_Pos            (7U)                               
-#define RCC_AHBRSTR_GPIOGRST_Msk            (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */
-#define RCC_AHBRSTR_GPIOGRST                RCC_AHBRSTR_GPIOGRST_Msk           /*!< GPIO port G reset */
-#define RCC_AHBRSTR_CRCRST_Pos              (12U)                              
-#define RCC_AHBRSTR_CRCRST_Msk              (0x1UL << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
-#define RCC_AHBRSTR_FLITFRST_Pos            (15U)                              
-#define RCC_AHBRSTR_FLITFRST_Msk            (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
-#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
-#define RCC_AHBRSTR_DMA1RST_Pos             (24U)                              
-#define RCC_AHBRSTR_DMA1RST_Msk             (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
-#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
-#define RCC_AHBRSTR_DMA2RST_Pos             (25U)                              
-#define RCC_AHBRSTR_DMA2RST_Msk             (0x1UL << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
-#define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
-#define RCC_AHBRSTR_AESRST_Pos              (27U)                              
-#define RCC_AHBRSTR_AESRST_Msk              (0x1UL << RCC_AHBRSTR_AESRST_Pos)   /*!< 0x08000000 */
-#define RCC_AHBRSTR_AESRST                  RCC_AHBRSTR_AESRST_Msk             /*!< AES reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
-#define RCC_APB2RSTR_TIM9RST_Pos            (2U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk            (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST_Pos           (3U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk           (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST_Pos           (4U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk           (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
-#define RCC_APB2RSTR_ADC1RST_Pos            (9U)                               
-#define RCC_APB2RSTR_ADC1RST_Msk            (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos            (0U)                               
-#define RCC_APB1RSTR_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos            (1U)                               
-#define RCC_APB1RSTR_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
-#define RCC_APB1RSTR_TIM4RST_Pos            (2U)                               
-#define RCC_APB1RSTR_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
-#define RCC_APB1RSTR_TIM5RST_Pos            (3U)                               
-#define RCC_APB1RSTR_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
-#define RCC_APB1RSTR_TIM6RST_Pos            (4U)                               
-#define RCC_APB1RSTR_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
-#define RCC_APB1RSTR_TIM7RST_Pos            (5U)                               
-#define RCC_APB1RSTR_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
-#define RCC_APB1RSTR_LCDRST_Pos             (9U)                               
-#define RCC_APB1RSTR_LCDRST_Msk             (0x1UL << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
-#define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
-#define RCC_APB1RSTR_WWDGRST_Pos            (11U)                              
-#define RCC_APB1RSTR_WWDGRST_Msk            (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_SPI2RST_Pos            (14U)                              
-#define RCC_APB1RSTR_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
-#define RCC_APB1RSTR_SPI3RST_Pos            (15U)                              
-#define RCC_APB1RSTR_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
-#define RCC_APB1RSTR_USART2RST_Pos          (17U)                              
-#define RCC_APB1RSTR_USART2RST_Msk          (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos          (18U)                              
-#define RCC_APB1RSTR_USART3RST_Msk          (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos           (19U)                              
-#define RCC_APB1RSTR_UART4RST_Msk           (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST               RCC_APB1RSTR_UART4RST_Msk          /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos           (20U)                              
-#define RCC_APB1RSTR_UART5RST_Msk           (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST               RCC_APB1RSTR_UART5RST_Msk          /*!< UART 5 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos            (21U)                              
-#define RCC_APB1RSTR_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos            (22U)                              
-#define RCC_APB1RSTR_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
-#define RCC_APB1RSTR_USBRST_Pos             (23U)                              
-#define RCC_APB1RSTR_USBRST_Msk             (0x1UL << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
-#define RCC_APB1RSTR_PWRRST_Pos             (28U)                              
-#define RCC_APB1RSTR_PWRRST_Msk             (0x1UL << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
-#define RCC_APB1RSTR_DACRST_Pos             (29U)                              
-#define RCC_APB1RSTR_DACRST_Msk             (0x1UL << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
-#define RCC_APB1RSTR_COMPRST_Pos            (31U)                              
-#define RCC_APB1RSTR_COMPRST_Msk            (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
-#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_GPIOAEN_Pos              (0U)                               
-#define RCC_AHBENR_GPIOAEN_Msk              (0x1UL << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
-#define RCC_AHBENR_GPIOBEN_Pos              (1U)                               
-#define RCC_AHBENR_GPIOBEN_Msk              (0x1UL << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
-#define RCC_AHBENR_GPIOCEN_Pos              (2U)                               
-#define RCC_AHBENR_GPIOCEN_Msk              (0x1UL << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
-#define RCC_AHBENR_GPIODEN_Pos              (3U)                               
-#define RCC_AHBENR_GPIODEN_Msk              (0x1UL << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
-#define RCC_AHBENR_GPIOEEN_Pos              (4U)                               
-#define RCC_AHBENR_GPIOEEN_Msk              (0x1UL << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
-#define RCC_AHBENR_GPIOHEN_Pos              (5U)                               
-#define RCC_AHBENR_GPIOHEN_Msk              (0x1UL << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
-#define RCC_AHBENR_GPIOFEN_Pos              (6U)                               
-#define RCC_AHBENR_GPIOFEN_Msk              (0x1UL << RCC_AHBENR_GPIOFEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHBENR_GPIOFEN                  RCC_AHBENR_GPIOFEN_Msk             /*!< GPIO port F clock enable */
-#define RCC_AHBENR_GPIOGEN_Pos              (7U)                               
-#define RCC_AHBENR_GPIOGEN_Msk              (0x1UL << RCC_AHBENR_GPIOGEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHBENR_GPIOGEN                  RCC_AHBENR_GPIOGEN_Msk             /*!< GPIO port G clock enable */
-#define RCC_AHBENR_CRCEN_Pos                (12U)                              
-#define RCC_AHBENR_CRCEN_Msk                (0x1UL << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
-#define RCC_AHBENR_FLITFEN_Pos              (15U)                              
-#define RCC_AHBENR_FLITFEN_Msk              (0x1UL << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
-#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define RCC_AHBENR_DMA1EN_Pos               (24U)                              
-#define RCC_AHBENR_DMA1EN_Msk               (0x1UL << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
-#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
-#define RCC_AHBENR_DMA2EN_Pos               (25U)                              
-#define RCC_AHBENR_DMA2EN_Msk               (0x1UL << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
-#define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
-#define RCC_AHBENR_AESEN_Pos                (27U)                              
-#define RCC_AHBENR_AESEN_Msk                (0x1UL << RCC_AHBENR_AESEN_Pos)     /*!< 0x08000000 */
-#define RCC_AHBENR_AESEN                    RCC_AHBENR_AESEN_Msk               /*!< AES clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
-#define RCC_APB2ENR_TIM9EN_Pos              (2U)                               
-#define RCC_APB2ENR_TIM9EN_Msk              (0x1UL << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
-#define RCC_APB2ENR_TIM10EN_Pos             (3U)                               
-#define RCC_APB2ENR_TIM10EN_Msk             (0x1UL << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
-#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
-#define RCC_APB2ENR_TIM11EN_Pos             (4U)                               
-#define RCC_APB2ENR_TIM11EN_Msk             (0x1UL << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos              (9U)                               
-#define RCC_APB2ENR_ADC1EN_Msk              (0x1UL << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN_Pos              (0U)                               
-#define RCC_APB1ENR_TIM2EN_Msk              (0x1UL << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos              (1U)                               
-#define RCC_APB1ENR_TIM3EN_Msk              (0x1UL << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM4EN_Pos              (2U)                               
-#define RCC_APB1ENR_TIM4EN_Msk              (0x1UL << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_TIM5EN_Pos              (3U)                               
-#define RCC_APB1ENR_TIM5EN_Msk              (0x1UL << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
-#define RCC_APB1ENR_TIM6EN_Pos              (4U)                               
-#define RCC_APB1ENR_TIM6EN_Msk              (0x1UL << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN_Pos              (5U)                               
-#define RCC_APB1ENR_TIM7EN_Msk              (0x1UL << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN_Pos               (9U)                               
-#define RCC_APB1ENR_LCDEN_Msk               (0x1UL << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
-#define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos              (11U)                              
-#define RCC_APB1ENR_WWDGEN_Msk              (0x1UL << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos              (14U)                              
-#define RCC_APB1ENR_SPI2EN_Msk              (0x1UL << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_SPI3EN_Pos              (15U)                              
-#define RCC_APB1ENR_SPI3EN_Msk              (0x1UL << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_USART2EN_Pos            (17U)                              
-#define RCC_APB1ENR_USART2EN_Msk            (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos            (18U)                              
-#define RCC_APB1ENR_USART3EN_Msk            (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos             (19U)                              
-#define RCC_APB1ENR_UART4EN_Msk             (0x1UL << RCC_APB1ENR_UART4EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                 RCC_APB1ENR_UART4EN_Msk            /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos             (20U)                              
-#define RCC_APB1ENR_UART5EN_Msk             (0x1UL << RCC_APB1ENR_UART5EN_Pos)  /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                 RCC_APB1ENR_UART5EN_Msk            /*!< UART 5 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos              (21U)                              
-#define RCC_APB1ENR_I2C1EN_Msk              (0x1UL << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos              (22U)                              
-#define RCC_APB1ENR_I2C2EN_Msk              (0x1UL << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN_Pos               (23U)                              
-#define RCC_APB1ENR_USBEN_Msk               (0x1UL << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
-#define RCC_APB1ENR_PWREN_Pos               (28U)                              
-#define RCC_APB1ENR_PWREN_Msk               (0x1UL << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
-#define RCC_APB1ENR_DACEN_Pos               (29U)                              
-#define RCC_APB1ENR_DACEN_Msk               (0x1UL << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
-#define RCC_APB1ENR_COMPEN_Pos              (31U)                              
-#define RCC_APB1ENR_COMPEN_Msk              (0x1UL << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
-#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)                               
-#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)                               
-#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)                               
-#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)                               
-#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)                               
-#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)                               
-#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOFLPEN_Pos          (6U)                               
-#define RCC_AHBLPENR_GPIOFLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBLPENR_GPIOFLPEN              RCC_AHBLPENR_GPIOFLPEN_Msk         /*!< GPIO port F clock enabled in sleep mode */
-#define RCC_AHBLPENR_GPIOGLPEN_Pos          (7U)                               
-#define RCC_AHBLPENR_GPIOGLPEN_Msk          (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHBLPENR_GPIOGLPEN              RCC_AHBLPENR_GPIOGLPEN_Msk         /*!< GPIO port G clock enabled in sleep mode */
-#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)                              
-#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)                              
-#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)                              
-#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)                              
-#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
-#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)                              
-#define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
-#define RCC_AHBLPENR_AESLPEN_Pos            (27U)                              
-#define RCC_AHBLPENR_AESLPEN_Msk            (0x1UL << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHBLPENR_AESLPEN                RCC_AHBLPENR_AESLPEN_Msk           /*!< AES clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
-#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
-#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)                               
-#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)                              
-#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)                              
-#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)                               
-#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)                               
-#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)                               
-#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)                               
-#define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)                               
-#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)                               
-#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1LPENR_LCDLPEN_Pos           (9U)                               
-#define RCC_APB1LPENR_LCDLPEN_Msk           (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)                              
-#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)                              
-#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)                              
-#define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)                              
-#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)                              
-#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART4LPEN_Pos         (19U)                              
-#define RCC_APB1LPENR_UART4LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN             RCC_APB1LPENR_UART4LPEN_Msk        /*!< UART 4 clock enabled in sleep mode */
-#define RCC_APB1LPENR_UART5LPEN_Pos         (20U)                              
-#define RCC_APB1LPENR_UART5LPEN_Msk         (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN             RCC_APB1LPENR_UART5LPEN_Msk        /*!< UART 5 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)                              
-#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
-#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)                              
-#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
-#define RCC_APB1LPENR_USBLPEN_Pos           (23U)                              
-#define RCC_APB1LPENR_USBLPEN_Msk           (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
-#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)                              
-#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_DACLPEN_Pos           (29U)                              
-#define RCC_APB1LPENR_DACLPEN_Msk           (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
-#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)                              
-#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
-#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define RCC_CSR_LSION_Pos                   (0U)                               
-#define RCC_CSR_LSION_Msk                   (0x1UL << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
-#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos                  (1U)                               
-#define RCC_CSR_LSIRDY_Msk                  (0x1UL << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON_Pos                   (8U)                               
-#define RCC_CSR_LSEON_Msk                   (0x1UL << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
-#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY_Pos                  (9U)                               
-#define RCC_CSR_LSERDY_Msk                  (0x1UL << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
-#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP_Pos                  (10U)                              
-#define RCC_CSR_LSEBYP_Msk                  (0x1UL << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
-#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
-
-#define RCC_CSR_LSECSSON_Pos                (11U)                              
-#define RCC_CSR_LSECSSON_Msk                (0x1UL << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
-#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD_Pos                 (12U)                              
-#define RCC_CSR_LSECSSD_Msk                 (0x1UL << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
-#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
-
-#define RCC_CSR_RTCSEL_Pos                  (16U)                              
-#define RCC_CSR_RTCSEL_Msk                  (0x3UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    (0x1UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_1                    (0x2UL << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
-
-/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_LSE_Msk              (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
-#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI_Pos              (17U)                              
-#define RCC_CSR_RTCSEL_LSI_Msk              (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
-#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE_Pos              (16U)                              
-#define RCC_CSR_RTCSEL_HSE_Msk              (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
-#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define RCC_CSR_RTCEN_Pos                   (22U)                              
-#define RCC_CSR_RTCEN_Msk                   (0x1UL << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
-#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
-#define RCC_CSR_RTCRST_Pos                  (23U)                              
-#define RCC_CSR_RTCRST_Msk                  (0x1UL << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
-#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
- 
-#define RCC_CSR_RMVF_Pos                    (24U)                              
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
-#define RCC_CSR_PINRSTF_Pos                 (26U)                              
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos                 (27U)                              
-#define RCC_CSR_PORRSTF_Msk                 (0x1UL << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
-*/
-#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
-#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
-#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
-#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
-#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
-#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
-#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
-
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                        (22U)                             
-#define RTC_TR_PM_Msk                        (0x1UL << RTC_TR_PM_Pos)           /*!< 0x00400000 */
-#define RTC_TR_PM                            RTC_TR_PM_Msk                     
-#define RTC_TR_HT_Pos                        (20U)                             
-#define RTC_TR_HT_Msk                        (0x3UL << RTC_TR_HT_Pos)           /*!< 0x00300000 */
-#define RTC_TR_HT                            RTC_TR_HT_Msk                     
-#define RTC_TR_HT_0                          (0x1UL << RTC_TR_HT_Pos)           /*!< 0x00100000 */
-#define RTC_TR_HT_1                          (0x2UL << RTC_TR_HT_Pos)           /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                        (16U)                             
-#define RTC_TR_HU_Msk                        (0xFUL << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
-#define RTC_TR_HU                            RTC_TR_HU_Msk                     
-#define RTC_TR_HU_0                          (0x1UL << RTC_TR_HU_Pos)           /*!< 0x00010000 */
-#define RTC_TR_HU_1                          (0x2UL << RTC_TR_HU_Pos)           /*!< 0x00020000 */
-#define RTC_TR_HU_2                          (0x4UL << RTC_TR_HU_Pos)           /*!< 0x00040000 */
-#define RTC_TR_HU_3                          (0x8UL << RTC_TR_HU_Pos)           /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                       (12U)                             
-#define RTC_TR_MNT_Msk                       (0x7UL << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
-#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
-#define RTC_TR_MNT_0                         (0x1UL << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
-#define RTC_TR_MNT_1                         (0x2UL << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
-#define RTC_TR_MNT_2                         (0x4UL << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                       (8U)                              
-#define RTC_TR_MNU_Msk                       (0xFUL << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
-#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
-#define RTC_TR_MNU_0                         (0x1UL << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
-#define RTC_TR_MNU_1                         (0x2UL << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
-#define RTC_TR_MNU_2                         (0x4UL << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
-#define RTC_TR_MNU_3                         (0x8UL << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                        (4U)                              
-#define RTC_TR_ST_Msk                        (0x7UL << RTC_TR_ST_Pos)           /*!< 0x00000070 */
-#define RTC_TR_ST                            RTC_TR_ST_Msk                     
-#define RTC_TR_ST_0                          (0x1UL << RTC_TR_ST_Pos)           /*!< 0x00000010 */
-#define RTC_TR_ST_1                          (0x2UL << RTC_TR_ST_Pos)           /*!< 0x00000020 */
-#define RTC_TR_ST_2                          (0x4UL << RTC_TR_ST_Pos)           /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                        (0U)                              
-#define RTC_TR_SU_Msk                        (0xFUL << RTC_TR_SU_Pos)           /*!< 0x0000000F */
-#define RTC_TR_SU                            RTC_TR_SU_Msk                     
-#define RTC_TR_SU_0                          (0x1UL << RTC_TR_SU_Pos)           /*!< 0x00000001 */
-#define RTC_TR_SU_1                          (0x2UL << RTC_TR_SU_Pos)           /*!< 0x00000002 */
-#define RTC_TR_SU_2                          (0x4UL << RTC_TR_SU_Pos)           /*!< 0x00000004 */
-#define RTC_TR_SU_3                          (0x8UL << RTC_TR_SU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                        (20U)                             
-#define RTC_DR_YT_Msk                        (0xFUL << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
-#define RTC_DR_YT                            RTC_DR_YT_Msk                     
-#define RTC_DR_YT_0                          (0x1UL << RTC_DR_YT_Pos)           /*!< 0x00100000 */
-#define RTC_DR_YT_1                          (0x2UL << RTC_DR_YT_Pos)           /*!< 0x00200000 */
-#define RTC_DR_YT_2                          (0x4UL << RTC_DR_YT_Pos)           /*!< 0x00400000 */
-#define RTC_DR_YT_3                          (0x8UL << RTC_DR_YT_Pos)           /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                        (16U)                             
-#define RTC_DR_YU_Msk                        (0xFUL << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
-#define RTC_DR_YU                            RTC_DR_YU_Msk                     
-#define RTC_DR_YU_0                          (0x1UL << RTC_DR_YU_Pos)           /*!< 0x00010000 */
-#define RTC_DR_YU_1                          (0x2UL << RTC_DR_YU_Pos)           /*!< 0x00020000 */
-#define RTC_DR_YU_2                          (0x4UL << RTC_DR_YU_Pos)           /*!< 0x00040000 */
-#define RTC_DR_YU_3                          (0x8UL << RTC_DR_YU_Pos)           /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                       (13U)                             
-#define RTC_DR_WDU_Msk                       (0x7UL << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
-#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
-#define RTC_DR_WDU_0                         (0x1UL << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
-#define RTC_DR_WDU_1                         (0x2UL << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
-#define RTC_DR_WDU_2                         (0x4UL << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                        (12U)                             
-#define RTC_DR_MT_Msk                        (0x1UL << RTC_DR_MT_Pos)           /*!< 0x00001000 */
-#define RTC_DR_MT                            RTC_DR_MT_Msk                     
-#define RTC_DR_MU_Pos                        (8U)                              
-#define RTC_DR_MU_Msk                        (0xFUL << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
-#define RTC_DR_MU                            RTC_DR_MU_Msk                     
-#define RTC_DR_MU_0                          (0x1UL << RTC_DR_MU_Pos)           /*!< 0x00000100 */
-#define RTC_DR_MU_1                          (0x2UL << RTC_DR_MU_Pos)           /*!< 0x00000200 */
-#define RTC_DR_MU_2                          (0x4UL << RTC_DR_MU_Pos)           /*!< 0x00000400 */
-#define RTC_DR_MU_3                          (0x8UL << RTC_DR_MU_Pos)           /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                        (4U)                              
-#define RTC_DR_DT_Msk                        (0x3UL << RTC_DR_DT_Pos)           /*!< 0x00000030 */
-#define RTC_DR_DT                            RTC_DR_DT_Msk                     
-#define RTC_DR_DT_0                          (0x1UL << RTC_DR_DT_Pos)           /*!< 0x00000010 */
-#define RTC_DR_DT_1                          (0x2UL << RTC_DR_DT_Pos)           /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                        (0U)                              
-#define RTC_DR_DU_Msk                        (0xFUL << RTC_DR_DU_Pos)           /*!< 0x0000000F */
-#define RTC_DR_DU                            RTC_DR_DU_Msk                     
-#define RTC_DR_DU_0                          (0x1UL << RTC_DR_DU_Pos)           /*!< 0x00000001 */
-#define RTC_DR_DU_1                          (0x2UL << RTC_DR_DU_Pos)           /*!< 0x00000002 */
-#define RTC_DR_DU_2                          (0x4UL << RTC_DR_DU_Pos)           /*!< 0x00000004 */
-#define RTC_DR_DU_3                          (0x8UL << RTC_DR_DU_Pos)           /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                       (23U)                             
-#define RTC_CR_COE_Msk                       (0x1UL << RTC_CR_COE_Pos)          /*!< 0x00800000 */
-#define RTC_CR_COE                           RTC_CR_COE_Msk                    
-#define RTC_CR_OSEL_Pos                      (21U)                             
-#define RTC_CR_OSEL_Msk                      (0x3UL << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
-#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
-#define RTC_CR_OSEL_0                        (0x1UL << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                        (0x2UL << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                       (20U)                             
-#define RTC_CR_POL_Msk                       (0x1UL << RTC_CR_POL_Pos)          /*!< 0x00100000 */
-#define RTC_CR_POL                           RTC_CR_POL_Msk                    
-#define RTC_CR_COSEL_Pos                     (19U)                             
-#define RTC_CR_COSEL_Msk                     (0x1UL << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
-#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BKP_Pos                       (18U)                             
-#define RTC_CR_BKP_Msk                       (0x1UL << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
-#define RTC_CR_SUB1H_Pos                     (17U)                             
-#define RTC_CR_SUB1H_Msk                     (0x1UL << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
-#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
-#define RTC_CR_ADD1H_Pos                     (16U)                             
-#define RTC_CR_ADD1H_Msk                     (0x1UL << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
-#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
-#define RTC_CR_TSIE_Pos                      (15U)                             
-#define RTC_CR_TSIE_Msk                      (0x1UL << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
-#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
-#define RTC_CR_WUTIE_Pos                     (14U)                             
-#define RTC_CR_WUTIE_Msk                     (0x1UL << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
-#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
-#define RTC_CR_ALRBIE_Pos                    (13U)                             
-#define RTC_CR_ALRBIE_Msk                    (0x1UL << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
-#define RTC_CR_ALRAIE_Pos                    (12U)                             
-#define RTC_CR_ALRAIE_Msk                    (0x1UL << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
-#define RTC_CR_TSE_Pos                       (11U)                             
-#define RTC_CR_TSE_Msk                       (0x1UL << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
-#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
-#define RTC_CR_WUTE_Pos                      (10U)                             
-#define RTC_CR_WUTE_Msk                      (0x1UL << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
-#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
-#define RTC_CR_ALRBE_Pos                     (9U)                              
-#define RTC_CR_ALRBE_Msk                     (0x1UL << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
-#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
-#define RTC_CR_ALRAE_Pos                     (8U)                              
-#define RTC_CR_ALRAE_Msk                     (0x1UL << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
-#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
-#define RTC_CR_DCE_Pos                       (7U)                              
-#define RTC_CR_DCE_Msk                       (0x1UL << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
-#define RTC_CR_DCE                           RTC_CR_DCE_Msk                    
-#define RTC_CR_FMT_Pos                       (6U)                              
-#define RTC_CR_FMT_Msk                       (0x1UL << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
-#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
-#define RTC_CR_BYPSHAD_Pos                   (5U)                              
-#define RTC_CR_BYPSHAD_Msk                   (0x1UL << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
-#define RTC_CR_REFCKON_Pos                   (4U)                              
-#define RTC_CR_REFCKON_Msk                   (0x1UL << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
-#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
-#define RTC_CR_TSEDGE_Pos                    (3U)                              
-#define RTC_CR_TSEDGE_Msk                    (0x1UL << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
-#define RTC_CR_WUCKSEL_Pos                   (0U)                              
-#define RTC_CR_WUCKSEL_Msk                   (0x7UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
-#define RTC_CR_WUCKSEL_0                     (0x1UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1                     (0x2UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2                     (0x4UL << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
-
-/* Legacy defines */
-#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
-#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
-#define  RTC_CR_BCK     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos                  (16U)                             
-#define RTC_ISR_RECALPF_Msk                  (0x1UL << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
-#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
-#define RTC_ISR_TAMP3F_Pos                   (15U)                             
-#define RTC_ISR_TAMP3F_Msk                   (0x1UL << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
-#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
-#define RTC_ISR_TAMP2F_Pos                   (14U)                             
-#define RTC_ISR_TAMP2F_Msk                   (0x1UL << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
-#define RTC_ISR_TAMP1F_Pos                   (13U)                             
-#define RTC_ISR_TAMP1F_Msk                   (0x1UL << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
-#define RTC_ISR_TSOVF_Pos                    (12U)                             
-#define RTC_ISR_TSOVF_Msk                    (0x1UL << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
-#define RTC_ISR_TSF_Pos                      (11U)                             
-#define RTC_ISR_TSF_Msk                      (0x1UL << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
-#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
-#define RTC_ISR_WUTF_Pos                     (10U)                             
-#define RTC_ISR_WUTF_Msk                     (0x1UL << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
-#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
-#define RTC_ISR_ALRBF_Pos                    (9U)                              
-#define RTC_ISR_ALRBF_Msk                    (0x1UL << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
-#define RTC_ISR_ALRAF_Pos                    (8U)                              
-#define RTC_ISR_ALRAF_Msk                    (0x1UL << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
-#define RTC_ISR_INIT_Pos                     (7U)                              
-#define RTC_ISR_INIT_Msk                     (0x1UL << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
-#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
-#define RTC_ISR_INITF_Pos                    (6U)                              
-#define RTC_ISR_INITF_Msk                    (0x1UL << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
-#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
-#define RTC_ISR_RSF_Pos                      (5U)                              
-#define RTC_ISR_RSF_Msk                      (0x1UL << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
-#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
-#define RTC_ISR_INITS_Pos                    (4U)                              
-#define RTC_ISR_INITS_Msk                    (0x1UL << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
-#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
-#define RTC_ISR_SHPF_Pos                     (3U)                              
-#define RTC_ISR_SHPF_Msk                     (0x1UL << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
-#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
-#define RTC_ISR_WUTWF_Pos                    (2U)                              
-#define RTC_ISR_WUTWF_Msk                    (0x1UL << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
-#define RTC_ISR_ALRBWF_Pos                   (1U)                              
-#define RTC_ISR_ALRBWF_Msk                   (0x1UL << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
-#define RTC_ISR_ALRAWF_Pos                   (0U)                              
-#define RTC_ISR_ALRAWF_Msk                   (0x1UL << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos                (16U)                             
-#define RTC_PRER_PREDIV_A_Msk                (0x7FUL << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
-#define RTC_PRER_PREDIV_S_Pos                (0U)                              
-#define RTC_PRER_PREDIV_S_Msk                (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos                     (0U)                              
-#define RTC_WUTR_WUT_Msk                     (0xFFFFUL << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos                   (7U)                              
-#define RTC_CALIBR_DCS_Msk                   (0x1UL << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk                
-#define RTC_CALIBR_DC_Pos                    (0U)                              
-#define RTC_CALIBR_DC_Msk                    (0x1FUL << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
-#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk                 
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMAR_MSK4_Msk                  (0x1UL << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
-#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMAR_WDSEL_Msk                 (0x1UL << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
-#define RTC_ALRMAR_DT_Pos                    (28U)                             
-#define RTC_ALRMAR_DT_Msk                    (0x3UL << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
-#define RTC_ALRMAR_DT_0                      (0x1UL << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1                      (0x2UL << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos                    (24U)                             
-#define RTC_ALRMAR_DU_Msk                    (0xFUL << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
-#define RTC_ALRMAR_DU_0                      (0x1UL << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1                      (0x2UL << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2                      (0x4UL << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3                      (0x8UL << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMAR_MSK3_Msk                  (0x1UL << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
-#define RTC_ALRMAR_PM_Pos                    (22U)                             
-#define RTC_ALRMAR_PM_Msk                    (0x1UL << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
-#define RTC_ALRMAR_HT_Pos                    (20U)                             
-#define RTC_ALRMAR_HT_Msk                    (0x3UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
-#define RTC_ALRMAR_HT_0                      (0x1UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1                      (0x2UL << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos                    (16U)                             
-#define RTC_ALRMAR_HU_Msk                    (0xFUL << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
-#define RTC_ALRMAR_HU_0                      (0x1UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1                      (0x2UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2                      (0x4UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3                      (0x8UL << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMAR_MSK2_Msk                  (0x1UL << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
-#define RTC_ALRMAR_MNT_Pos                   (12U)                             
-#define RTC_ALRMAR_MNT_Msk                   (0x7UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
-#define RTC_ALRMAR_MNT_0                     (0x1UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1                     (0x2UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2                     (0x4UL << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos                   (8U)                              
-#define RTC_ALRMAR_MNU_Msk                   (0xFUL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
-#define RTC_ALRMAR_MNU_0                     (0x1UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1                     (0x2UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2                     (0x4UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3                     (0x8UL << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMAR_MSK1_Msk                  (0x1UL << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
-#define RTC_ALRMAR_ST_Pos                    (4U)                              
-#define RTC_ALRMAR_ST_Msk                    (0x7UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
-#define RTC_ALRMAR_ST_0                      (0x1UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1                      (0x2UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2                      (0x4UL << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos                    (0U)                              
-#define RTC_ALRMAR_SU_Msk                    (0xFUL << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
-#define RTC_ALRMAR_SU_0                      (0x1UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1                      (0x2UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2                      (0x4UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3                      (0x8UL << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
-#define RTC_ALRMBR_MSK4_Msk                  (0x1UL << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
-#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
-#define RTC_ALRMBR_WDSEL_Msk                 (0x1UL << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
-#define RTC_ALRMBR_DT_Pos                    (28U)                             
-#define RTC_ALRMBR_DT_Msk                    (0x3UL << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
-#define RTC_ALRMBR_DT_0                      (0x1UL << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1                      (0x2UL << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos                    (24U)                             
-#define RTC_ALRMBR_DU_Msk                    (0xFUL << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
-#define RTC_ALRMBR_DU_0                      (0x1UL << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1                      (0x2UL << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2                      (0x4UL << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3                      (0x8UL << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
-#define RTC_ALRMBR_MSK3_Msk                  (0x1UL << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
-#define RTC_ALRMBR_PM_Pos                    (22U)                             
-#define RTC_ALRMBR_PM_Msk                    (0x1UL << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
-#define RTC_ALRMBR_HT_Pos                    (20U)                             
-#define RTC_ALRMBR_HT_Msk                    (0x3UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
-#define RTC_ALRMBR_HT_0                      (0x1UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1                      (0x2UL << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos                    (16U)                             
-#define RTC_ALRMBR_HU_Msk                    (0xFUL << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
-#define RTC_ALRMBR_HU_0                      (0x1UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1                      (0x2UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2                      (0x4UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3                      (0x8UL << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
-#define RTC_ALRMBR_MSK2_Msk                  (0x1UL << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
-#define RTC_ALRMBR_MNT_Pos                   (12U)                             
-#define RTC_ALRMBR_MNT_Msk                   (0x7UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
-#define RTC_ALRMBR_MNT_0                     (0x1UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1                     (0x2UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2                     (0x4UL << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos                   (8U)                              
-#define RTC_ALRMBR_MNU_Msk                   (0xFUL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
-#define RTC_ALRMBR_MNU_0                     (0x1UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1                     (0x2UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2                     (0x4UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3                     (0x8UL << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
-#define RTC_ALRMBR_MSK1_Msk                  (0x1UL << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
-#define RTC_ALRMBR_ST_Pos                    (4U)                              
-#define RTC_ALRMBR_ST_Msk                    (0x7UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
-#define RTC_ALRMBR_ST_0                      (0x1UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1                      (0x2UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2                      (0x4UL << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos                    (0U)                              
-#define RTC_ALRMBR_SU_Msk                    (0xFUL << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
-#define RTC_ALRMBR_SU_0                      (0x1UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1                      (0x2UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2                      (0x4UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3                      (0x8UL << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos                      (0U)                              
-#define RTC_WPR_KEY_Msk                      (0xFFUL << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
-#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                       (0U)                              
-#define RTC_SSR_SS_Msk                       (0xFFFFUL << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
-#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
-#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
-#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
-#define RTC_SHIFTR_ADD1S_Msk                 (0x1UL << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos                      (22U)                             
-#define RTC_TSTR_PM_Msk                      (0x1UL << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
-#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
-#define RTC_TSTR_HT_Pos                      (20U)                             
-#define RTC_TSTR_HT_Msk                      (0x3UL << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
-#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
-#define RTC_TSTR_HT_0                        (0x1UL << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                        (0x2UL << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos                      (16U)                             
-#define RTC_TSTR_HU_Msk                      (0xFUL << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
-#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
-#define RTC_TSTR_HU_0                        (0x1UL << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                        (0x2UL << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                        (0x4UL << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                        (0x8UL << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos                     (12U)                             
-#define RTC_TSTR_MNT_Msk                     (0x7UL << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
-#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
-#define RTC_TSTR_MNT_0                       (0x1UL << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                       (0x2UL << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                       (0x4UL << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos                     (8U)                              
-#define RTC_TSTR_MNU_Msk                     (0xFUL << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
-#define RTC_TSTR_MNU_0                       (0x1UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                       (0x2UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                       (0x4UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                       (0x8UL << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos                      (4U)                              
-#define RTC_TSTR_ST_Msk                      (0x7UL << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
-#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
-#define RTC_TSTR_ST_0                        (0x1UL << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                        (0x2UL << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                        (0x4UL << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos                      (0U)                              
-#define RTC_TSTR_SU_Msk                      (0xFUL << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
-#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
-#define RTC_TSTR_SU_0                        (0x1UL << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                        (0x2UL << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                        (0x4UL << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                        (0x8UL << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos                     (13U)                             
-#define RTC_TSDR_WDU_Msk                     (0x7UL << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
-#define RTC_TSDR_WDU_0                       (0x1UL << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                       (0x2UL << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                       (0x4UL << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos                      (12U)                             
-#define RTC_TSDR_MT_Msk                      (0x1UL << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
-#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
-#define RTC_TSDR_MU_Pos                      (8U)                              
-#define RTC_TSDR_MU_Msk                      (0xFUL << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
-#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
-#define RTC_TSDR_MU_0                        (0x1UL << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                        (0x2UL << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                        (0x4UL << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                        (0x8UL << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos                      (4U)                              
-#define RTC_TSDR_DT_Msk                      (0x3UL << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
-#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
-#define RTC_TSDR_DT_0                        (0x1UL << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                        (0x2UL << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos                      (0U)                              
-#define RTC_TSDR_DU_Msk                      (0xFUL << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
-#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
-#define RTC_TSDR_DU_0                        (0x1UL << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                        (0x2UL << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                        (0x4UL << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                        (0x8UL << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos                     (0U)                              
-#define RTC_TSSSR_SS_Msk                     (0xFFFFUL << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos                    (15U)                             
-#define RTC_CALR_CALP_Msk                    (0x1UL << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
-#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
-#define RTC_CALR_CALW8_Pos                   (14U)                             
-#define RTC_CALR_CALW8_Msk                   (0x1UL << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
-#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
-#define RTC_CALR_CALW16_Pos                  (13U)                             
-#define RTC_CALR_CALW16_Msk                  (0x1UL << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
-#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
-#define RTC_CALR_CALM_Pos                    (0U)                              
-#define RTC_CALR_CALM_Msk                    (0x1FFUL << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
-#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
-#define RTC_CALR_CALM_0                      (0x001UL << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
-#define RTC_CALR_CALM_1                      (0x002UL << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
-#define RTC_CALR_CALM_2                      (0x004UL << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
-#define RTC_CALR_CALM_3                      (0x008UL << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
-#define RTC_CALR_CALM_4                      (0x010UL << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
-#define RTC_CALR_CALM_5                      (0x020UL << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
-#define RTC_CALR_CALM_6                      (0x040UL << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
-#define RTC_CALR_CALM_7                      (0x080UL << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
-#define RTC_CALR_CALM_8                      (0x100UL << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)                             
-#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk        
-#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)                             
-#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk           
-#define RTC_TAFCR_TAMPPRCH_Pos               (13U)                             
-#define RTC_TAFCR_TAMPPRCH_Msk               (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk            
-#define RTC_TAFCR_TAMPPRCH_0                 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1                 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos                (11U)                             
-#define RTC_TAFCR_TAMPFLT_Msk                (0x3UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk             
-#define RTC_TAFCR_TAMPFLT_0                  (0x1UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1                  (0x2UL << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos               (8U)                              
-#define RTC_TAFCR_TAMPFREQ_Msk               (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk            
-#define RTC_TAFCR_TAMPFREQ_0                 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1                 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2                 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos                 (7U)                              
-#define RTC_TAFCR_TAMPTS_Msk                 (0x1UL << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk              
-#define RTC_TAFCR_TAMP3TRG_Pos               (6U)                              
-#define RTC_TAFCR_TAMP3TRG_Msk               (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
-#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk            
-#define RTC_TAFCR_TAMP3E_Pos                 (5U)                              
-#define RTC_TAFCR_TAMP3E_Msk                 (0x1UL << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
-#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk              
-#define RTC_TAFCR_TAMP2TRG_Pos               (4U)                              
-#define RTC_TAFCR_TAMP2TRG_Msk               (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk            
-#define RTC_TAFCR_TAMP2E_Pos                 (3U)                              
-#define RTC_TAFCR_TAMP2E_Msk                 (0x1UL << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk              
-#define RTC_TAFCR_TAMPIE_Pos                 (2U)                              
-#define RTC_TAFCR_TAMPIE_Msk                 (0x1UL << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk              
-#define RTC_TAFCR_TAMP1TRG_Pos               (1U)                              
-#define RTC_TAFCR_TAMP1TRG_Msk               (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk            
-#define RTC_TAFCR_TAMP1E_Pos                 (0U)                              
-#define RTC_TAFCR_TAMP1E_Msk                 (0x1UL << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk              
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMASSR_MASKSS_Msk              (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
-#define RTC_ALRMASSR_MASKSS_0                (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1                (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2                (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3                (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos                  (0U)                              
-#define RTC_ALRMASSR_SS_Msk                  (0x7FFFUL << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
-#define RTC_ALRMBSSR_MASKSS_Msk              (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
-#define RTC_ALRMBSSR_MASKSS_0                (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1                (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2                (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3                (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
-#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                        (0U)                              
-#define RTC_BKP0R_Msk                        (0xFFFFFFFFUL << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                            RTC_BKP0R_Msk                     
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                        (0U)                              
-#define RTC_BKP1R_Msk                        (0xFFFFFFFFUL << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                            RTC_BKP1R_Msk                     
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                        (0U)                              
-#define RTC_BKP2R_Msk                        (0xFFFFFFFFUL << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                            RTC_BKP2R_Msk                     
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                        (0U)                              
-#define RTC_BKP3R_Msk                        (0xFFFFFFFFUL << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                            RTC_BKP3R_Msk                     
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                        (0U)                              
-#define RTC_BKP4R_Msk                        (0xFFFFFFFFUL << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                            RTC_BKP4R_Msk                     
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                        (0U)                              
-#define RTC_BKP5R_Msk                        (0xFFFFFFFFUL << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                            RTC_BKP5R_Msk                     
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                        (0U)                              
-#define RTC_BKP6R_Msk                        (0xFFFFFFFFUL << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                            RTC_BKP6R_Msk                     
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                        (0U)                              
-#define RTC_BKP7R_Msk                        (0xFFFFFFFFUL << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                            RTC_BKP7R_Msk                     
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                        (0U)                              
-#define RTC_BKP8R_Msk                        (0xFFFFFFFFUL << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                            RTC_BKP8R_Msk                     
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                        (0U)                              
-#define RTC_BKP9R_Msk                        (0xFFFFFFFFUL << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                            RTC_BKP9R_Msk                     
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                       (0U)                              
-#define RTC_BKP10R_Msk                       (0xFFFFFFFFUL << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                           RTC_BKP10R_Msk                    
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                       (0U)                              
-#define RTC_BKP11R_Msk                       (0xFFFFFFFFUL << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                           RTC_BKP11R_Msk                    
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                       (0U)                              
-#define RTC_BKP12R_Msk                       (0xFFFFFFFFUL << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                           RTC_BKP12R_Msk                    
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                       (0U)                              
-#define RTC_BKP13R_Msk                       (0xFFFFFFFFUL << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                           RTC_BKP13R_Msk                    
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                       (0U)                              
-#define RTC_BKP14R_Msk                       (0xFFFFFFFFUL << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                           RTC_BKP14R_Msk                    
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                       (0U)                              
-#define RTC_BKP15R_Msk                       (0xFFFFFFFFUL << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                           RTC_BKP15R_Msk                    
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                       (0U)                              
-#define RTC_BKP16R_Msk                       (0xFFFFFFFFUL << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                           RTC_BKP16R_Msk                    
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                       (0U)                              
-#define RTC_BKP17R_Msk                       (0xFFFFFFFFUL << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                           RTC_BKP17R_Msk                    
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                       (0U)                              
-#define RTC_BKP18R_Msk                       (0xFFFFFFFFUL << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                           RTC_BKP18R_Msk                    
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                       (0U)                              
-#define RTC_BKP19R_Msk                       (0xFFFFFFFFUL << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                           RTC_BKP19R_Msk                    
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R_Pos                       (0U)                              
-#define RTC_BKP20R_Msk                       (0xFFFFFFFFUL << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP20R                           RTC_BKP20R_Msk                    
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R_Pos                       (0U)                              
-#define RTC_BKP21R_Msk                       (0xFFFFFFFFUL << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP21R                           RTC_BKP21R_Msk                    
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R_Pos                       (0U)                              
-#define RTC_BKP22R_Msk                       (0xFFFFFFFFUL << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP22R                           RTC_BKP22R_Msk                    
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R_Pos                       (0U)                              
-#define RTC_BKP23R_Msk                       (0xFFFFFFFFUL << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP23R                           RTC_BKP23R_Msk                    
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R_Pos                       (0U)                              
-#define RTC_BKP24R_Msk                       (0xFFFFFFFFUL << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP24R                           RTC_BKP24R_Msk                    
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R_Pos                       (0U)                              
-#define RTC_BKP25R_Msk                       (0xFFFFFFFFUL << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP25R                           RTC_BKP25R_Msk                    
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R_Pos                       (0U)                              
-#define RTC_BKP26R_Msk                       (0xFFFFFFFFUL << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP26R                           RTC_BKP26R_Msk                    
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R_Pos                       (0U)                              
-#define RTC_BKP27R_Msk                       (0xFFFFFFFFUL << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP27R                           RTC_BKP27R_Msk                    
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R_Pos                       (0U)                              
-#define RTC_BKP28R_Msk                       (0xFFFFFFFFUL << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP28R                           RTC_BKP28R_Msk                    
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R_Pos                       (0U)                              
-#define RTC_BKP29R_Msk                       (0xFFFFFFFFUL << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP29R                           RTC_BKP29R_Msk                    
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R_Pos                       (0U)                              
-#define RTC_BKP30R_Msk                       (0xFFFFFFFFUL << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP30R                           RTC_BKP30R_Msk                    
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R_Pos                       (0U)                              
-#define RTC_BKP31R_Msk                       (0xFFFFFFFFUL << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
-#define RTC_BKP31R                           RTC_BKP31R_Msk                    
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
- */
-#define SPI_I2S_SUPPORT    
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos                    (0U)                               
-#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
-#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos                    (1U)                               
-#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
-#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos                    (2U)                               
-#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
-#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos                      (3U)                               
-#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
-#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
-#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
-#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos                     (6U)                               
-#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
-#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos                (7U)                               
-#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
-#define SPI_CR1_SSI_Pos                     (8U)                               
-#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
-#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos                     (9U)                               
-#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
-#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos                  (10U)                              
-#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
-#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
-#define SPI_CR1_DFF_Pos                     (11U)                              
-#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
-#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
-#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos                   (13U)                              
-#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
-#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos                  (14U)                              
-#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos                (15U)                              
-#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
-#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
-#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos                    (2U)                               
-#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
-#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
-#define SPI_CR2_FRF_Pos                     (4U)                               
-#define SPI_CR2_FRF_Msk                     (0x1UL << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
-#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
-#define SPI_CR2_ERRIE_Pos                   (5U)                               
-#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
-#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos                  (6U)                               
-#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos                   (7U)                               
-#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
-#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos                     (0U)                               
-#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
-#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos                      (1U)                               
-#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
-#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos                   (2U)                               
-#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
-#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
-#define SPI_SR_UDR_Pos                      (3U)                               
-#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
-#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos                   (4U)                               
-#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
-#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos                     (5U)                               
-#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
-#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
-#define SPI_SR_OVR_Pos                      (6U)                               
-#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
-#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
-#define SPI_SR_BSY_Pos                      (7U)                               
-#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
-#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
-#define SPI_SR_FRE_Pos                      (8U)                               
-#define SPI_SR_FRE_Msk                      (0x1UL << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
-#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos                       (0U)                               
-#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
-#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
-#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
-#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
-#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos               (0U)                               
-#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos              (1U)                               
-#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos               (3U)                               
-#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
-
-#define SPI_I2SCFGR_I2SSTD_Pos              (4U)                               
-#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)                               
-#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
-
-#define SPI_I2SCFGR_I2SCFG_Pos              (8U)                               
-#define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos                (10U)                              
-#define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              
-#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos                (0U)                               
-#define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos                   (8U)                               
-#define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
-#define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos                 (9U)                               
-#define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
-#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)                                   
-#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
-#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU_Pos           (0U)                                   
-#define SYSCFG_PMC_USB_PU_Msk           (0x1UL << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
-#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
-#define SYSCFG_PMC_LCD_CAPA_Pos         (1U)                                   
-#define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
-#define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
-#define SYSCFG_PMC_LCD_CAPA_0           (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
-#define SYSCFG_PMC_LCD_CAPA_1           (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
-#define SYSCFG_PMC_LCD_CAPA_2           (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
-#define SYSCFG_PMC_LCD_CAPA_3           (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
-#define SYSCFG_PMC_LCD_CAPA_4           (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
-#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
-#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
-#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
-#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         (0x00006000U)                          /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         (0x00007000U)                          /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
-#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
-#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
-#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
-#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
-#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
-#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
-#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
-#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
-#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
-#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
-#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
-#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define RI_ICR_IC1OS_Pos                (0U)                                   
-#define RI_ICR_IC1OS_Msk                (0xFUL << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
-#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define RI_ICR_IC1OS_0                  (0x1UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
-#define RI_ICR_IC1OS_1                  (0x2UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
-#define RI_ICR_IC1OS_2                  (0x4UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
-#define RI_ICR_IC1OS_3                  (0x8UL << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
-
-#define RI_ICR_IC2OS_Pos                (4U)                                   
-#define RI_ICR_IC2OS_Msk                (0xFUL << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
-#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define RI_ICR_IC2OS_0                  (0x1UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
-#define RI_ICR_IC2OS_1                  (0x2UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
-#define RI_ICR_IC2OS_2                  (0x4UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
-#define RI_ICR_IC2OS_3                  (0x8UL << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
-
-#define RI_ICR_IC3OS_Pos                (8U)                                   
-#define RI_ICR_IC3OS_Msk                (0xFUL << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
-#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define RI_ICR_IC3OS_0                  (0x1UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
-#define RI_ICR_IC3OS_1                  (0x2UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
-#define RI_ICR_IC3OS_2                  (0x4UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
-#define RI_ICR_IC3OS_3                  (0x8UL << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
-
-#define RI_ICR_IC4OS_Pos                (12U)                                  
-#define RI_ICR_IC4OS_Msk                (0xFUL << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
-#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define RI_ICR_IC4OS_0                  (0x1UL << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
-#define RI_ICR_IC4OS_1                  (0x2UL << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
-#define RI_ICR_IC4OS_2                  (0x4UL << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
-#define RI_ICR_IC4OS_3                  (0x8UL << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
-
-#define RI_ICR_TIM_Pos                  (16U)                                  
-#define RI_ICR_TIM_Msk                  (0x3UL << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
-#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
-#define RI_ICR_TIM_0                    (0x1UL << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
-#define RI_ICR_TIM_1                    (0x2UL << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
-
-#define RI_ICR_IC1_Pos                  (18U)                                  
-#define RI_ICR_IC1_Msk                  (0x1UL << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
-#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
-#define RI_ICR_IC2_Pos                  (19U)                                  
-#define RI_ICR_IC2_Msk                  (0x1UL << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
-#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
-#define RI_ICR_IC3_Pos                  (20U)                                  
-#define RI_ICR_IC3_Msk                  (0x1UL << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
-#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
-#define RI_ICR_IC4_Pos                  (21U)                                  
-#define RI_ICR_IC4_Msk                  (0x1UL << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
-#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define RI_ASCR1_CH_Pos                 (0U)                                   
-#define RI_ASCR1_CH_Msk                 (0x7BFDFFFFUL << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
-#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
-#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
-#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
-#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
-#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
-#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
-#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
-#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
-#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
-#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
-#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
-#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
-#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
-#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
-#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
-#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
-#define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
-#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
-#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
-#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
-#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
-#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
-#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
-#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
-#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
-#define RI_ASCR1_VCOMP_Pos              (26U)                                  
-#define RI_ASCR1_VCOMP_Msk              (0x1UL << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
-#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
-#define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
-#define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
-#define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
-#define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
-#define RI_ASCR1_SCM_Pos                (31U)                                  
-#define RI_ASCR1_SCM_Msk                (0x1UL << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
-#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
-#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
-#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
-#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
-#define RI_ASCR2_GR6_Pos                (4U)                                   
-#define RI_ASCR2_GR6_Msk                (0x1800003UL << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
-#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
-#define RI_ASCR2_GR6_1                  (0x0000001UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
-#define RI_ASCR2_GR6_2                  (0x0000002UL << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
-#define RI_ASCR2_GR6_3                  (0x0800000UL << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
-#define RI_ASCR2_GR6_4                  (0x1000000UL << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
-#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
-#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
-#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
-#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
-#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
-#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
-#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
-#define RI_ASCR2_CH0b_Pos               (16U)                                  
-#define RI_ASCR2_CH0b_Msk               (0x1UL << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
-#define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
-#define RI_ASCR2_CH1b_Pos               (17U)                                  
-#define RI_ASCR2_CH1b_Msk               (0x1UL << RI_ASCR2_CH1b_Pos)            /*!< 0x00020000 */
-#define RI_ASCR2_CH1b                   RI_ASCR2_CH1b_Msk                      /*!< CH1b selection bit */
-#define RI_ASCR2_CH2b_Pos               (18U)                                  
-#define RI_ASCR2_CH2b_Msk               (0x1UL << RI_ASCR2_CH2b_Pos)            /*!< 0x00040000 */
-#define RI_ASCR2_CH2b                   RI_ASCR2_CH2b_Msk                      /*!< CH2b selection bit */
-#define RI_ASCR2_CH3b_Pos               (19U)                                  
-#define RI_ASCR2_CH3b_Msk               (0x1UL << RI_ASCR2_CH3b_Pos)            /*!< 0x00080000 */
-#define RI_ASCR2_CH3b                   RI_ASCR2_CH3b_Msk                      /*!< CH3b selection bit */
-#define RI_ASCR2_CH6b_Pos               (20U)                                  
-#define RI_ASCR2_CH6b_Msk               (0x1UL << RI_ASCR2_CH6b_Pos)            /*!< 0x00100000 */
-#define RI_ASCR2_CH6b                   RI_ASCR2_CH6b_Msk                      /*!< CH6b selection bit */
-#define RI_ASCR2_CH7b_Pos               (21U)                                  
-#define RI_ASCR2_CH7b_Msk               (0x1UL << RI_ASCR2_CH7b_Pos)            /*!< 0x00200000 */
-#define RI_ASCR2_CH7b                   RI_ASCR2_CH7b_Msk                      /*!< CH7b selection bit */
-#define RI_ASCR2_CH8b_Pos               (22U)                                  
-#define RI_ASCR2_CH8b_Msk               (0x1UL << RI_ASCR2_CH8b_Pos)            /*!< 0x00400000 */
-#define RI_ASCR2_CH8b                   RI_ASCR2_CH8b_Msk                      /*!< CH8b selection bit */
-#define RI_ASCR2_CH9b_Pos               (23U)                                  
-#define RI_ASCR2_CH9b_Msk               (0x1UL << RI_ASCR2_CH9b_Pos)            /*!< 0x00800000 */
-#define RI_ASCR2_CH9b                   RI_ASCR2_CH9b_Msk                      /*!< CH9b selection bit */
-#define RI_ASCR2_CH10b_Pos              (24U)                                  
-#define RI_ASCR2_CH10b_Msk              (0x1UL << RI_ASCR2_CH10b_Pos)           /*!< 0x01000000 */
-#define RI_ASCR2_CH10b                  RI_ASCR2_CH10b_Msk                     /*!< CH10b selection bit */
-#define RI_ASCR2_CH11b_Pos              (25U)                                  
-#define RI_ASCR2_CH11b_Msk              (0x1UL << RI_ASCR2_CH11b_Pos)           /*!< 0x02000000 */
-#define RI_ASCR2_CH11b                  RI_ASCR2_CH11b_Msk                     /*!< CH11b selection bit */
-#define RI_ASCR2_CH12b_Pos              (26U)                                  
-#define RI_ASCR2_CH12b_Msk              (0x1UL << RI_ASCR2_CH12b_Pos)           /*!< 0x04000000 */
-#define RI_ASCR2_CH12b                  RI_ASCR2_CH12b_Msk                     /*!< CH12b selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define RI_HYSCR1_PA_Pos                (0U)                                   
-#define RI_HYSCR1_PA_Msk                (0xFFFFUL << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
-#define RI_HYSCR1_PA_0                  (0x0001UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR1_PA_1                  (0x0002UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR1_PA_2                  (0x0004UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR1_PA_3                  (0x0008UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR1_PA_4                  (0x0010UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR1_PA_5                  (0x0020UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR1_PA_6                  (0x0040UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR1_PA_7                  (0x0080UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR1_PA_8                  (0x0100UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR1_PA_9                  (0x0200UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR1_PA_10                 (0x0400UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR1_PA_11                 (0x0800UL << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR1_PA_12                 (0x1000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR1_PA_13                 (0x2000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR1_PA_14                 (0x4000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR1_PA_15                 (0x8000UL << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR1_PB_Pos                (16U)                                  
-#define RI_HYSCR1_PB_Msk                (0xFFFFUL << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
-#define RI_HYSCR1_PB_0                  (0x0001UL << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR1_PB_1                  (0x0002UL << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR1_PB_2                  (0x0004UL << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR1_PB_3                  (0x0008UL << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR1_PB_4                  (0x0010UL << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR1_PB_5                  (0x0020UL << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR1_PB_6                  (0x0040UL << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR1_PB_7                  (0x0080UL << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR1_PB_8                  (0x0100UL << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR1_PB_9                  (0x0200UL << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR1_PB_10                 (0x0400UL << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR1_PB_11                 (0x0800UL << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR1_PB_12                 (0x1000UL << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR1_PB_13                 (0x2000UL << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR1_PB_14                 (0x4000UL << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR1_PB_15                 (0x8000UL << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define RI_HYSCR2_PC_Pos                (0U)                                   
-#define RI_HYSCR2_PC_Msk                (0xFFFFUL << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
-#define RI_HYSCR2_PC_0                  (0x0001UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR2_PC_1                  (0x0002UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR2_PC_2                  (0x0004UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR2_PC_3                  (0x0008UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR2_PC_4                  (0x0010UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR2_PC_5                  (0x0020UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR2_PC_6                  (0x0040UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR2_PC_7                  (0x0080UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR2_PC_8                  (0x0100UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR2_PC_9                  (0x0200UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR2_PC_10                 (0x0400UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR2_PC_11                 (0x0800UL << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR2_PC_12                 (0x1000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR2_PC_13                 (0x2000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR2_PC_14                 (0x4000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR2_PC_15                 (0x8000UL << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
-
-#define RI_HYSCR2_PD_Pos                (16U)                                  
-#define RI_HYSCR2_PD_Msk                (0xFFFFUL << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
-#define RI_HYSCR2_PD_0                  (0x0001UL << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR2_PD_1                  (0x0002UL << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR2_PD_2                  (0x0004UL << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR2_PD_3                  (0x0008UL << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR2_PD_4                  (0x0010UL << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR2_PD_5                  (0x0020UL << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR2_PD_6                  (0x0040UL << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR2_PD_7                  (0x0080UL << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR2_PD_8                  (0x0100UL << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR2_PD_9                  (0x0200UL << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR2_PD_10                 (0x0400UL << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR2_PD_11                 (0x0800UL << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR2_PD_12                 (0x1000UL << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR2_PD_13                 (0x2000UL << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR2_PD_14                 (0x4000UL << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR2_PD_15                 (0x8000UL << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define RI_HYSCR3_PE_Pos                (0U)                                   
-#define RI_HYSCR3_PE_Msk                (0xFFFFUL << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
-#define RI_HYSCR3_PE_0                  (0x0001UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR3_PE_1                  (0x0002UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR3_PE_2                  (0x0004UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR3_PE_3                  (0x0008UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR3_PE_4                  (0x0010UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR3_PE_5                  (0x0020UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR3_PE_6                  (0x0040UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR3_PE_7                  (0x0080UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR3_PE_8                  (0x0100UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR3_PE_9                  (0x0200UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR3_PE_10                 (0x0400UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR3_PE_11                 (0x0800UL << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR3_PE_12                 (0x1000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR3_PE_13                 (0x2000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR3_PE_14                 (0x4000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR3_PE_15                 (0x8000UL << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
-#define RI_HYSCR3_PF_Pos                (16U)                                  
-#define RI_HYSCR3_PF_Msk                (0xFFFFUL << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
-#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
-#define RI_HYSCR3_PF_0                  (0x0001UL << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
-#define RI_HYSCR3_PF_1                  (0x0002UL << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
-#define RI_HYSCR3_PF_2                  (0x0004UL << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
-#define RI_HYSCR3_PF_3                  (0x0008UL << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
-#define RI_HYSCR3_PF_4                  (0x0010UL << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
-#define RI_HYSCR3_PF_5                  (0x0020UL << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
-#define RI_HYSCR3_PF_6                  (0x0040UL << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
-#define RI_HYSCR3_PF_7                  (0x0080UL << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
-#define RI_HYSCR3_PF_8                  (0x0100UL << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
-#define RI_HYSCR3_PF_9                  (0x0200UL << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
-#define RI_HYSCR3_PF_10                 (0x0400UL << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
-#define RI_HYSCR3_PF_11                 (0x0800UL << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
-#define RI_HYSCR3_PF_12                 (0x1000UL << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
-#define RI_HYSCR3_PF_13                 (0x2000UL << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
-#define RI_HYSCR3_PF_14                 (0x4000UL << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
-#define RI_HYSCR3_PF_15                 (0x8000UL << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define RI_HYSCR4_PG_Pos                (0U)                                   
-#define RI_HYSCR4_PG_Msk                (0xFFFFUL << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
-#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
-#define RI_HYSCR4_PG_0                  (0x0001UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
-#define RI_HYSCR4_PG_1                  (0x0002UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
-#define RI_HYSCR4_PG_2                  (0x0004UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
-#define RI_HYSCR4_PG_3                  (0x0008UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
-#define RI_HYSCR4_PG_4                  (0x0010UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
-#define RI_HYSCR4_PG_5                  (0x0020UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
-#define RI_HYSCR4_PG_6                  (0x0040UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
-#define RI_HYSCR4_PG_7                  (0x0080UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
-#define RI_HYSCR4_PG_8                  (0x0100UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
-#define RI_HYSCR4_PG_9                  (0x0200UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
-#define RI_HYSCR4_PG_10                 (0x0400UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
-#define RI_HYSCR4_PG_11                 (0x0800UL << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
-#define RI_HYSCR4_PG_12                 (0x1000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
-#define RI_HYSCR4_PG_13                 (0x2000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
-#define RI_HYSCR4_PG_14                 (0x4000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
-#define RI_HYSCR4_PG_15                 (0x8000UL << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define RI_ASMR1_PA_Pos                 (0U)                                   
-#define RI_ASMR1_PA_Msk                 (0xFFFFUL << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_ASMR1_PA_0                   (0x0001UL << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_ASMR1_PA_1                   (0x0002UL << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_ASMR1_PA_2                   (0x0004UL << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_ASMR1_PA_3                   (0x0008UL << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_ASMR1_PA_4                   (0x0010UL << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_ASMR1_PA_5                   (0x0020UL << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_ASMR1_PA_6                   (0x0040UL << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_ASMR1_PA_7                   (0x0080UL << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_ASMR1_PA_8                   (0x0100UL << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_ASMR1_PA_9                   (0x0200UL << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_ASMR1_PA_10                  (0x0400UL << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_ASMR1_PA_11                  (0x0800UL << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_ASMR1_PA_12                  (0x1000UL << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_ASMR1_PA_13                  (0x2000UL << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_ASMR1_PA_14                  (0x4000UL << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_ASMR1_PA_15                  (0x8000UL << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define RI_CMR1_PA_Pos                  (0U)                                   
-#define RI_CMR1_PA_Msk                  (0xFFFFUL << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
-#define RI_CMR1_PA_0                    (0x0001UL << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
-#define RI_CMR1_PA_1                    (0x0002UL << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
-#define RI_CMR1_PA_2                    (0x0004UL << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
-#define RI_CMR1_PA_3                    (0x0008UL << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
-#define RI_CMR1_PA_4                    (0x0010UL << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
-#define RI_CMR1_PA_5                    (0x0020UL << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
-#define RI_CMR1_PA_6                    (0x0040UL << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
-#define RI_CMR1_PA_7                    (0x0080UL << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
-#define RI_CMR1_PA_8                    (0x0100UL << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
-#define RI_CMR1_PA_9                    (0x0200UL << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
-#define RI_CMR1_PA_10                   (0x0400UL << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
-#define RI_CMR1_PA_11                   (0x0800UL << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
-#define RI_CMR1_PA_12                   (0x1000UL << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
-#define RI_CMR1_PA_13                   (0x2000UL << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
-#define RI_CMR1_PA_14                   (0x4000UL << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
-#define RI_CMR1_PA_15                   (0x8000UL << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define RI_CICR1_PA_Pos                 (0U)                                   
-#define RI_CICR1_PA_Msk                 (0xFFFFUL << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
-#define RI_CICR1_PA_0                   (0x0001UL << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
-#define RI_CICR1_PA_1                   (0x0002UL << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
-#define RI_CICR1_PA_2                   (0x0004UL << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
-#define RI_CICR1_PA_3                   (0x0008UL << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
-#define RI_CICR1_PA_4                   (0x0010UL << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
-#define RI_CICR1_PA_5                   (0x0020UL << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
-#define RI_CICR1_PA_6                   (0x0040UL << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
-#define RI_CICR1_PA_7                   (0x0080UL << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
-#define RI_CICR1_PA_8                   (0x0100UL << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
-#define RI_CICR1_PA_9                   (0x0200UL << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
-#define RI_CICR1_PA_10                  (0x0400UL << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
-#define RI_CICR1_PA_11                  (0x0800UL << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
-#define RI_CICR1_PA_12                  (0x1000UL << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
-#define RI_CICR1_PA_13                  (0x2000UL << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
-#define RI_CICR1_PA_14                  (0x4000UL << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
-#define RI_CICR1_PA_15                  (0x8000UL << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define RI_ASMR2_PB_Pos                 (0U)                                   
-#define RI_ASMR2_PB_Msk                 (0xFFFFUL << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_ASMR2_PB_0                   (0x0001UL << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_ASMR2_PB_1                   (0x0002UL << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_ASMR2_PB_2                   (0x0004UL << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_ASMR2_PB_3                   (0x0008UL << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_ASMR2_PB_4                   (0x0010UL << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_ASMR2_PB_5                   (0x0020UL << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_ASMR2_PB_6                   (0x0040UL << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_ASMR2_PB_7                   (0x0080UL << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_ASMR2_PB_8                   (0x0100UL << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_ASMR2_PB_9                   (0x0200UL << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_ASMR2_PB_10                  (0x0400UL << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_ASMR2_PB_11                  (0x0800UL << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_ASMR2_PB_12                  (0x1000UL << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_ASMR2_PB_13                  (0x2000UL << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_ASMR2_PB_14                  (0x4000UL << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_ASMR2_PB_15                  (0x8000UL << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define RI_CMR2_PB_Pos                  (0U)                                   
-#define RI_CMR2_PB_Msk                  (0xFFFFUL << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
-#define RI_CMR2_PB_0                    (0x0001UL << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
-#define RI_CMR2_PB_1                    (0x0002UL << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
-#define RI_CMR2_PB_2                    (0x0004UL << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
-#define RI_CMR2_PB_3                    (0x0008UL << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
-#define RI_CMR2_PB_4                    (0x0010UL << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
-#define RI_CMR2_PB_5                    (0x0020UL << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
-#define RI_CMR2_PB_6                    (0x0040UL << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
-#define RI_CMR2_PB_7                    (0x0080UL << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
-#define RI_CMR2_PB_8                    (0x0100UL << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
-#define RI_CMR2_PB_9                    (0x0200UL << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
-#define RI_CMR2_PB_10                   (0x0400UL << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
-#define RI_CMR2_PB_11                   (0x0800UL << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
-#define RI_CMR2_PB_12                   (0x1000UL << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
-#define RI_CMR2_PB_13                   (0x2000UL << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
-#define RI_CMR2_PB_14                   (0x4000UL << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
-#define RI_CMR2_PB_15                   (0x8000UL << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define RI_CICR2_PB_Pos                 (0U)                                   
-#define RI_CICR2_PB_Msk                 (0xFFFFUL << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
-#define RI_CICR2_PB_0                   (0x0001UL << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
-#define RI_CICR2_PB_1                   (0x0002UL << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
-#define RI_CICR2_PB_2                   (0x0004UL << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
-#define RI_CICR2_PB_3                   (0x0008UL << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
-#define RI_CICR2_PB_4                   (0x0010UL << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
-#define RI_CICR2_PB_5                   (0x0020UL << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
-#define RI_CICR2_PB_6                   (0x0040UL << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
-#define RI_CICR2_PB_7                   (0x0080UL << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
-#define RI_CICR2_PB_8                   (0x0100UL << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
-#define RI_CICR2_PB_9                   (0x0200UL << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
-#define RI_CICR2_PB_10                  (0x0400UL << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
-#define RI_CICR2_PB_11                  (0x0800UL << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
-#define RI_CICR2_PB_12                  (0x1000UL << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
-#define RI_CICR2_PB_13                  (0x2000UL << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
-#define RI_CICR2_PB_14                  (0x4000UL << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
-#define RI_CICR2_PB_15                  (0x8000UL << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define RI_ASMR3_PC_Pos                 (0U)                                   
-#define RI_ASMR3_PC_Msk                 (0xFFFFUL << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_ASMR3_PC_0                   (0x0001UL << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_ASMR3_PC_1                   (0x0002UL << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_ASMR3_PC_2                   (0x0004UL << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_ASMR3_PC_3                   (0x0008UL << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_ASMR3_PC_4                   (0x0010UL << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_ASMR3_PC_5                   (0x0020UL << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_ASMR3_PC_6                   (0x0040UL << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_ASMR3_PC_7                   (0x0080UL << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_ASMR3_PC_8                   (0x0100UL << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_ASMR3_PC_9                   (0x0200UL << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_ASMR3_PC_10                  (0x0400UL << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_ASMR3_PC_11                  (0x0800UL << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_ASMR3_PC_12                  (0x1000UL << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_ASMR3_PC_13                  (0x2000UL << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_ASMR3_PC_14                  (0x4000UL << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_ASMR3_PC_15                  (0x8000UL << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define RI_CMR3_PC_Pos                  (0U)                                   
-#define RI_CMR3_PC_Msk                  (0xFFFFUL << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
-#define RI_CMR3_PC_0                    (0x0001UL << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
-#define RI_CMR3_PC_1                    (0x0002UL << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
-#define RI_CMR3_PC_2                    (0x0004UL << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
-#define RI_CMR3_PC_3                    (0x0008UL << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
-#define RI_CMR3_PC_4                    (0x0010UL << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
-#define RI_CMR3_PC_5                    (0x0020UL << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
-#define RI_CMR3_PC_6                    (0x0040UL << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
-#define RI_CMR3_PC_7                    (0x0080UL << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
-#define RI_CMR3_PC_8                    (0x0100UL << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
-#define RI_CMR3_PC_9                    (0x0200UL << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
-#define RI_CMR3_PC_10                   (0x0400UL << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
-#define RI_CMR3_PC_11                   (0x0800UL << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
-#define RI_CMR3_PC_12                   (0x1000UL << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
-#define RI_CMR3_PC_13                   (0x2000UL << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
-#define RI_CMR3_PC_14                   (0x4000UL << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
-#define RI_CMR3_PC_15                   (0x8000UL << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define RI_CICR3_PC_Pos                 (0U)                                   
-#define RI_CICR3_PC_Msk                 (0xFFFFUL << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
-#define RI_CICR3_PC_0                   (0x0001UL << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
-#define RI_CICR3_PC_1                   (0x0002UL << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
-#define RI_CICR3_PC_2                   (0x0004UL << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
-#define RI_CICR3_PC_3                   (0x0008UL << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
-#define RI_CICR3_PC_4                   (0x0010UL << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
-#define RI_CICR3_PC_5                   (0x0020UL << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
-#define RI_CICR3_PC_6                   (0x0040UL << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
-#define RI_CICR3_PC_7                   (0x0080UL << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
-#define RI_CICR3_PC_8                   (0x0100UL << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
-#define RI_CICR3_PC_9                   (0x0200UL << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
-#define RI_CICR3_PC_10                  (0x0400UL << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
-#define RI_CICR3_PC_11                  (0x0800UL << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
-#define RI_CICR3_PC_12                  (0x1000UL << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
-#define RI_CICR3_PC_13                  (0x2000UL << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
-#define RI_CICR3_PC_14                  (0x4000UL << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
-#define RI_CICR3_PC_15                  (0x8000UL << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define RI_ASMR4_PF_Pos                 (0U)                                   
-#define RI_ASMR4_PF_Msk                 (0xFFFFUL << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_ASMR4_PF_0                   (0x0001UL << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_ASMR4_PF_1                   (0x0002UL << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_ASMR4_PF_2                   (0x0004UL << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_ASMR4_PF_3                   (0x0008UL << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_ASMR4_PF_4                   (0x0010UL << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_ASMR4_PF_5                   (0x0020UL << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_ASMR4_PF_6                   (0x0040UL << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_ASMR4_PF_7                   (0x0080UL << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_ASMR4_PF_8                   (0x0100UL << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_ASMR4_PF_9                   (0x0200UL << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_ASMR4_PF_10                  (0x0400UL << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_ASMR4_PF_11                  (0x0800UL << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_ASMR4_PF_12                  (0x1000UL << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_ASMR4_PF_13                  (0x2000UL << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_ASMR4_PF_14                  (0x4000UL << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_ASMR4_PF_15                  (0x8000UL << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define RI_CMR4_PF_Pos                  (0U)                                   
-#define RI_CMR4_PF_Msk                  (0xFFFFUL << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
-#define RI_CMR4_PF_0                    (0x0001UL << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
-#define RI_CMR4_PF_1                    (0x0002UL << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
-#define RI_CMR4_PF_2                    (0x0004UL << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
-#define RI_CMR4_PF_3                    (0x0008UL << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
-#define RI_CMR4_PF_4                    (0x0010UL << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
-#define RI_CMR4_PF_5                    (0x0020UL << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
-#define RI_CMR4_PF_6                    (0x0040UL << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
-#define RI_CMR4_PF_7                    (0x0080UL << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
-#define RI_CMR4_PF_8                    (0x0100UL << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
-#define RI_CMR4_PF_9                    (0x0200UL << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
-#define RI_CMR4_PF_10                   (0x0400UL << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
-#define RI_CMR4_PF_11                   (0x0800UL << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
-#define RI_CMR4_PF_12                   (0x1000UL << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
-#define RI_CMR4_PF_13                   (0x2000UL << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
-#define RI_CMR4_PF_14                   (0x4000UL << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
-#define RI_CMR4_PF_15                   (0x8000UL << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define RI_CICR4_PF_Pos                 (0U)                                   
-#define RI_CICR4_PF_Msk                 (0xFFFFUL << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
-#define RI_CICR4_PF_0                   (0x0001UL << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
-#define RI_CICR4_PF_1                   (0x0002UL << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
-#define RI_CICR4_PF_2                   (0x0004UL << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
-#define RI_CICR4_PF_3                   (0x0008UL << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
-#define RI_CICR4_PF_4                   (0x0010UL << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
-#define RI_CICR4_PF_5                   (0x0020UL << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
-#define RI_CICR4_PF_6                   (0x0040UL << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
-#define RI_CICR4_PF_7                   (0x0080UL << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
-#define RI_CICR4_PF_8                   (0x0100UL << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
-#define RI_CICR4_PF_9                   (0x0200UL << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
-#define RI_CICR4_PF_10                  (0x0400UL << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
-#define RI_CICR4_PF_11                  (0x0800UL << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
-#define RI_CICR4_PF_12                  (0x1000UL << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
-#define RI_CICR4_PF_13                  (0x2000UL << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
-#define RI_CICR4_PF_14                  (0x4000UL << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
-#define RI_CICR4_PF_15                  (0x8000UL << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define RI_ASMR5_PG_Pos                 (0U)                                   
-#define RI_ASMR5_PG_Msk                 (0xFFFFUL << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_ASMR5_PG_0                   (0x0001UL << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_ASMR5_PG_1                   (0x0002UL << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_ASMR5_PG_2                   (0x0004UL << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_ASMR5_PG_3                   (0x0008UL << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_ASMR5_PG_4                   (0x0010UL << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_ASMR5_PG_5                   (0x0020UL << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_ASMR5_PG_6                   (0x0040UL << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_ASMR5_PG_7                   (0x0080UL << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_ASMR5_PG_8                   (0x0100UL << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_ASMR5_PG_9                   (0x0200UL << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_ASMR5_PG_10                  (0x0400UL << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_ASMR5_PG_11                  (0x0800UL << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_ASMR5_PG_12                  (0x1000UL << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_ASMR5_PG_13                  (0x2000UL << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_ASMR5_PG_14                  (0x4000UL << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_ASMR5_PG_15                  (0x8000UL << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define RI_CMR5_PG_Pos                  (0U)                                   
-#define RI_CMR5_PG_Msk                  (0xFFFFUL << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
-#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
-#define RI_CMR5_PG_0                    (0x0001UL << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
-#define RI_CMR5_PG_1                    (0x0002UL << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
-#define RI_CMR5_PG_2                    (0x0004UL << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
-#define RI_CMR5_PG_3                    (0x0008UL << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
-#define RI_CMR5_PG_4                    (0x0010UL << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
-#define RI_CMR5_PG_5                    (0x0020UL << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
-#define RI_CMR5_PG_6                    (0x0040UL << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
-#define RI_CMR5_PG_7                    (0x0080UL << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
-#define RI_CMR5_PG_8                    (0x0100UL << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
-#define RI_CMR5_PG_9                    (0x0200UL << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
-#define RI_CMR5_PG_10                   (0x0400UL << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
-#define RI_CMR5_PG_11                   (0x0800UL << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
-#define RI_CMR5_PG_12                   (0x1000UL << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
-#define RI_CMR5_PG_13                   (0x2000UL << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
-#define RI_CMR5_PG_14                   (0x4000UL << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
-#define RI_CMR5_PG_15                   (0x8000UL << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define RI_CICR5_PG_Pos                 (0U)                                   
-#define RI_CICR5_PG_Msk                 (0xFFFFUL << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
-#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
-#define RI_CICR5_PG_0                   (0x0001UL << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
-#define RI_CICR5_PG_1                   (0x0002UL << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
-#define RI_CICR5_PG_2                   (0x0004UL << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
-#define RI_CICR5_PG_3                   (0x0008UL << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
-#define RI_CICR5_PG_4                   (0x0010UL << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
-#define RI_CICR5_PG_5                   (0x0020UL << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
-#define RI_CICR5_PG_6                   (0x0040UL << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
-#define RI_CICR5_PG_7                   (0x0080UL << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
-#define RI_CICR5_PG_8                   (0x0100UL << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
-#define RI_CICR5_PG_9                   (0x0200UL << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
-#define RI_CICR5_PG_10                  (0x0400UL << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
-#define RI_CICR5_PG_11                  (0x0800UL << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
-#define RI_CICR5_PG_12                  (0x1000UL << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
-#define RI_CICR5_PG_13                  (0x2000UL << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
-#define RI_CICR5_PG_14                  (0x4000UL << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
-#define RI_CICR5_PG_15                  (0x8000UL << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos                     (0U)                               
-#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
-#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos                    (1U)                               
-#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
-#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
-#define TIM_CR1_URS_Pos                     (2U)                               
-#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
-#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
-#define TIM_CR1_OPM_Pos                     (3U)                               
-#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
-#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos                     (4U)                               
-#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
-#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
-
-#define TIM_CR1_CMS_Pos                     (5U)                               
-#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
-#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos                    (7U)                               
-#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
-#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos                     (8U)                               
-#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
-#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
-#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCDS_Pos                    (3U)                               
-#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
-#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos                     (4U)                               
-#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
-#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
-#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
-#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos                    (7U)                               
-#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
-#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos                    (0U)                               
-#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
-#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
-
-#define TIM_SMCR_OCCS_Pos                   (3U)                               
-#define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos                     (4U)                               
-#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
-#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
-#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
-#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos                    (7U)                               
-#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
-#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos                    (8U)                               
-#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
-#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos                   (12U)                              
-#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
-#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos                    (14U)                              
-#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
-#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos                    (15U)                              
-#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
-#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos                    (0U)                               
-#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
-#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos                  (1U)                               
-#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
-#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos                  (2U)                               
-#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
-#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos                  (3U)                               
-#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
-#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos                  (4U)                               
-#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
-#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE_Pos                    (6U)                               
-#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
-#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE_Pos                    (8U)                               
-#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
-#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos                  (9U)                               
-#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
-#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos                  (10U)                              
-#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
-#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos                  (11U)                              
-#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
-#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos                  (12U)                              
-#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
-#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos                    (14U)                              
-#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
-#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos                      (0U)                               
-#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
-#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos                    (1U)                               
-#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
-#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos                    (2U)                               
-#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
-#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos                    (3U)                               
-#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
-#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos                    (4U)                               
-#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
-#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_TIF_Pos                      (6U)                               
-#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
-#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
-#define TIM_SR_CC1OF_Pos                    (9U)                               
-#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
-#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos                    (10U)                              
-#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
-#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos                    (11U)                              
-#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
-#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos                    (12U)                              
-#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
-#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos                      (0U)                               
-#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
-#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos                    (1U)                               
-#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
-#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos                    (2U)                               
-#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
-#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos                    (3U)                               
-#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
-#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos                    (4U)                               
-#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
-#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_TG_Pos                      (6U)                               
-#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
-#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos                  (0U)                               
-#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos                 (2U)                               
-#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos                 (3U)                               
-#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos                  (4U)                               
-#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos                 (7U)                               
-#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos                  (8U)                               
-#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos                 (10U)                              
-#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos                 (11U)                              
-#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos                  (12U)                              
-#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos                 (15U)                              
-#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos                (2U)                               
-#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos                  (4U)                               
-#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos                (10U)                              
-#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos                  (12U)                              
-#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos                  (0U)                               
-#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos                 (2U)                               
-#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos                 (3U)                               
-#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos                  (4U)                               
-#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos                 (7U)                               
-#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos                  (8U)                               
-#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos                 (10U)                              
-#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos                 (11U)                              
-#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos                  (12U)                              
-#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos                 (15U)                              
-#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos                (2U)                               
-#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos                  (4U)                               
-#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos                (10U)                              
-#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos                  (12U)                              
-#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos                   (0U)                               
-#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
-#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos                   (1U)                               
-#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
-#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NP_Pos                  (3U)                               
-#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
-#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos                   (4U)                               
-#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
-#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos                   (5U)                               
-#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
-#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NP_Pos                  (7U)                               
-#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
-#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos                   (8U)                               
-#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
-#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos                   (9U)                               
-#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
-#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NP_Pos                  (11U)                              
-#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
-#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos                   (12U)                              
-#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
-#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos                   (13U)                              
-#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
-#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos                  (15U)                              
-#define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos                     (0U)                               
-#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos                     (0U)                               
-#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
-#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos                     (0U)                               
-#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos                   (0U)                               
-#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos                   (0U)                               
-#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos                   (0U)                               
-#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos                   (0U)                               
-#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos                     (0U)                               
-#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
-#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
-#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
-#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
-#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
-#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos                     (8U)                               
-#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
-#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
-#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
-#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
-#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
-#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos                   (0U)                               
-#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1RMP_Pos                   (0U)                               
-#define TIM_OR_TI1RMP_Msk                   (0x3UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
-#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define TIM_OR_TI1RMP_0                     (0x1UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
-#define TIM_OR_TI1RMP_1                     (0x2UL << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
-
-#define TIM_OR_ETR_RMP_Pos                  (2U)                               
-#define TIM_OR_ETR_RMP_Msk                  (0x1UL << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
-#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define TIM_OR_TI1_RMP_RI_Pos               (3U)                               
-#define TIM_OR_TI1_RMP_RI_Msk               (0x1UL << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
-#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM9_OR_ITR1_RMP_Pos                (2U)                               
-#define TIM9_OR_ITR1_RMP_Msk                (0x1UL << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
-#define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM2_OR_ITR1_RMP_Pos                (0U)                               
-#define TIM2_OR_ITR1_RMP_Msk                (0x1UL << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
-#define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define TIM3_OR_ITR2_RMP_Pos                (0U)                               
-#define TIM3_OR_ITR2_RMP_Msk                (0x1UL << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
-#define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos                     (0U)                               
-#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
-#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
-#define USART_SR_FE_Pos                     (1U)                               
-#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
-#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
-#define USART_SR_NE_Pos                     (2U)                               
-#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
-#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos                    (3U)                               
-#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
-#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
-#define USART_SR_IDLE_Pos                   (4U)                               
-#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
-#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos                   (5U)                               
-#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
-#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos                     (6U)                               
-#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
-#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
-#define USART_SR_TXE_Pos                    (7U)                               
-#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
-#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos                    (8U)                               
-#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
-#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos                    (9U)                               
-#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
-#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos                     (0U)                               
-#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
-#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION_Pos          (0U)                               
-#define USART_BRR_DIV_FRACTION_Msk          (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_Pos          (4U)                               
-#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos                   (0U)                               
-#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
-#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
-#define USART_CR1_RWU_Pos                   (1U)                               
-#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
-#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos                    (2U)                               
-#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
-#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
-#define USART_CR1_TE_Pos                    (3U)                               
-#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
-#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos                (4U)                               
-#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
-#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos                (5U)                               
-#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
-#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos                  (6U)                               
-#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
-#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos                 (7U)                               
-#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
-#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos                  (8U)                               
-#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
-#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos                    (9U)                               
-#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
-#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
-#define USART_CR1_PCE_Pos                   (10U)                              
-#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
-#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos                  (11U)                              
-#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
-#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
-#define USART_CR1_M_Pos                     (12U)                              
-#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
-#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
-#define USART_CR1_UE_Pos                    (13U)                              
-#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
-#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
-#define USART_CR1_OVER8_Pos                 (15U)                              
-#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
-#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos                   (0U)                               
-#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
-#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos                  (5U)                               
-#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
-#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos                 (6U)                               
-#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
-#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos                  (8U)                               
-#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
-#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos                  (9U)                               
-#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
-#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos                  (10U)                              
-#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
-#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos                 (11U)                              
-#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
-#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos                  (12U)                              
-#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
-#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
-#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos                 (14U)                              
-#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
-#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos                   (0U)                               
-#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
-#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos                  (1U)                               
-#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
-#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos                  (2U)                               
-#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
-#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos                 (3U)                               
-#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
-#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos                  (4U)                               
-#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
-#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos                  (5U)                               
-#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
-#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos                  (6U)                               
-#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
-#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos                  (7U)                               
-#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
-#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos                  (8U)                               
-#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
-#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos                  (9U)                               
-#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
-#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos                 (10U)                              
-#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
-#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos                (11U)                              
-#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
-#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos                  (0U)                               
-#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
-#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
-#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
-#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
-#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
-#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
-#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
-#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
-#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos                   (8U)                               
-#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
-#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define USB_EP_CTR_RX_Pos                     (15U)                            
-#define USB_EP_CTR_RX_Msk                     (0x1UL << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
-#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                    (14U)                            
-#define USB_EP_DTOG_RX_Msk                    (0x1UL << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                     (12U)                            
-#define USB_EPRX_STAT_Msk                     (0x3UL << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
-#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                      (11U)                            
-#define USB_EP_SETUP_Msk                      (0x1UL << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
-#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                    (9U)                             
-#define USB_EP_T_FIELD_Msk                    (0x3UL << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
-#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
-#define USB_EP_KIND_Pos                       (8U)                             
-#define USB_EP_KIND_Msk                       (0x1UL << USB_EP_KIND_Pos)        /*!< 0x00000100 */
-#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                     (7U)                             
-#define USB_EP_CTR_TX_Msk                     (0x1UL << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
-#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                    (6U)                             
-#define USB_EP_DTOG_TX_Msk                    (0x1UL << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                     (4U)                             
-#define USB_EPTX_STAT_Msk                     (0x3UL << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
-#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                  (0U)                             
-#define USB_EPADDR_FIELD_Msk                  (0xFUL << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                  (9U)                             
-#define USB_EP_TYPE_MASK_Msk                  (0x3UL << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                       (0U)                             
-#define USB_EP0R_EA_Msk                       (0xFUL << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                  (4U)                             
-#define USB_EP0R_STAT_TX_Msk                  (0x3UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                    (0x1UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                    (0x2UL << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP0R_DTOG_TX_Msk                  (0x1UL << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                   (7U)                             
-#define USB_EP0R_CTR_TX_Msk                   (0x1UL << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                  (8U)                             
-#define USB_EP0R_EP_KIND_Msk                  (0x1UL << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP0R_EP_TYPE_Msk                  (0x3UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                    (0x1UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                    (0x2UL << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                    (11U)                            
-#define USB_EP0R_SETUP_Msk                    (0x1UL << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                  (12U)                            
-#define USB_EP0R_STAT_RX_Msk                  (0x3UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                    (0x1UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                    (0x2UL << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP0R_DTOG_RX_Msk                  (0x1UL << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                   (15U)                            
-#define USB_EP0R_CTR_RX_Msk                   (0x1UL << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                       (0U)                             
-#define USB_EP1R_EA_Msk                       (0xFUL << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                  (4U)                             
-#define USB_EP1R_STAT_TX_Msk                  (0x3UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                    (0x1UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                    (0x2UL << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP1R_DTOG_TX_Msk                  (0x1UL << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                   (7U)                             
-#define USB_EP1R_CTR_TX_Msk                   (0x1UL << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                  (8U)                             
-#define USB_EP1R_EP_KIND_Msk                  (0x1UL << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP1R_EP_TYPE_Msk                  (0x3UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                    (0x1UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                    (0x2UL << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                    (11U)                            
-#define USB_EP1R_SETUP_Msk                    (0x1UL << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                  (12U)                            
-#define USB_EP1R_STAT_RX_Msk                  (0x3UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                    (0x1UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                    (0x2UL << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP1R_DTOG_RX_Msk                  (0x1UL << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                   (15U)                            
-#define USB_EP1R_CTR_RX_Msk                   (0x1UL << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                       (0U)                             
-#define USB_EP2R_EA_Msk                       (0xFUL << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                  (4U)                             
-#define USB_EP2R_STAT_TX_Msk                  (0x3UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                    (0x1UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                    (0x2UL << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP2R_DTOG_TX_Msk                  (0x1UL << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                   (7U)                             
-#define USB_EP2R_CTR_TX_Msk                   (0x1UL << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                  (8U)                             
-#define USB_EP2R_EP_KIND_Msk                  (0x1UL << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP2R_EP_TYPE_Msk                  (0x3UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                    (0x1UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                    (0x2UL << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                    (11U)                            
-#define USB_EP2R_SETUP_Msk                    (0x1UL << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                  (12U)                            
-#define USB_EP2R_STAT_RX_Msk                  (0x3UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                    (0x1UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                    (0x2UL << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP2R_DTOG_RX_Msk                  (0x1UL << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                   (15U)                            
-#define USB_EP2R_CTR_RX_Msk                   (0x1UL << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                       (0U)                             
-#define USB_EP3R_EA_Msk                       (0xFUL << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                  (4U)                             
-#define USB_EP3R_STAT_TX_Msk                  (0x3UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                    (0x1UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                    (0x2UL << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP3R_DTOG_TX_Msk                  (0x1UL << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                   (7U)                             
-#define USB_EP3R_CTR_TX_Msk                   (0x1UL << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                  (8U)                             
-#define USB_EP3R_EP_KIND_Msk                  (0x1UL << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP3R_EP_TYPE_Msk                  (0x3UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                    (0x1UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                    (0x2UL << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                    (11U)                            
-#define USB_EP3R_SETUP_Msk                    (0x1UL << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                  (12U)                            
-#define USB_EP3R_STAT_RX_Msk                  (0x3UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                    (0x1UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                    (0x2UL << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP3R_DTOG_RX_Msk                  (0x1UL << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                   (15U)                            
-#define USB_EP3R_CTR_RX_Msk                   (0x1UL << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                       (0U)                             
-#define USB_EP4R_EA_Msk                       (0xFUL << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                  (4U)                             
-#define USB_EP4R_STAT_TX_Msk                  (0x3UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                    (0x1UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                    (0x2UL << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP4R_DTOG_TX_Msk                  (0x1UL << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                   (7U)                             
-#define USB_EP4R_CTR_TX_Msk                   (0x1UL << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                  (8U)                             
-#define USB_EP4R_EP_KIND_Msk                  (0x1UL << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP4R_EP_TYPE_Msk                  (0x3UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                    (0x1UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                    (0x2UL << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                    (11U)                            
-#define USB_EP4R_SETUP_Msk                    (0x1UL << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                  (12U)                            
-#define USB_EP4R_STAT_RX_Msk                  (0x3UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                    (0x1UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                    (0x2UL << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP4R_DTOG_RX_Msk                  (0x1UL << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                   (15U)                            
-#define USB_EP4R_CTR_RX_Msk                   (0x1UL << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                       (0U)                             
-#define USB_EP5R_EA_Msk                       (0xFUL << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                  (4U)                             
-#define USB_EP5R_STAT_TX_Msk                  (0x3UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                    (0x1UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                    (0x2UL << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP5R_DTOG_TX_Msk                  (0x1UL << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                   (7U)                             
-#define USB_EP5R_CTR_TX_Msk                   (0x1UL << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                  (8U)                             
-#define USB_EP5R_EP_KIND_Msk                  (0x1UL << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP5R_EP_TYPE_Msk                  (0x3UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                    (0x1UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                    (0x2UL << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                    (11U)                            
-#define USB_EP5R_SETUP_Msk                    (0x1UL << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                  (12U)                            
-#define USB_EP5R_STAT_RX_Msk                  (0x3UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                    (0x1UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                    (0x2UL << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP5R_DTOG_RX_Msk                  (0x1UL << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                   (15U)                            
-#define USB_EP5R_CTR_RX_Msk                   (0x1UL << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                       (0U)                             
-#define USB_EP6R_EA_Msk                       (0xFUL << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                  (4U)                             
-#define USB_EP6R_STAT_TX_Msk                  (0x3UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                    (0x1UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                    (0x2UL << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP6R_DTOG_TX_Msk                  (0x1UL << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                   (7U)                             
-#define USB_EP6R_CTR_TX_Msk                   (0x1UL << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                  (8U)                             
-#define USB_EP6R_EP_KIND_Msk                  (0x1UL << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP6R_EP_TYPE_Msk                  (0x3UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                    (0x1UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                    (0x2UL << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                    (11U)                            
-#define USB_EP6R_SETUP_Msk                    (0x1UL << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                  (12U)                            
-#define USB_EP6R_STAT_RX_Msk                  (0x3UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                    (0x1UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                    (0x2UL << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP6R_DTOG_RX_Msk                  (0x1UL << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                   (15U)                            
-#define USB_EP6R_CTR_RX_Msk                   (0x1UL << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                       (0U)                             
-#define USB_EP7R_EA_Msk                       (0xFUL << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
-#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                  (4U)                             
-#define USB_EP7R_STAT_TX_Msk                  (0x3UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                    (0x1UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                    (0x2UL << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                  (6U)                             
-#define USB_EP7R_DTOG_TX_Msk                  (0x1UL << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                   (7U)                             
-#define USB_EP7R_CTR_TX_Msk                   (0x1UL << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                  (8U)                             
-#define USB_EP7R_EP_KIND_Msk                  (0x1UL << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                  (9U)                             
-#define USB_EP7R_EP_TYPE_Msk                  (0x3UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                    (0x1UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                    (0x2UL << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                    (11U)                            
-#define USB_EP7R_SETUP_Msk                    (0x1UL << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                  (12U)                            
-#define USB_EP7R_STAT_RX_Msk                  (0x3UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                    (0x1UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                    (0x2UL << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                  (14U)                            
-#define USB_EP7R_DTOG_RX_Msk                  (0x1UL << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                   (15U)                            
-#define USB_EP7R_CTR_RX_Msk                   (0x1UL << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                     (0U)                             
-#define USB_CNTR_FRES_Msk                     (0x1UL << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
-#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
-#define USB_CNTR_PDWN_Pos                     (1U)                             
-#define USB_CNTR_PDWN_Msk                     (0x1UL << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
-#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
-#define USB_CNTR_LPMODE_Pos                   (2U)                             
-#define USB_CNTR_LPMODE_Msk                   (0x1UL << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
-#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
-#define USB_CNTR_FSUSP_Pos                    (3U)                             
-#define USB_CNTR_FSUSP_Msk                    (0x1UL << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
-#define USB_CNTR_RESUME_Pos                   (4U)                             
-#define USB_CNTR_RESUME_Msk                   (0x1UL << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
-#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
-#define USB_CNTR_ESOFM_Pos                    (8U)                             
-#define USB_CNTR_ESOFM_Msk                    (0x1UL << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                     (9U)                             
-#define USB_CNTR_SOFM_Msk                     (0x1UL << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
-#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                   (10U)                            
-#define USB_CNTR_RESETM_Msk                   (0x1UL << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
-#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                    (11U)                            
-#define USB_CNTR_SUSPM_Msk                    (0x1UL << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                    (12U)                            
-#define USB_CNTR_WKUPM_Msk                    (0x1UL << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                     (13U)                            
-#define USB_CNTR_ERRM_Msk                     (0x1UL << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
-#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                  (14U)                            
-#define USB_CNTR_PMAOVRM_Msk                  (0x1UL << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                     (15U)                            
-#define USB_CNTR_CTRM_Msk                     (0x1UL << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
-#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                    (0U)                             
-#define USB_ISTR_EP_ID_Msk                    (0xFUL << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                      (4U)                             
-#define USB_ISTR_DIR_Msk                      (0x1UL << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
-#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
-#define USB_ISTR_ESOF_Pos                     (8U)                             
-#define USB_ISTR_ESOF_Msk                     (0x1UL << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
-#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                      (9U)                             
-#define USB_ISTR_SOF_Msk                      (0x1UL << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
-#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
-#define USB_ISTR_RESET_Pos                    (10U)                            
-#define USB_ISTR_RESET_Msk                    (0x1UL << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
-#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
-#define USB_ISTR_SUSP_Pos                     (11U)                            
-#define USB_ISTR_SUSP_Msk                     (0x1UL << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
-#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
-#define USB_ISTR_WKUP_Pos                     (12U)                            
-#define USB_ISTR_WKUP_Msk                     (0x1UL << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
-#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
-#define USB_ISTR_ERR_Pos                      (13U)                            
-#define USB_ISTR_ERR_Msk                      (0x1UL << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
-#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
-#define USB_ISTR_PMAOVR_Pos                   (14U)                            
-#define USB_ISTR_PMAOVR_Msk                   (0x1UL << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                      (15U)                            
-#define USB_ISTR_CTR_Msk                      (0x1UL << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
-#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                        (0U)                             
-#define USB_FNR_FN_Msk                        (0x7FFUL << USB_FNR_FN_Pos)       /*!< 0x000007FF */
-#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
-#define USB_FNR_LSOF_Pos                      (11U)                            
-#define USB_FNR_LSOF_Msk                      (0x3UL << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
-#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
-#define USB_FNR_LCK_Pos                       (13U)                            
-#define USB_FNR_LCK_Msk                       (0x1UL << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
-#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
-#define USB_FNR_RXDM_Pos                      (14U)                            
-#define USB_FNR_RXDM_Msk                      (0x1UL << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
-#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                      (15U)                            
-#define USB_FNR_RXDP_Msk                      (0x1UL << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
-#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                     (0U)                             
-#define USB_DADDR_ADD_Msk                     (0x7FUL << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
-#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                    (0U)                             
-#define USB_DADDR_ADD0_Msk                    (0x1UL << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
-#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
-#define USB_DADDR_ADD1_Pos                    (1U)                             
-#define USB_DADDR_ADD1_Msk                    (0x1UL << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
-#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
-#define USB_DADDR_ADD2_Pos                    (2U)                             
-#define USB_DADDR_ADD2_Msk                    (0x1UL << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
-#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
-#define USB_DADDR_ADD3_Pos                    (3U)                             
-#define USB_DADDR_ADD3_Msk                    (0x1UL << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
-#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
-#define USB_DADDR_ADD4_Pos                    (4U)                             
-#define USB_DADDR_ADD4_Msk                    (0x1UL << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
-#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
-#define USB_DADDR_ADD5_Pos                    (5U)                             
-#define USB_DADDR_ADD5_Msk                    (0x1UL << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
-#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
-#define USB_DADDR_ADD6_Pos                    (6U)                             
-#define USB_DADDR_ADD6_Msk                    (0x1UL << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
-#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
-
-#define USB_DADDR_EF_Pos                      (7U)                             
-#define USB_DADDR_EF_Msk                      (0x1UL << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
-#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define USB_BTABLE_BTABLE_Pos                 (3U)                             
-#define USB_BTABLE_BTABLE_Msk                 (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)                             
-#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)                             
-#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)                             
-#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)                             
-#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)                             
-#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)                             
-#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)                             
-#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)                             
-#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)                             
-#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)                             
-#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)                             
-#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)                             
-#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)                             
-#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)                             
-#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)                             
-#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)                             
-#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)                             
-#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)                             
-#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)                             
-#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)                             
-#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)                             
-#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)                             
-#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)                             
-#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)                             
-#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)                             
-#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT0_RX_BLSIZE_Msk              (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)                             
-#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT1_RX_BLSIZE_Msk              (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)                             
-#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT2_RX_BLSIZE_Msk              (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)                             
-#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT3_RX_BLSIZE_Msk              (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)                             
-#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT4_RX_BLSIZE_Msk              (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)                             
-#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT5_RX_BLSIZE_Msk              (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)                             
-#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT6_RX_BLSIZE_Msk              (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)                             
-#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)                            
-#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos              (15U)                            
-#define USB_COUNT7_RX_BLSIZE_Msk              (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos                       (0U)                               
-#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
-#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
-#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
-#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
-#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
-#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
-#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
-#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CR_T0 WWDG_CR_T_0
-#define  WWDG_CR_T1 WWDG_CR_T_1
-#define  WWDG_CR_T2 WWDG_CR_T_2
-#define  WWDG_CR_T3 WWDG_CR_T_3
-#define  WWDG_CR_T4 WWDG_CR_T_4
-#define  WWDG_CR_T5 WWDG_CR_T_5
-#define  WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos                    (7U)                               
-#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
-#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos                      (0U)                               
-#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
-#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
-#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
-#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
-#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
-#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
-#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
-#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
-
-/* Legacy defines */
-#define  WWDG_CFR_W0 WWDG_CFR_W_0
-#define  WWDG_CFR_W1 WWDG_CFR_W_1
-#define  WWDG_CFR_W2 WWDG_CFR_W_2
-#define  WWDG_CFR_W3 WWDG_CFR_W_3
-#define  WWDG_CFR_W4 WWDG_CFR_W_4
-#define  WWDG_CFR_W5 WWDG_CFR_W_5
-#define  WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos                  (7U)                               
-#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
-
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos                    (9U)                               
-#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
-#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos                    (0U)                               
-#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
-#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
-
-/****************************** AES Instances *********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-
-#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-                                       
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-#define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L162xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
deleted file mode 100644
index b4f78895b6b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *            - Configuration section that allows to select:
-  *              - The STM32L1xx device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral�s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx
-  * @{
-  */
-    
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L1)
-#define STM32L1
-#endif /* STM32L1 */
-
-
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
-    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \
-    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \
-    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE)
-  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
-  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
-  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
-  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
-  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
-  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
-  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
-  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
-  /* #define STM32L151xDX */   /*!< STM32L151VD-X Devices */
-  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
-  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
-  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
-  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
-  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
-  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
-  /* #define STM32L152xDX */   /*!< STM32L152VD-X Devices */
-  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
-  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
-  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
-  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
-  /* #define STM32L162xDX */   /*!< STM32L162VD-X Devices */
-  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-  
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V2.3.2
-  */
-#define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */
-#define __STM32L1xx_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
-                                         |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
-                                         |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
-                                         |(__STM32L1xx_CMSIS_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L100xB)
-  #include "stm32l100xb.h"
-#elif defined(STM32L100xBA)
-  #include "stm32l100xba.h"
-#elif defined(STM32L100xC)
-  #include "stm32l100xc.h"
-#elif defined(STM32L151xB)
-  #include "stm32l151xb.h"
-#elif defined(STM32L151xBA)
-  #include "stm32l151xba.h"
-#elif defined(STM32L151xC)
-  #include "stm32l151xc.h"
-#elif defined(STM32L151xCA)
-  #include "stm32l151xca.h"
-#elif defined(STM32L151xD)
-  #include "stm32l151xd.h"
-#elif defined(STM32L151xDX)
-  #include "stm32l151xdx.h"
-#elif defined(STM32L151xE)
-  #include "stm32l151xe.h"
-#elif defined(STM32L152xB)
-  #include "stm32l152xb.h"
-#elif defined(STM32L152xBA)
-  #include "stm32l152xba.h"
-#elif defined(STM32L152xC)
-  #include "stm32l152xc.h"
-#elif defined(STM32L152xCA)
-  #include "stm32l152xca.h"
-#elif defined(STM32L152xD)
-  #include "stm32l152xd.h"
-#elif defined(STM32L152xDX)
-  #include "stm32l152xdx.h"
-#elif defined(STM32L152xE)
-  #include "stm32l152xe.h"
-#elif defined(STM32L162xC)
-  #include "stm32l162xc.h"
-#elif defined(STM32L162xCA)
-  #include "stm32l162xca.h"
-#elif defined(STM32L162xD)
-  #include "stm32l162xd.h"
-#elif defined(STM32L162xDX)
-  #include "stm32l162xdx.h"
-#elif defined(STM32L162xE)
-  #include "stm32l162xe.h"
-#else
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  SUCCESS = 0,
-  ERROR = !SUCCESS
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-/* Use of CMSIS compiler intrinsics for register exclusive access */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT)                             \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
-  do {                                                                     \
-    uint32_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
-  } while(0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT)                            \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
-  do {                                                                     \
-    uint16_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
-  } while(0)
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L1xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
deleted file mode 100644
index 6fa05ff2793..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L1XX_H
-#define __SYSTEM_STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L1xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L1xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-/*
-*/
-extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
-extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L1XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html
deleted file mode 100644
index 97c793085b1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Release_Notes.html
+++ /dev/null
@@ -1,292 +0,0 @@
-<!DOCTYPE html>
-<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
-<head>
-  <meta charset="utf-8" />
-  <meta name="generator" content="pandoc" />
-  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
-  <title>Release Notes for STM32L1xx CMSIS</title>
-  <style type="text/css">
-      code{white-space: pre-wrap;}
-      span.smallcaps{font-variant: small-caps;}
-      span.underline{text-decoration: underline;}
-      div.column{display: inline-block; vertical-align: top; width: 50%;}
-  </style>
-  <link rel="stylesheet" href="_htmresc/mini-st.css" />
-  <!--[if lt IE 9]>
-    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
-  <![endif]-->
-</head>
-<body>
-<div class="row">
-<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
-<center>
-<h1 id="release-notes-for-stm32l1xx-cmsis"><small>Release Notes for</small> <mark>STM32L1xx CMSIS</mark></h1>
-<p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
-</center>
-</div>
-</div>
-<h1 id="purpose">Purpose</h1>
-<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
-<ul>
-<li>STM32L100xx devices</li>
-<li>STM32L151xx devices</li>
-<li>STM32L152xx devices</li>
-<li>STM32L162xx devices</li>
-</ul>
-<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
-<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
-<ul>
-<li>Templates/system_stm32l1xx.c contains the initialization code referred as SystemInit.</li>
-<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
-<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
-</ul>
-</div>
-<div class="col-sm-12 col-lg-8">
-<h1 id="update-history">Update History</h1>
-<div class="collapse">
-<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V2.3.2 / 21-May-2021</label>
-<div>
-<h2 id="main-changes">Main Changes</h2>
-<h3 id="maintenance-release">Maintenance release</h3>
-<h2 id="contents">Contents</h2>
-<ul>
-<li>Improve GCC startup files robustness.</li>
-<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
-<li>Add atomic register access macros.</li>
-<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
-<li>Remove bit definition related to PF and PG ports from unsupported devices (L1xxxB devices).</li>
-<li>Fix SYSCFG_EXTICR1_EXTI3_PF and SYSCFG_EXTICR1_EXTI3_PG defines values.</li>
-<li>Update the hal_flash.h file to correctly support the FLASH_SIZE of cat.2 devices.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label>
-<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
-<h2 id="contents-1">Contents</h2>
-<ul>
-<li>All header files
-<ul>
-<li>Remove NVIC CMSIS bits definitions to avoid duplication with CMSIS Core V5.x</li>
-<li>Remove GPIOx BRR register from GPIO structure and bit definitions when not supported</li>
-<li>Add ADC VREFINT/TEMPSENSOR addresses definitions in line with products datasheets:
-<ul>
-<li>VREFINT_CAL_ADDR_CMSIS</li>
-<li>TEMPSENSOR_CAL1_ADDR_CMSIS</li>
-<li>TEMPSENSOR_CAL2_ADDR_CMSIS</li>
-</ul></li>
-<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro</li>
-<li>Update IS_TIM_MASTER_INSTANCE with all supported instances.</li>
-</ul></li>
-<li>system_stm32l1xx.c file
-<ul>
-<li>Update SystemInit() API to don’t reset RCC registers to its reset values</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label>
-<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
-<h2 id="contents-2">Contents</h2>
-<ul>
-<li>stm32l0xx.h
-<ul>
-<li>Align ErrorStatus typedef to common error handling</li>
-</ul></li>
-<li>startup_stm32l1xxxxx.s
-<ul>
-<li>Update header of startup files to remove build error with ARM compiler.</li>
-</ul></li>
-<li>Updated Update CMSIS Devices compliancy with MISRA C 2012 rules
-<ul>
-<li>Rule-10.6: Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li>
-</ul></li>
-<li>Update CMSIS device description files according to latest version of HAL/LL drivers
-<ul>
-<li>Correct definitions for USB_COUNT3_TX_0 and USB_COUNT3_TX_1 registers</li>
-<li>Add IS_PCD_ALL_INSTANCE definition</li>
-<li>Add IS_TIM_SYNCHRO_INSTANCE macro definition</li>
-<li>Update macros definition for TIM instances</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.2.3 / 12-January-2018</label>
-<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="patch-release">Patch release</h3>
-<h2 id="contents-3">Contents</h2>
-<ul>
-<li>Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V2.2.2 / 25-August-2017</label>
-<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
-<h2 id="contents-4">Contents</h2>
-<ul>
-<li>Removed DATE and VERSION fields from header files.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V2.2.1 / 21-April-2017</label>
-<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance release</h3>
-<h2 id="contents-5">Contents</h2>
-<ul>
-<li>Update CMSIS Devices compliancy with MISRA C 2004 rules:
-<ul>
-<li>MISRA C 2004 rule 10.6 (‘U’ suffix applied to all constants of ‘unsigned’ type)</li>
-<li>Update system_stm32l1xx.h/.c files.</li>
-</ul></li>
-<li>Align Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x.</li>
-<li>Rename RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.</li>
-<li>Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V2.2.0 / 01-July-2016</label>
-<div>
-<h2 id="main-changes-6">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
-<ul>
-<li>Add macros _Pos and _Msk for each constants.
-<ul>
-<li>For instance:
-<ul>
-<li>#define ADC_LTR_LT ((uint32_t)0x00000FFFU)</li>
-</ul></li>
-<li>Is now provided as:
-<ul>
-<li>#define ADC_LTR_LT_Pos (0U)</li>
-<li>#define ADC_LTR_LT_Msk (0xFFFU &lt;&lt; ADC_LTR_LT_Pos)</li>
-<li>#define ADC_LTR_LT ADC_LTR_LT_Msk</li>
-</ul></li>
-</ul></li>
-<li>IS_I2S_ALL_INSTANCE is now SPI2 and SPI3 instead of SPI1 and SPI2.</li>
-<li>Update the TIM_ARR_ARR and TIM_CNT_CNT as they support the 32 bit counter feature.</li>
-<li>Add macro IS_TIM_ETR_INSTANCE.</li>
-<li>Add RI_ASCR2_GR6_x with x = 1,2,3,4 if applicable.</li>
-<li>Add macro IS_SMBUS_ALL_INSTANCE.</li>
-<li>Set default value for SystemCoreClock to 2097000 instead of 32000000.</li>
-<li>Correct the presence of TIM9 for some devices inside various TIMER macros.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V2.1.3 / 04-March-2016</label>
-<div>
-<h2 id="main-changes-7">Main Changes</h2>
-<h3 id="maintenance-release-6">Maintenance release</h3>
-<h2 id="contents-7">Contents</h2>
-<ul>
-<li>Add HardFault_IRQn.</li>
-<li>Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.</li>
-<li>Align bits naming on all stm32 families (ex: WWDG_CFR_WDGTB0 -&gt; WWDG_CFR_WDGTB_0).</li>
-<li>Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx</li>
-<li>Align Bits naming on all stm32 families (ex: EXTI_IMR_MR0 –&gt; EXTI_IMR_IM0)</li>
-<li>Update .icf file to correct empty linker ROM Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and stm32l162xdx.</li>
-<li>Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to be aligned with Reference Manual.</li>
-<li>Update CMSIS drivers to apply MISRA C 2004 rule 10.6. (Use U postfix)</li>
-<li>Add defines FLASHSIZE_BASE and UID_BASE</li>
-<li>ADC common instance standardization (new define ADC1_COMMON)</li>
-<li>Remove bit GPIO_BRR_BR_x from Cat1 to Cat2 devices</li>
-<li>Literals “ADC_SMPR1_SMP27, ADC_SMPR1_SMP28, ADC_SMPR1_SMP29” are available on Cat4, Cat5 only.</li>
-<li>Add DMA_CNDTR_NDT, DMA_CPAR_PA and DMA_CMAR_MA definitions present on other stm32 families.</li>
-<li>Add defines to trig feature inside source code based on CMSIS content:
-<ul>
-<li>RTC_TAMPER1_SUPPORT</li>
-<li>RTC_TAMPER2_SUPPORT</li>
-<li>RTC_TAMPER3_SUPPORT</li>
-<li>RTC_BACKUP_SUPPORT</li>
-<li>RTC_WAKEUP_SUPPORT</li>
-<li>RTC_SMOOTHCALIB_SUPPORT</li>
-<li>RTC_SUBSECOND_SUPPORT.</li>
-<li>PWR_PVD_SUPPORT</li>
-</ul></li>
-<li>Set CMSIS variables PLLMulTable, AHBPrescTable and APBPrescTable as external in system_stm32l1xx.h.</li>
-<li>Bit 23 of all EXTI registers (IMR, EMR, …) is not supported on Cat 1 &amp; 2.</li>
-<li>Correct a wrong values for RI_ASCR1_CH_27 to RI_ASCR1_CH_30</li>
-<li>Add defines for LCD capacitance</li>
-<li>Suppress SPI1 from I2S_ALL_INSTANCE</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.2 / 09-October-2015</label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="maintenance-release-7">Maintenance release</h3>
-<h2 id="contents-8">Contents</h2>
-<ul>
-<li>Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.</li>
-<li>IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.</li>
-<li>Added TIM10 and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).</li>
-<li>Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other bits.</li>
-<li>Renaming USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this register.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.1.1 / 31-March-2015</label>
-<div>
-<h2 id="main-changes-9">Main Changes</h2>
-<h3 id="maintenance-release-8">Maintenance release</h3>
-<h2 id="contents-9">Contents</h2>
-<ul>
-<li>Ensure compliancy w/ C++</li>
-<li>Minor update on Timer assert.</li>
-<li>Adding IS_AES_ALL_INSTANCE macro for product with AES.</li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V2.1.0 / 06-February-2015</label>
-<div>
-<h2 id="main-changes-10">Main Changes</h2>
-<h3 id="maintenance-release-9">Maintenance release</h3>
-<h2 id="contents-10">Contents</h2>
-<ul>
-<li>Add CMSIS files for new STM32L1 e<strong>X</strong>tended Devices : <strong>STM32L151xDX, STM32L152xDX and STM32L162xDX</strong></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V2.0.0 / 05-September-2014</label>
-<div>
-<h2 id="main-changes-11">Main Changes</h2>
-<h3 id="maintenance-release-10">Maintenance release</h3>
-<h2 id="contents-11">Contents</h2>
-<ul>
-<li>Update based on STM32Cube specification</li>
-</ul>
-<h2 id="other-compatibilities">Other compatibilities</h2>
-<ul>
-<li>This version has to be used only with <strong>STM32CubeL1</strong> based development</li>
-</ul>
-</div>
-</div>
-</div>
-</div>
-<footer class="sticky">
-For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
-</footer>
-</body>
-</html>
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xb.s
deleted file mode 100644
index 2a262989f4a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xb.s
+++ /dev/null
@@ -1,314 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XB Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xba.s
deleted file mode 100644
index 7edd27ad677..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xba.s
+++ /dev/null
@@ -1,314 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XBA Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xc.s
deleted file mode 100644
index d0918bf558b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l100xc.s
+++ /dev/null
@@ -1,340 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XC Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xb.s
deleted file mode 100644
index e0e73ec015b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xb.s
+++ /dev/null
@@ -1,312 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XB Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xba.s
deleted file mode 100644
index ebb9a7f9209..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xba.s
+++ /dev/null
@@ -1,312 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XBA Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xc.s
deleted file mode 100644
index cef9f3b1380..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xc.s
+++ /dev/null
@@ -1,340 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xca.s
deleted file mode 100644
index 8e4ad2ec364..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xca.s
+++ /dev/null
@@ -1,340 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xd.s
deleted file mode 100644
index 74dd3ddfc1c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xd.s
+++ /dev/null
@@ -1,346 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XD Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     SDIO_IRQHandler           ; SDIO
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xdx.s
deleted file mode 100644
index 694a61c32dc..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xdx.s
+++ /dev/null
@@ -1,344 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XD-X Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xe.s
deleted file mode 100644
index 6f0b75892d6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l151xe.s
+++ /dev/null
@@ -1,344 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XE Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     0                         ; Reserved
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xb.s
deleted file mode 100644
index 301dfdcb7f2..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xb.s
+++ /dev/null
@@ -1,314 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XB Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xba.s
deleted file mode 100644
index a74989e701e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xba.s
+++ /dev/null
@@ -1,314 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XBA Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xc.s
deleted file mode 100644
index 7e83efca609..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xc.s
+++ /dev/null
@@ -1,341 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XC Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xca.s
deleted file mode 100644
index 9c7c7362087..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xca.s
+++ /dev/null
@@ -1,342 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XCA Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xd.s
deleted file mode 100644
index 73c7fd75c54..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xd.s
+++ /dev/null
@@ -1,348 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XD Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     SDIO_IRQHandler           ; SDIO
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xdx.s
deleted file mode 100644
index b3488fbff40..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xdx.s
+++ /dev/null
@@ -1,346 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XD-X Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xe.s
deleted file mode 100644
index e1ac38a5718..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l152xe.s
+++ /dev/null
@@ -1,346 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XE Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xc.s
deleted file mode 100644
index 0b5ca41dab5..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xc.s
+++ /dev/null
@@ -1,344 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XC Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]              
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xca.s
deleted file mode 100644
index 805f11fea29..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xca.s
+++ /dev/null
@@ -1,344 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XCA Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xd.s
deleted file mode 100644
index 5ecfd72846a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xd.s
+++ /dev/null
@@ -1,350 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XD Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     SDIO_IRQHandler           ; SDIO
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  SDIO_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-SDIO_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xdx.s
deleted file mode 100644
index 8223a742cc1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xdx.s
+++ /dev/null
@@ -1,348 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XD-X Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xe.s
deleted file mode 100644
index 7409b130805..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l162xe.s
+++ /dev/null
@@ -1,348 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XE Devices vector for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;* <<< Use Configuration Wizard in Context Menu >>>
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0              
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB           
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xb.s
deleted file mode 100644
index f7d4657ebbd..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xb.s
+++ /dev/null
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l100xb.s
-  * @author    MCD Application Team
-  * @brief     STM32L100XB Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L100XB devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xba.s
deleted file mode 100644
index 656fc9ad2ba..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xba.s
+++ /dev/null
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l100xba.s
-  * @author    MCD Application Team
-  * @brief     STM32L100XBA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L100XBA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xc.s
deleted file mode 100644
index cbc8b7f420e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l100xc.s
+++ /dev/null
@@ -1,403 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l100xc.s
-  * @author    MCD Application Team
-  * @brief     STM32L100XC Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L100XC devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xb.s
deleted file mode 100644
index 497416f280f..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xb.s
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xb.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XB Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XB devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xba.s
deleted file mode 100644
index 758a097d1cf..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xba.s
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xba.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XBA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XBA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xc.s
deleted file mode 100644
index 6cce5a03245..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xc.s
+++ /dev/null
@@ -1,403 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xc.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XC Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XC devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xca.s
deleted file mode 100644
index d86e7d753b0..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xca.s
+++ /dev/null
@@ -1,403 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xca.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XCA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XCA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xd.s
deleted file mode 100644
index 57a5b8e8650..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xd.s
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xd.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XD Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XD devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xdx.s
deleted file mode 100644
index 31516f3e0b5..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xdx.s
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xdx.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XD-X Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XD-X devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xe.s
deleted file mode 100644
index 39e9df455b9..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l151xe.s
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xe.s
-  * @author    MCD Application Team
-  * @brief     STM32L151XE Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XE devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xb.s
deleted file mode 100644
index b57729ba091..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xb.s
+++ /dev/null
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xb.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XB Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XB devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xba.s
deleted file mode 100644
index dd2f9ddcd95..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xba.s
+++ /dev/null
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xba.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XBA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XBA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xc.s
deleted file mode 100644
index 691c9c409b2..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xc.s
+++ /dev/null
@@ -1,406 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xc.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XC Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XC devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xca.s
deleted file mode 100644
index 41dad284eec..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xca.s
+++ /dev/null
@@ -1,406 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xca.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XCA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XCA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xd.s
deleted file mode 100644
index 2404fbb6c00..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xd.s
+++ /dev/null
@@ -1,415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xd.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XD Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XD devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xdx.s
deleted file mode 100644
index c5540c148ad..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xdx.s
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xdx.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XD-X Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XD-X devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xe.s
deleted file mode 100644
index 24e0ec2f0ef..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l152xe.s
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xe.s
-  * @author    MCD Application Team
-  * @brief     STM32L152XE Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XE devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xc.s
deleted file mode 100644
index 9f9bd6e9d93..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xc.s
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l162xc.s
-  * @author    MCD Application Team
-  * @brief     STM32L162XC Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word AES_IRQHandler
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L162XC devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak AES_IRQHandler
-  .thumb_set AES_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xca.s
deleted file mode 100644
index 867a9a4708a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xca.s
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l162xca.s
-  * @author    MCD Application Team
-  * @brief     STM32L162XCA Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word AES_IRQHandler
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L162XCA devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak AES_IRQHandler
-  .thumb_set AES_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xd.s
deleted file mode 100644
index 7fc25d3707d..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xd.s
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l162xd.s
-  * @author    MCD Application Team
-  * @brief     STM32L162XD Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word SDIO_IRQHandler
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word AES_IRQHandler
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L162XD devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak AES_IRQHandler
-  .thumb_set AES_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xdx.s
deleted file mode 100644
index ab0b2f387d3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xdx.s
+++ /dev/null
@@ -1,415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l162xdx.s
-  * @author    MCD Application Team
-  * @brief     STM32L162XD-X Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word AES_IRQHandler
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L162XD-X devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak AES_IRQHandler
-  .thumb_set AES_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xe.s
deleted file mode 100644
index 637b27ed69a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc/startup_stm32l162xe.s
+++ /dev/null
@@ -1,415 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l162xe.s
-  * @author    MCD Application Team
-  * @brief     STM32L162XE Devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word AES_IRQHandler
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L162XE devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak AES_IRQHandler
-  .thumb_set AES_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf
deleted file mode 100644
index 60a65a36610..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x200027FF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf
deleted file mode 100644
index 31816211d0f..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xb_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20000000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf
deleted file mode 100644
index ef5c3783033..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf
deleted file mode 100644
index 10206dc0169..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xba_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf
deleted file mode 100644
index 172bc663bdc..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf
deleted file mode 100644
index 10206dc0169..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l100xc_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf
deleted file mode 100644
index ef5c3783033..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf
deleted file mode 100644
index 10206dc0169..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xb_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf
deleted file mode 100644
index bc51d1f07fe..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xba_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xc_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xca_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf
deleted file mode 100644
index 5d0c7986395..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xd_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf
deleted file mode 100644
index 60ae633020b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_ROM1_start__ = 0x08040000 ;
-define symbol __ICFEDIT_region_ROM1_end__   = 0x0806FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__] |
-    mem:[from __ICFEDIT_region_ROM1_start__   to __ICFEDIT_region_ROM1_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xdx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf
deleted file mode 100644
index c9e97b1955a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf
deleted file mode 100644
index 3ee399dc170..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l151xe_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf
deleted file mode 100644
index ef5c3783033..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf
deleted file mode 100644
index 10206dc0169..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xb_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf
deleted file mode 100644
index bc51d1f07fe..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xba_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xc_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xca_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf
deleted file mode 100644
index 3aeec61d41c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xd_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf
deleted file mode 100644
index 60ae633020b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_ROM1_start__ = 0x08040000 ;
-define symbol __ICFEDIT_region_ROM1_end__   = 0x0806FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__] |
-    mem:[from __ICFEDIT_region_ROM1_start__   to __ICFEDIT_region_ROM1_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xdx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf
deleted file mode 100644
index c9e97b1955a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf
deleted file mode 100644
index 3ee399dc170..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l152xe_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xc_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf
deleted file mode 100644
index 8bc6a84fb50..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf
deleted file mode 100644
index 2374f5c85a3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xca_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf
deleted file mode 100644
index 5d0c7986395..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xd_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf
deleted file mode 100644
index 60ae633020b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_flash.icf
+++ /dev/null
@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0802FFFF;
-define symbol __ICFEDIT_region_ROM1_start__ = 0x08040000 ;
-define symbol __ICFEDIT_region_ROM1_end__   = 0x0806FFFF;
-define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__    = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__] |
-    mem:[from __ICFEDIT_region_ROM1_start__   to __ICFEDIT_region_ROM1_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf
deleted file mode 100644
index d332a4b46e6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xdx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf
deleted file mode 100644
index c9e97b1955a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf
deleted file mode 100644
index 3ee399dc170..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/linker/stm32l162xe_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
-define symbol __ICFEDIT_region_ROM_end__   = 0x200013FF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20013FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xb.s
deleted file mode 100644
index f4e7c0b4935..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xb.s
+++ /dev/null
@@ -1,460 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XB Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xba.s
deleted file mode 100644
index 51ad5ab676a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xba.s
+++ /dev/null
@@ -1,460 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XBA Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xc.s
deleted file mode 100644
index 28d70e79b1c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l100xc.s
+++ /dev/null
@@ -1,513 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l100xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L100XC Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xb.s
deleted file mode 100644
index 8e8604b77e4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xb.s
+++ /dev/null
@@ -1,454 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XB Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xba.s
deleted file mode 100644
index 87947a54de7..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xba.s
+++ /dev/null
@@ -1,454 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XBA Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xc.s
deleted file mode 100644
index fb0139dc139..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xc.s
+++ /dev/null
@@ -1,513 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XC Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xca.s
deleted file mode 100644
index 3506dac510f..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xca.s
+++ /dev/null
@@ -1,512 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XC Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xd.s
deleted file mode 100644
index 813a99b9050..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xd.s
+++ /dev/null
@@ -1,529 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XD Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     SDIO_IRQHandler           ; SDIO
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-                       
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xdx.s
deleted file mode 100644
index 52723f89102..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xdx.s
+++ /dev/null
@@ -1,524 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XD-X Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xe.s
deleted file mode 100644
index a5f4fff5b63..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l151xe.s
+++ /dev/null
@@ -1,524 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l151xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L151XE Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     0                         ; Reserved
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xb.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xb.s
deleted file mode 100644
index 84dbd23d980..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xb.s
+++ /dev/null
@@ -1,460 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xb.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XB Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xba.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xba.s
deleted file mode 100644
index 73224c2c320..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xba.s
+++ /dev/null
@@ -1,460 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xba.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XBA Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler                
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xc.s
deleted file mode 100644
index f2aa3f81b90..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xc.s
+++ /dev/null
@@ -1,519 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xca.s
deleted file mode 100644
index 3a47617d91e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xca.s
+++ /dev/null
@@ -1,519 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XCA Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xd.s
deleted file mode 100644
index 904ea76a896..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xd.s
+++ /dev/null
@@ -1,535 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XD Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     SDIO_IRQHandler           ; SDIO
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-                       
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xdx.s
deleted file mode 100644
index f70889c76c3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xdx.s
+++ /dev/null
@@ -1,529 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XD-X Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xe.s
deleted file mode 100644
index 382e8933eb8..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l152xe.s
+++ /dev/null
@@ -1,529 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L152XE Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xc.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xc.s
deleted file mode 100644
index c84379e2fc8..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xc.s
+++ /dev/null
@@ -1,525 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xc.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XC Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     AES_IRQHandler            ; AES
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-                       
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AES_IRQHandler
-        B AES_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xca.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xca.s
deleted file mode 100644
index 55bb30e6969..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xca.s
+++ /dev/null
@@ -1,524 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xca.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XCA Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     AES_IRQHandler            ; AES
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AES_IRQHandler
-        B AES_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xd.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xd.s
deleted file mode 100644
index 7c0508b180a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xd.s
+++ /dev/null
@@ -1,541 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xd.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XD Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     SDIO_IRQHandler           ; SDIO
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     AES_IRQHandler            ; AES
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler 
-                       
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
-        B SDIO_IRQHandler 
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler                                
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AES_IRQHandler
-        B AES_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xdx.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xdx.s
deleted file mode 100644
index c6f212e5f6c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xdx.s
+++ /dev/null
@@ -1,535 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xdx.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XD-X Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     AES_IRQHandler            ; AES
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AES_IRQHandler
-        B AES_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xe.s b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xe.s
deleted file mode 100644
index bff971aa097..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l162xe.s
+++ /dev/null
@@ -1,535 +0,0 @@
-;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name          : startup_stm32l162xe.s
-;* Author             : MCD Application Team
-;* Description        : STM32L162XE Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics. All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the 
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     AES_IRQHandler            ; AES
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AES_IRQHandler
-        B AES_IRQHandler
-        
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c b/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
deleted file mode 100644
index 42f02a1a230..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *             
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *                        
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.   
-  *      
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/* Note: Following vector table addresses must be defined in line with linker
-         configuration. */
-/*!< Uncomment the following line if you need to relocate the vector table
-     anywhere in Flash or Sram, else the vector table is kept at the automatic
-     remap of boot address selected */
-/* #define USER_VECT_TAB_ADDRESS */
-
-#if defined(USER_VECT_TAB_ADDRESS)
-/*!< Uncomment the following line if you need to relocate your vector Table
-     in Sram else user remap will be done in Flash. */
-/* #define VECT_TAB_SRAM */
-#if defined(VECT_TAB_SRAM)
-#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#else
-#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#endif /* VECT_TAB_SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock        = 2097000U;
-const uint8_t PLLMulTable[9]    = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-const uint8_t APBPrescTable[8]  = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-  /* Configure the Vector Table location -------------------------------------*/
-#if defined(USER_VECT_TAB_ADDRESS)
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#endif /* USER_VECT_TAB_ADDRESS */
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Flash 1 wait state */
-  FLASH->ACR |= FLASH_ACR_LATENCY;
-  
-  /* Power enable */
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-
-  /* Select the Voltage Range 1 (1.8 V) */
-  PWR->CR = PWR_CR_VOS_0;
-  
-  /* Wait Until the Voltage Regulator is ready */
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  {
-  }
-  
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  (void)(tmpreg);
-  
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript b/bsp/stm32/libraries/STM32L1xx_HAL/SConscript
deleted file mode 100644
index 7c2b1d785d1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript
+++ /dev/null
@@ -1,79 +0,0 @@
-import rtconfig
-Import('RTT_ROOT')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32L1xx.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_dma.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_cortex.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_crc.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_pwr.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_rcc.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_rcc_ex.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal.c
-STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c
-STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_sram.c
-STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_gpio.c
-""")
-
-
-
-if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_uart.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_usart.c']
-
-if GetDepend(['RT_USING_I2C']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_i2c.c']
-
-if GetDepend(['RT_USING_SPI']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_spi.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_ll_spi.c']
-
-if GetDepend(['RT_USING_USB']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_pcd.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_pcd_ex.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_ll_usb.c']
-
-
-if GetDepend(['RT_USING_CAN']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_can.c']
-
-if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_tim.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_tim_ex.c']
-
-if GetDepend(['RT_USING_ADC']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_adc.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_adc_ex.c']
-
-if GetDepend(['RT_USING_RTC']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_rtc.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_rtc_ex.c']
-
-if GetDepend(['RT_USING_WDT']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_iwdg.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_wwdg.c']
-
-if GetDepend(['RT_USING_SDIO']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_ll_sdmmc.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_sd.c']
-
-if GetDepend(['RT_USING_AUDIO']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_i2s.c']
-
-if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_flash.c']
-    src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_flash_ex.c']
-
-path = [cwd + '/CMSIS/Device/ST/STM32L1xx/Include',
-    cwd + '/STM32L1xx_HAL_Driver/Inc']
-
-CPPDEFINES = ['USE_HAL_DRIVER']
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index b71bb246125..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3793 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
-/* to the second dedicated IO (only for COMP2).                               */
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Aliases CRC API aliases
-  * @{
-  */
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   0x00000000U
-#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7)
-#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
-    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
-
-#if defined(STM32L1)
-#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
-  */
-#define HRTIM_EVENTSRC_1              (0x00000000U)
-#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
-  */
-#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
-#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE               I2S_IT_TXP
-#define I2S_IT_RXNE              I2S_IT_RXP
-
-#define I2S_FLAG_TXE             I2S_FLAG_TXP
-#define I2S_FLAG_RXNE            I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD                  ATA_CARD_HEAD
-#define CF_STATUS_CMD                 ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE                    SPI_FLAG_TXP
-#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
-
-#define SPI_IT_TXE                      SPI_IT_TXP
-#define SPI_IT_RXNE                     SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define __DIV_LPUART                    UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              0x00000100U
-#define ETH_MMCRIR             0x00000104U
-#define ETH_MMCTIR             0x00000108U
-#define ETH_MMCRIMR            0x0000010CU
-#define ETH_MMCTIMR            0x00000110U
-#define ETH_MMCTGFSCCR         0x0000014CU
-#define ETH_MMCTGFMSCCR        0x00000150U
-#define ETH_MMCTGFCR           0x00000168U
-#define ETH_MMCRFCECR          0x00000194U
-#define ETH_MMCRFAECR          0x00000198U
-#define ETH_MMCRGUFCR          0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888
-#define CM_RGB565               DMA2D_INPUT_RGB565
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8
-#define CM_AL44                 DMA2D_INPUT_AL44
-#define CM_AL88                 DMA2D_INPUT_AL88
-#define CM_L4                   DMA2D_INPUT_L4
-#define CM_A8                   DMA2D_INPUT_A8
-#define CM_A4                   DMA2D_INPUT_A4
-/**
-  * @}
-  */
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
-  * @{
-  */
-#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
-                                                                        for compatibility with legacy code */
-/**
-  * @}
-  */
-
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
-  * @{
-  */
-#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
-/**
-  *
-  * @}
-  */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
-                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
-                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
-                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
-  * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
-#define CR_PMODE_BB                                   CR_VOS_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod           HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                           ((WAVE) == DAC_WAVE_NOISE)|| \
-                           ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
-                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS
-#define RCC_IT_CSSHSE               RCC_IT_CSS
-
-#define RCC_PLLMUL_3                RCC_PLL_MUL3
-#define RCC_PLLMUL_4                RCC_PLL_MUL4
-#define RCC_PLLMUL_6                RCC_PLL_MUL6
-#define RCC_PLLMUL_8                RCC_PLL_MUL8
-#define RCC_PLLMUL_12               RCC_PLL_MUL12
-#define RCC_PLLMUL_16               RCC_PLL_MUL16
-#define RCC_PLLMUL_24               RCC_PLL_MUL24
-#define RCC_PLLMUL_32               RCC_PLL_MUL32
-#define RCC_PLLMUL_48               RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2                RCC_PLL_DIV2
-#define RCC_PLLDIV_3                RCC_PLL_DIV3
-#define RCC_PLLDIV_4                RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
-#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) 
-#else
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
-#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
-#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
-
-#if defined(STM32F4) || defined(STM32F2)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
-#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
-#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
-#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16               0x00000000U
-#define USART_OVERSAMPLING_8                USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
-                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32_assert_template.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32_assert_template.h
deleted file mode 100644
index 8777d3f51a7..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32_assert_template.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_assert.h
-  * @author  MCD Application Team
-  * @brief   STM32 assert template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32_assert.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h
deleted file mode 100644
index e3d4967d057..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h
+++ /dev/null
@@ -1,996 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal.h
-  * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the HAL
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_H
-#define __STM32L1xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_conf.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
-  * @{
-  */
-#define  HAL_TICK_FREQ_10HZ         100U
-#define  HAL_TICK_FREQ_100HZ        10U
-#define  HAL_TICK_FREQ_1KHZ         1U
-#define  HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ
-
-#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ)  || \
-                               ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \
-                               ((__FREQ__) == HAL_TICK_FREQ_1KHZ))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
-  * @{
-  */
-
-/** @defgroup SYSCFG_BootMode Boot Mode
-  * @{
-  */
-
-#define SYSCFG_BOOT_MAINFLASH          (0x00000000U)
-#define SYSCFG_BOOT_SYSTEMFLASH        ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
-#if defined(FSMC_R_BASE)
-#define SYSCFG_BOOT_FSMC               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
-#endif /* FSMC_R_BASE  */
-#define SYSCFG_BOOT_SRAM               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_Constants RI: Routing Interface
-  * @{
-  */
-
-/** @defgroup RI_InputCapture Input Capture
-  * @{
-  */
-
-#define RI_INPUTCAPTURE_IC1  RI_ICR_IC1    /*!< Input Capture 1 */
-#define RI_INPUTCAPTURE_IC2  RI_ICR_IC2    /*!< Input Capture 2 */
-#define RI_INPUTCAPTURE_IC3  RI_ICR_IC3    /*!< Input Capture 3 */
-#define RI_INPUTCAPTURE_IC4  RI_ICR_IC4    /*!< Input Capture 4 */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Select TIM Select
-  * @{
-  */
-
-#define TIM_SELECT_NONE  (0x00000000U)    /*!< None selected */
-#define TIM_SELECT_TIM2  ((uint32_t)RI_ICR_TIM_0)  /*!< Timer 2 selected */
-#define TIM_SELECT_TIM3  ((uint32_t)RI_ICR_TIM_1)  /*!< Timer 3 selected */
-#define TIM_SELECT_TIM4  ((uint32_t)RI_ICR_TIM)    /*!< Timer 4 selected */
-
-#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
-                        ((__TIM__) == TIM_SELECT_TIM2) || \
-                        ((__TIM__) == TIM_SELECT_TIM3) || \
-                        ((__TIM__) == TIM_SELECT_TIM4))
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_InputCaptureRouting Input Capture Routing
-  * @{
-  */
-                                                          /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */
-#define RI_INPUTCAPTUREROUTING_0   (0x00000000U) /* PA0       PA1      PA2       PA3      */
-#define RI_INPUTCAPTUREROUTING_1   (0x00000001U) /* PA4       PA5      PA6       PA7      */
-#define RI_INPUTCAPTUREROUTING_2   (0x00000002U) /* PA8       PA9      PA10      PA11     */
-#define RI_INPUTCAPTUREROUTING_3   (0x00000003U) /* PA12      PA13     PA14      PA15     */
-#define RI_INPUTCAPTUREROUTING_4   (0x00000004U) /* PC0       PC1      PC2       PC3      */
-#define RI_INPUTCAPTUREROUTING_5   (0x00000005U) /* PC4       PC5      PC6       PC7      */
-#define RI_INPUTCAPTUREROUTING_6   (0x00000006U) /* PC8       PC9      PC10      PC11     */
-#define RI_INPUTCAPTUREROUTING_7   (0x00000007U) /* PC12      PC13     PC14      PC15     */
-#define RI_INPUTCAPTUREROUTING_8   (0x00000008U) /* PD0       PD1      PD2       PD3      */
-#define RI_INPUTCAPTUREROUTING_9   (0x00000009U) /* PD4       PD5      PD6       PD7      */
-#define RI_INPUTCAPTUREROUTING_10  (0x0000000AU) /* PD8       PD9      PD10      PD11     */
-#define RI_INPUTCAPTUREROUTING_11  (0x0000000BU) /* PD12      PD13     PD14      PD15     */
-#define RI_INPUTCAPTUREROUTING_12  (0x0000000CU) /* PE0       PE1      PE2       PE3      */
-#define RI_INPUTCAPTUREROUTING_13  (0x0000000DU) /* PE4       PE5      PE6       PE7      */
-#define RI_INPUTCAPTUREROUTING_14  (0x0000000EU) /* PE8       PE9      PE10      PE11     */
-#define RI_INPUTCAPTUREROUTING_15  (0x0000000FU) /* PE12      PE13     PE14      PE15     */
-
-#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_IOSwitch IO Switch
-  * @{
-  */
-#define RI_ASCR1_REGISTER       (0x80000000U)
-/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
-#define RI_IOSWITCH_CH0         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
-#define RI_IOSWITCH_CH1         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
-#define RI_IOSWITCH_CH2         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
-#define RI_IOSWITCH_CH3         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
-#define RI_IOSWITCH_CH4         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
-#define RI_IOSWITCH_CH5         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
-#define RI_IOSWITCH_CH6         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
-#define RI_IOSWITCH_CH7         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
-#define RI_IOSWITCH_CH8         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
-#define RI_IOSWITCH_CH9         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
-#define RI_IOSWITCH_CH10        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
-#define RI_IOSWITCH_CH11        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
-#define RI_IOSWITCH_CH12        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
-#define RI_IOSWITCH_CH13        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
-#define RI_IOSWITCH_CH14        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
-#define RI_IOSWITCH_CH15        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
-#define RI_IOSWITCH_CH18        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
-#define RI_IOSWITCH_CH19        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
-#define RI_IOSWITCH_CH20        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
-#define RI_IOSWITCH_CH21        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
-#define RI_IOSWITCH_CH22        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
-#define RI_IOSWITCH_CH23        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
-#define RI_IOSWITCH_CH24        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
-#define RI_IOSWITCH_CH25        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
-#define RI_IOSWITCH_VCOMP       ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH27        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
-#define RI_IOSWITCH_CH28        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
-#define RI_IOSWITCH_CH29        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
-#define RI_IOSWITCH_CH30        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
-#define RI_IOSWITCH_CH31        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
-#endif /* RI_ASCR2_CH1b */
-
-/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
-#define RI_IOSWITCH_GR10_1      ((uint32_t)RI_ASCR2_GR10_1)
-#define RI_IOSWITCH_GR10_2      ((uint32_t)RI_ASCR2_GR10_2)
-#define RI_IOSWITCH_GR10_3      ((uint32_t)RI_ASCR2_GR10_3)
-#define RI_IOSWITCH_GR10_4      ((uint32_t)RI_ASCR2_GR10_4)
-#define RI_IOSWITCH_GR6_1       ((uint32_t)RI_ASCR2_GR6_1)
-#define RI_IOSWITCH_GR6_2       ((uint32_t)RI_ASCR2_GR6_2)
-#define RI_IOSWITCH_GR5_1       ((uint32_t)RI_ASCR2_GR5_1)
-#define RI_IOSWITCH_GR5_2       ((uint32_t)RI_ASCR2_GR5_2)
-#define RI_IOSWITCH_GR5_3       ((uint32_t)RI_ASCR2_GR5_3)
-#define RI_IOSWITCH_GR4_1       ((uint32_t)RI_ASCR2_GR4_1)
-#define RI_IOSWITCH_GR4_2       ((uint32_t)RI_ASCR2_GR4_2)
-#define RI_IOSWITCH_GR4_3       ((uint32_t)RI_ASCR2_GR4_3)
-#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH0b        ((uint32_t)RI_ASCR2_CH0b)
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH1b        ((uint32_t)RI_ASCR2_CH1b)
-#define RI_IOSWITCH_CH2b        ((uint32_t)RI_ASCR2_CH2b)
-#define RI_IOSWITCH_CH3b        ((uint32_t)RI_ASCR2_CH3b)
-#define RI_IOSWITCH_CH6b        ((uint32_t)RI_ASCR2_CH6b)
-#define RI_IOSWITCH_CH7b        ((uint32_t)RI_ASCR2_CH7b)
-#define RI_IOSWITCH_CH8b        ((uint32_t)RI_ASCR2_CH8b)
-#define RI_IOSWITCH_CH9b        ((uint32_t)RI_ASCR2_CH9b)
-#define RI_IOSWITCH_CH10b       ((uint32_t)RI_ASCR2_CH10b)
-#define RI_IOSWITCH_CH11b       ((uint32_t)RI_ASCR2_CH11b)
-#define RI_IOSWITCH_CH12b       ((uint32_t)RI_ASCR2_CH12b)
-#endif /* RI_ASCR2_CH1b */
-#define RI_IOSWITCH_GR6_3       ((uint32_t)RI_ASCR2_GR6_3)
-#define RI_IOSWITCH_GR6_4       ((uint32_t)RI_ASCR2_GR6_4)
-#endif /* RI_ASCR2_CH0b */
-
-
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_CH27)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH28)    || ((__IOSWITCH__) == RI_IOSWITCH_CH29)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH30)    || ((__IOSWITCH__) == RI_IOSWITCH_CH31)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_1)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_3)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH0b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH1b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH3b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH7b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH9b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10b)   || ((__IOSWITCH__) == RI_IOSWITCH_CH11b)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
-
-#else /* !RI_ASCR2_CH1b */
-
-#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)   || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
-
-#else /* !RI_ASCR2_CH0b */  /* STM32L1 devices category Cat.1 and Cat.2 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
-
-#endif /* RI_ASCR2_CH0b */
-#endif /* RI_ASCR2_CH1b */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_Pin PIN define
-  * @{
-  */
-#define RI_PIN_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
-#define RI_PIN_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
-#define RI_PIN_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
-#define RI_PIN_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
-#define RI_PIN_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
-#define RI_PIN_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
-#define RI_PIN_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
-#define RI_PIN_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
-#define RI_PIN_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
-#define RI_PIN_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
-#define RI_PIN_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
-#define RI_PIN_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
-#define RI_PIN_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
-#define RI_PIN_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
-#define RI_PIN_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
-#define RI_PIN_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
-#define RI_PIN_ALL               ((uint16_t)0xFFFF)  /*!< All pins selected */
-
-#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
-  * @{
-  */
-
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
-  * @brief   Freeze/Unfreeze Peripherals in Debug mode
-  * @{
-  */
-
-/**
-  * @brief  TIM2 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#endif
-
-/**
-  * @brief  TIM3 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#endif
-
-/**
-  * @brief  TIM4 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#endif
-
-/**
-  * @brief  TIM5 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#endif
-
-/**
-  * @brief  TIM6 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#endif
-
-/**
-  * @brief  TIM7 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#endif
-
-/**
-  * @brief  RTC Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC()             SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC()           CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#endif
-
-/**
-  * @brief  WWDG Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#endif
-
-/**
-  * @brief  IWDG Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#endif
-
-/**
-  * @brief  I2C1 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#endif
-
-/**
-  * @brief  I2C2 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#endif
-
-/**
-  * @brief  TIM9 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#endif
-
-/**
-  * @brief  TIM10 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM10()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM10()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#endif
-
-/**
-  * @brief  TIM11 Peripherals Debug mode
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM11()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM11()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#endif
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
-  * @{
-  */
-
-/** @defgroup SYSCFG_VrefInt VREFINT configuration
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the output of internal reference voltage
-  *         (VrefInt) on I/O pin.
-  * @note   The VrefInt output can be routed to any I/O in group 3:
-  *          - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
-  *          - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
-  *          - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
-  *            CH1b (PF11) or CH2b (PF12).
-  *         Note: Comparator peripheral clock must be preliminarily enabled,
-  *               either in COMP user function "HAL_COMP_MspInit()" (should be
-  *               done if comparators are used) or by direct clock enable:
-  *               Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
-  *         Note: In addition with this macro, VrefInt output buffer must be
-  *               connected to the selected I/O pin. Refer to macro
-  *               "__HAL_RI_IOSWITCH_CLOSE()".
-  * @note  VrefInt output enable: Internal reference voltage connected to I/O group 3
-  *        VrefInt output disable: Internal reference voltage disconnected from I/O group 3
-  * @retval None
-  */
-#define __HAL_SYSCFG_VREFINT_OUT_ENABLE()       SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
-#define __HAL_SYSCFG_VREFINT_OUT_DISABLE()      CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
-  * @{
-  */
-
-/**
-  * @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
-
-#if defined(FSMC_R_BASE)
-/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FSMC()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
-
-#endif /* FSMC_R_BASE */
-
-/**
-  * @brief  Returns the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one
-  *         of the following values:
-  *           @arg SYSCFG_BOOT_MAINFLASH
-  *           @arg SYSCFG_BOOT_SYSTEMFLASH
-  *           @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
-  *           @arg SYSCFG_BOOT_SRAM
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_USBConfig USB DP line Configuration
-  * @{
-  */
-
-/**
-  * @brief  Control the internal pull-up on USB DP line.
-  */
-#define __HAL_SYSCFG_USBPULLUP_ENABLE()       SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
-
-#define __HAL_SYSCFG_USBPULLUP_DISABLE()      CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_Macris RI: Routing Interface
-  * @{
-  */
-
-/** @defgroup RI_InputCaputureConfig Input Capture configuration
-  * @{
-  */
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__ Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__ selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  *     e.g.
-  *       __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
-  *       allows routing of Input capture IC1 of TIM2 to PA4.
-  *       For details about correspondence between RI_INPUTCAPTUREROUTING_x
-  *       and I/O pins refer to the parameters' description in the header file
-  *       or refer to the product reference manual.
-  * @note Input capture selection bits are not reset by this function.
-  *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.
-  * @note The I/O should be configured in alternate function mode (AF14) using
-  *       GPIO_PinAFConfig() function.
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__ Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__ selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__ Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__ selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__ Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__ selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
-          }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_SwitchControlConfig Switch Control configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable or disable the switch control mode.
-  * @note  ENABLE: ADC analog switches closed if the corresponding
-  *                    I/O switch is also closed.
-  *                    When using COMP1, switch control mode must be enabled.
-  * @note  DISABLE: ADC analog switches open or controlled by the ADC interface.
-  *                    When using the ADC for acquisition, switch control mode
-  *                    must be disabled.
-  * @note COMP1 comparator and ADC cannot be used at the same time since
-  *       they share the ADC switch matrix.
-  * @retval None
-  */
-#define __HAL_RI_SWITCHCONTROLMODE_ENABLE()       SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
-
-#define __HAL_RI_SWITCHCONTROLMODE_DISABLE()      CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
-
-/*
-  * @brief  Close or Open the routing interface Input Output switches.
-  * @param  __IOSWITCH__ selects the I/O analog switch number.
-  *   This parameter must be a value of @ref RI_IOSwitch
-  * @retval None
-  */
-#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
-            if ((__IOSWITCH__) >> 31 != 0 ) \
-            { \
-              SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
-            } \
-            else \
-            { \
-              SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
-            } \
-          }while(0)
-
-#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
-            if ((__IOSWITCH__) >> 31 != 0 ) \
-            { \
-              CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
-            } \
-            else \
-            { \
-              CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
-            } \
-          }while(0)
-
-#if defined (COMP_CSR_SW1)
-/**
-  * @brief  Close or open the internal switch COMP1_SW1.
-  *         This switch connects I/O pin PC3 (can be used as ADC channel 13)
-  *         and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
-  *         26) and COMP1 non-inverting input.
-  *         Pin PC3 connection depends on another switch setting, refer to
-  *         macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
-  * @retval None.
-  */
-#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE()  SET_BIT(COMP->CSR, COMP_CSR_SW1)
-
-#define __HAL_RI_SWITCH_COMP1_SW1_OPEN()   CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
-#endif /* COMP_CSR_SW1 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
-  * @{
-  */
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR1, (__IOPIN__)); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports B
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports C
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR2, (__IOPIN__)); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports D
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#if defined (GPIOE_BASE)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports E
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR3, (__IOPIN__)); \
-          } while(0)
-
-#endif /* GPIOE_BASE */
-
-#if defined(GPIOF_BASE) || defined(GPIOG_BASE)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports F
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports G
-  *         When the I/Os are programmed in input mode by standard I/O port
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR4, (__IOPIN__)); \
-          } while(0)
-
-#endif /* GPIOF_BASE || GPIOG_BASE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported variables --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Variables HAL Exported Variables
-  * @{
-  */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern uint32_t uwTickFreq;
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void              HAL_MspInit(void);
-void              HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void               HAL_IncTick(void);
-void               HAL_Delay(uint32_t Delay);
-uint32_t           HAL_GetTick(void);
-uint32_t           HAL_GetTickPrio(void);
-HAL_StatusTypeDef  HAL_SetTickFreq(uint32_t Freq);
-uint32_t           HAL_GetTickFreq(void);
-void               HAL_SuspendTick(void);
-void               HAL_ResumeTick(void);
-uint32_t           HAL_GetHalVersion(void);
-uint32_t           HAL_GetREVID(void);
-uint32_t           HAL_GetDEVID(void);
-uint32_t           HAL_GetUIDw0(void);
-uint32_t           HAL_GetUIDw1(void);
-uint32_t           HAL_GetUIDw2(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group3
-  * @{
-  */
-
-/* DBGMCU Peripheral Control functions  *****************************************/
-void              HAL_DBGMCU_EnableDBGSleepMode(void);
-void              HAL_DBGMCU_DisableDBGSleepMode(void);
-void              HAL_DBGMCU_EnableDBGStopMode(void);
-void              HAL_DBGMCU_DisableDBGStopMode(void);
-void              HAL_DBGMCU_EnableDBGStandbyMode(void);
-void              HAL_DBGMCU_DisableDBGStandbyMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h
deleted file mode 100644
index 4f10ffe28ef..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h
+++ /dev/null
@@ -1,1368 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc.h
-  * @author  MCD Application Team
-  * @brief   Header file containing functions prototypes of ADC HAL library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_ADC_H
-#define __STM32L1xx_HAL_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  Structure definition of ADC and regular group initialization 
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
-  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
-  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler
-                                       Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 
-                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
-                                       Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
-  uint32_t Resolution;            /*!< Configures the ADC resolution. 
-                                       This parameter can be a value of @ref ADC_Resolution */
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
-                                       This parameter can be a value of @ref ADC_Data_align */
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
-                                                    Scan direction is upward: from rank1 to rank 'n'.
-                                       This parameter can be a value of @ref ADC_Scan_mode */
-  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
-                                       This parameter can be a value of @ref ADC_EOCSelection.
-                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
-                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
-                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
-                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
-                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
-  uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
-                                       conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
-                                       This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 
-                                       This parameter can be a value of @ref ADC_LowPowerAutoWait.
-                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
-                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
-                                             and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
-                                       Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
-  uint32_t LowPowerAutoPowerOff;  /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
-                                       This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
-  uint32_t ChannelsBank;          /*!< Selects the ADC channels bank.
-                                       This parameter can be a value of @ref ADC_ChannelsBank.
-                                       Note: Banks availability depends on devices categories.
-                                       Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
-  FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after the selected trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
-#else
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       If set to external trigger source, triggering is on event rising edge by default.
-                                       This parameter can be a value of @ref ADC_External_trigger_source_Regular */
-  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
-                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
-  FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
-                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
-                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
-                                       This parameter can be set to ENABLE or DISABLE. */
-}ADC_InitTypeDef;
-
-/** 
-  * @brief  Structure definition of ADC channel for regular group   
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */ 
-typedef struct 
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels
-                                        Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
-                                              Maximum number of channels by device category (without taking in account each device package constraints): 
-                                              STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
-                                              STM32L1 category 3:    25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
-                                              STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
-                                        Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
-                                        Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
-                                        This parameter can be a value of @ref ADC_regular_rank
-                                        Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-}ADC_ChannelConfTypeDef;
-
-/**
-  * @brief  ADC Configuration analog watchdog definition
-  * @note   The setting of these parameters with function is conditioned to ADC state.
-  *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
-  */
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
-  uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
-                                   This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
-                                   This parameter can be a value of @ref ADC_channels. */
-  FunctionalState ITMode;     /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/** 
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  */ 
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             (0x00000000U)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             (0x00000001U)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           (0x00000004U)    /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010U)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020U)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         (0x00000040U)    /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          (0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           (0x00000200U)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           (0x00000400U)    /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         (0x00000800U)    /*!< Not available on STM32L1 device: End Of Sampling flag raised  */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          (0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           (0x00002000U)    /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000U)    /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              (0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              (0x00020000U)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              (0x00040000U)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/**
-  * @brief  ADC handle Structure definition
-  */ 
-typedef struct __ADC_HandleTypeDef
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
-
-  __IO uint32_t                 NbrOfConversionRank ;   /*!< ADC conversion rank counter */
-
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-
-  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
-
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
-  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
-  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
-  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
-  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */       /*!< ADC end of sampling callback */
-  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
-  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL ADC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
-  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
-  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
-  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
-  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
-  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL ADC Callback pointer definition
-  */
-typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE        (0x00U)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    (0x01U)   /*!< ADC IP internal error: if problem of clocking, 
-                                                          enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         (0x02U)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         (0x04U)   /*!< DMA transfer error                                    */
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
-  * @{
-  */
-#define ADC_CLOCK_ASYNC_DIV1          (0x00000000U)                   /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2          ((uint32_t)ADC_CCR_ADCPRE_0)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
-#define ADC_CLOCK_ASYNC_DIV4          ((uint32_t)ADC_CCR_ADCPRE_1)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */
-#define ADC_RESOLUTION_12B      (0x00000000U)                   /*!<  ADC 12-bit resolution */
-#define ADC_RESOLUTION_10B      ((uint32_t)ADC_CR1_RES_0)       /*!<  ADC 10-bit resolution */
-#define ADC_RESOLUTION_8B       ((uint32_t)ADC_CR1_RES_1)       /*!<  ADC 8-bit resolution */
-#define ADC_RESOLUTION_6B       ((uint32_t)ADC_CR1_RES)         /*!<  ADC 6-bit resolution */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Data_align ADC Data_align
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      (0x00000000U)
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC Scan mode
-  * @{
-  */
-#define ADC_SCAN_DISABLE         (0x00000000U)
-#define ADC_SCAN_ENABLE          ((uint32_t)ADC_CR1_SCAN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
-  * @{
-  */
-/* List of external triggers with generic trigger name, sorted by trigger     */
-/* name:                                                                      */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIGCONV_T2_CC3      ADC_EXTERNALTRIG_T2_CC3
-#define ADC_EXTERNALTRIGCONV_T2_CC2      ADC_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO     ADC_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_CC1      ADC_EXTERNALTRIG_T3_CC1
-#define ADC_EXTERNALTRIGCONV_T3_CC3      ADC_EXTERNALTRIG_T3_CC3
-#define ADC_EXTERNALTRIGCONV_T3_TRGO     ADC_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4      ADC_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T4_TRGO     ADC_EXTERNALTRIG_T4_TRGO
-#define ADC_EXTERNALTRIGCONV_T6_TRGO     ADC_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T9_CC2      ADC_EXTERNALTRIG_T9_CC2
-#define ADC_EXTERNALTRIGCONV_T9_TRGO     ADC_EXTERNALTRIG_T9_TRGO
-#define ADC_EXTERNALTRIGCONV_EXT_IT11    ADC_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START               (0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_EOCSelection ADC EOCSelection
-  * @{
-  */
-#define ADC_EOC_SEQ_CONV            (0x00000000U)
-#define ADC_EOC_SINGLE_CONV         ((uint32_t)ADC_CR2_EOCS)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
-  * @{
-  */
-/*!< Note : For compatibility with other STM32 devices with ADC autowait      */
-/* feature limited to enable or disable settings:                             */
-/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE".          */
-
-#define ADC_AUTOWAIT_DISABLE                (0x00000000U)
-#define ADC_AUTOWAIT_UNTIL_DATA_READ        ((uint32_t)(                                  ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
-#define ADC_AUTOWAIT_7_APBCLOCKCYCLES       ((uint32_t)(                 ADC_CR2_DELS_1                 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
-#define ADC_AUTOWAIT_15_APBCLOCKCYCLES      ((uint32_t)(                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
-#define ADC_AUTOWAIT_31_APBCLOCKCYCLES      ((uint32_t)(ADC_CR2_DELS_2                                  )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */
-#define ADC_AUTOWAIT_63_APBCLOCKCYCLES      ((uint32_t)(ADC_CR2_DELS_2                  | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */
-#define ADC_AUTOWAIT_127_APBCLOCKCYCLES     ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1                 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */
-#define ADC_AUTOWAIT_255_APBCLOCKCYCLES     ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
-  * @{
-  */
-#define ADC_AUTOPOWEROFF_DISABLE            (0x00000000U)
-#define ADC_AUTOPOWEROFF_IDLE_PHASE         ((uint32_t)ADC_CR1_PDI)                     /*!< ADC power off when ADC is not converting (idle phase) */
-#define ADC_AUTOPOWEROFF_DELAY_PHASE        ((uint32_t)ADC_CR1_PDD)                     /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
-#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES  ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD))     /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_ChannelsBank ADC ChannelsBank
-  * @{
-  */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CHANNELS_BANK_A                 (0x00000000U)
-#define ADC_CHANNELS_BANK_B                 ((uint32_t)ADC_CR2_CFG)
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
-                                   ((BANK) == ADC_CHANNELS_BANK_B)   )
-#else
-#define ADC_CHANNELS_BANK_A                 (0x00000000U)
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels ADC channels
-  * @{
-  */
-/* Note: Depending on devices, some channels may not be available on package  */
-/*       pins. Refer to device datasheet for channels availability.           */
-#define ADC_CHANNEL_0           (0x00000000U)                                                                                     /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_1           ((uint32_t)(                                                                    ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_2           ((uint32_t)(                                                   ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_3           ((uint32_t)(                                                   ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_4           ((uint32_t)(                                  ADC_SQR5_SQ1_2                                  ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_5           ((uint32_t)(                                  ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_6           ((uint32_t)(                                  ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_7           ((uint32_t)(                                  ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_8           ((uint32_t)(                 ADC_SQR5_SQ1_3                                                   ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_9           ((uint32_t)(                 ADC_SQR5_SQ1_3                                   | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_10          ((uint32_t)(                 ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_11          ((uint32_t)(                 ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_12          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                                  ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_13          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_14          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_15          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR5_SQ1_4                                                                    ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR5_SQ1_4                                                    | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR5_SQ1_4                                   | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_19          ((uint32_t)(ADC_SQR5_SQ1_4                                   | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_20          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2                                  ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_21          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_22          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_23          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_24          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                                                   ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_25          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                                   | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_26          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CHANNEL_27          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_28          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                                  ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_29          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_30          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_31          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-#define ADC_CHANNEL_VCOMP       ADC_CHANNEL_26  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CHANNEL_VOPAMP1     ADC_CHANNEL_3   /* Internal connection from OPAMP1 output to ADC switch matrix */
-#define ADC_CHANNEL_VOPAMP2     ADC_CHANNEL_8   /* Internal connection from OPAMP2 output to ADC switch matrix */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
-#define ADC_CHANNEL_VOPAMP3     ADC_CHANNEL_13  /* Internal connection from OPAMP3 output to ADC switch matrix */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC sampling times
-  * @{
-  */
-#define ADC_SAMPLETIME_4CYCLES      (0x00000000U)                                     /*!< Sampling time 4 ADC clock cycles */
-#define ADC_SAMPLETIME_9CYCLES      ((uint32_t) ADC_SMPR3_SMP0_0)                     /*!< Sampling time 9 ADC clock cycles */
-#define ADC_SAMPLETIME_16CYCLES     ((uint32_t) ADC_SMPR3_SMP0_1)                     /*!< Sampling time 16 ADC clock cycles */
-#define ADC_SAMPLETIME_24CYCLES     ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
-#define ADC_SAMPLETIME_48CYCLES     ((uint32_t) ADC_SMPR3_SMP0_2)                     /*!< Sampling time 48 ADC clock cycles */
-#define ADC_SAMPLETIME_96CYCLES     ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */
-#define ADC_SAMPLETIME_192CYCLES    ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */
-#define ADC_SAMPLETIME_384CYCLES    ((uint32_t) ADC_SMPR3_SMP0)                       /*!< Sampling time 384 ADC clock cycles */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
-  * @{
-  */
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2                                          \
-     (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 |     \
-      ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 |     \
-      ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2                                          \
-     (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \
-      ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \
-      ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
-     (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \
-      ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
-     (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \
-      ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \
-      ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2                                          \
-     (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-       
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1                                          \
-     (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 |     \
-      ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 |     \
-      ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1                                          \
-     (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \
-      ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \
-      ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
-     (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \
-      ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
-     (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \
-      ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \
-      ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1                                          \
-     (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-       
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0                                          \
-     (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 |     \
-      ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 |     \
-      ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0                                          \
-     (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \
-      ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \
-      ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
-     (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \
-      ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
-     (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \
-      ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \
-      ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0                                          \
-     (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_rank ADC rank into regular group
-  * @{
-  */
-#define ADC_REGULAR_RANK_1    (0x00000001U)
-#define ADC_REGULAR_RANK_2    (0x00000002U)
-#define ADC_REGULAR_RANK_3    (0x00000003U)
-#define ADC_REGULAR_RANK_4    (0x00000004U)
-#define ADC_REGULAR_RANK_5    (0x00000005U)
-#define ADC_REGULAR_RANK_6    (0x00000006U)
-#define ADC_REGULAR_RANK_7    (0x00000007U)
-#define ADC_REGULAR_RANK_8    (0x00000008U)
-#define ADC_REGULAR_RANK_9    (0x00000009U)
-#define ADC_REGULAR_RANK_10   (0x0000000AU)
-#define ADC_REGULAR_RANK_11   (0x0000000BU)
-#define ADC_REGULAR_RANK_12   (0x0000000CU)
-#define ADC_REGULAR_RANK_13   (0x0000000DU)
-#define ADC_REGULAR_RANK_14   (0x0000000EU)
-#define ADC_REGULAR_RANK_15   (0x0000000FU)
-#define ADC_REGULAR_RANK_16   (0x00000010U)
-#define ADC_REGULAR_RANK_17   (0x00000011U)
-#define ADC_REGULAR_RANK_18   (0x00000012U)
-#define ADC_REGULAR_RANK_19   (0x00000013U)
-#define ADC_REGULAR_RANK_20   (0x00000014U)
-#define ADC_REGULAR_RANK_21   (0x00000015U)
-#define ADC_REGULAR_RANK_22   (0x00000016U)
-#define ADC_REGULAR_RANK_23   (0x00000017U)
-#define ADC_REGULAR_RANK_24   (0x00000018U)
-#define ADC_REGULAR_RANK_25   (0x00000019U)
-#define ADC_REGULAR_RANK_26   (0x0000001AU)
-#define ADC_REGULAR_RANK_27   (0x0000001BU)
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_REGULAR_RANK_28   (0x0000001CU)
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000U)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_conversion_group ADC conversion group
-  * @{
-  */
-#define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC))
-#define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC))
-#define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event type
-  * @{
-  */
-#define ADC_AWD_EVENT               ((uint32_t)ADC_FLAG_AWD)   /*!< ADC Analog watchdog event */
-#define ADC_OVR_EVENT               ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
-  * @{
-  */
-#define ADC_IT_EOC           ADC_CR1_EOCIE        /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_JEOC          ADC_CR1_JEOCIE       /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_AWD           ADC_CR1_AWDIE        /*!< ADC Analog watchdog interrupt source */
-#define ADC_IT_OVR           ADC_CR1_OVRIE        /*!< ADC overrun interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC flags definition
-  * @{
-  */
-#define ADC_FLAG_AWD           ADC_SR_AWD      /*!< ADC Analog watchdog flag */
-#define ADC_FLAG_EOC           ADC_SR_EOC      /*!< ADC End of Regular conversion flag */
-#define ADC_FLAG_JEOC          ADC_SR_JEOC     /*!< ADC End of Injected conversion flag */
-#define ADC_FLAG_JSTRT         ADC_SR_JSTRT    /*!< ADC Injected group start flag */
-#define ADC_FLAG_STRT          ADC_SR_STRT     /*!< ADC Regular group start flag */
-#define ADC_FLAG_OVR           ADC_SR_OVR      /*!< ADC overrun flag */
-#define ADC_FLAG_ADONS         ADC_SR_ADONS    /*!< ADC ready status flag */
-#define ADC_FLAG_RCNR          ADC_SR_RCNR     /*!< ADC Regular group ready status flag */
-#define ADC_FLAG_JCNR          ADC_SR_JCNR     /*!< ADC Injected group ready status flag */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/* List of external triggers of regular group for ADC1:                       */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T9_CC2         (0x00000000U)
-#define ADC_EXTERNALTRIG_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T2_CC3         ((uint32_t)(                                      ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_T2_CC2         ((uint32_t)(                                      ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_TRGO        ((uint32_t)(                   ADC_CR2_EXTSEL_2                                      ))
-#define ADC_EXTERNALTRIG_T4_CC4         ((uint32_t)(                   ADC_CR2_EXTSEL_2 |                    ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T2_TRGO        ((uint32_t)(                   ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_T3_CC1         ((uint32_t)(                   ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_CC3         ((uint32_t)(ADC_CR2_EXTSEL_3                                                         ))
-#define ADC_EXTERNALTRIG_T4_TRGO        ((uint32_t)(ADC_CR2_EXTSEL_3                                       | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T6_TRGO        ((uint32_t)(ADC_CR2_EXTSEL_3                    | ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_EXT_IT11       ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL   (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \
-                                 ADC_FLAG_OVR)
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */
-
-/**
-  * @brief Enable the ADC peripheral
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE(__HANDLE__)                                           \
-  (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
-
-/**
-  * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
-  (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
-
-/**
-  * @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  *            @arg ADC_IT_OVR: ADC overrun interrupt source
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
-  (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-    
-/**
-  * @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  *            @arg ADC_IT_OVR: ADC overrun interrupt source
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
-  *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
-  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
-  *            @arg ADC_IT_OVR: ADC overrun interrupt source
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  *          This parameter can be any combination of the following values:
-  *            @arg ADC_FLAG_STRT: ADC Regular group start flag
-  *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
-  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
-  *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
-  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
-  *            @arg ADC_FLAG_OVR: ADC overrun flag
-  *            @arg ADC_FLAG_ADONS: ADC ready status flag
-  *            @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
-  *            @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
-  ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  *            @arg ADC_FLAG_STRT: ADC Regular group start flag
-  *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
-  *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
-  *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
-  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
-  *            @arg ADC_FLAG_OVR: ADC overrun flag
-  *            @arg ADC_FLAG_ADONS: ADC ready status flag
-  *            @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
-  *            @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
-  (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/** @brief  Reset ADC handle state
-  * @param  __HANDLE__ ADC handle
-  * @retval None
-  */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  do{                                                                          \
-     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
-     (__HANDLE__)->MspInitCallback = NULL;                                     \
-     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
-    } while(0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
-   
-/**
-  * @}
-  */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define ADC_IS_ENABLE(__HANDLE__)                                              \
-  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
-  ) ? SET : RESET)
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
-  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
-
-/**
-  * @brief Simultaneously clears and sets specific bits of the handle State
-  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
-  * @brief Set ADC number of ranks into regular channel sequence length.
-  * @param _NbrOfConversion_: Regular channel sequence length 
-  * @retval None
-  */
-#define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
-  (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 1 and 6.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 7 and 12.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 13 and 18.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 19 and 24.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
-      
-/**
-  * @brief Set the selected regular channel rank for rank between 25 and 28.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
-  ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
-      
-/**
-  * @brief Set the injected sequence length.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define ADC_JSQR_JL_SHIFT(_JSQR_JL_)   (((_JSQR_JL_) -1) << 20)
-
-/**
-  * @brief Set the selected injected channel rank
-  *        Note: on STM32L1 devices, channel rank position in JSQR register
-  *              is depending on total number of ranks selected into
-  *              injected sequencer (ranks sequence starting from 4-JL)
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
-  ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
-
-/**
-  * @brief Enable the ADC DMA continuous request.
-  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
-  * @retval None
-  */
-#define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_)                                  \
-  ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
-
-/**
-  * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
-  * @retval None
-  */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
-  ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
-
-/**
-  * @brief Configures the number of discontinuous conversions for the regular group channels.
-  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
-  * @retval None
-  */
-#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
-  (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
-
-/**
-  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_: Scan conversion mode.
-  * @retval None
-  */
-/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
-/*       is equivalent to ADC_SCAN_ENABLE.                                    */
-#define ADC_CR1_SCAN_SET(_SCAN_MODE_)                                          \
-  (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
-   )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
-  )
-
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4)   )
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_6B)    )
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
-                                                ((RESOLUTION) == ADC_RESOLUTION_6B)   )
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
-                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
-
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)              )
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
-                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)         )
-
-#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE)            || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ)    || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES)   || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES)   )
-
-#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE)          || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE)       || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE)      || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES)  )
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
-                                   ((BANK) == ADC_CHANNELS_BANK_B)   )
-#else
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_19)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_20)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_21)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_22)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_23)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_24)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_25)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_26)            )
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_19)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_20)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_21)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_22)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_23)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_24)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_25)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_26)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_27)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_28)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_29)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_30)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_31)            )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES)   || \
-                                  ((TIME) == ADC_SAMPLETIME_9CYCLES)   || \
-                                  ((TIME) == ADC_SAMPLETIME_16CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_24CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_48CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_96CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_192CYCLES) || \
-                                  ((TIME) == ADC_SAMPLETIME_384CYCLES)   )
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-       
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_17) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_18) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_19) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_20) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_21) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_22) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_23) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_24) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_25) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_26) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_27) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_28)   )
-#else
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_17) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_18) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_19) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_20) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_21) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_22) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_23) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_24) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_25) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_26) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_27)   )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
-                                             ((CONVERSION) == ADC_INJECTED_GROUP)        || \
-                                             ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT)  || \
-                                  ((EVENT) == ADC_FLAG_OVR) )
-
-/**
-  * @brief Verify that a ADC data is within range corresponding to
-  *        ADC resolution.
-  * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
-  * @param __ADC_DATA__: value checked against the resolution.     
-  * @retval SET: ADC data is within range corresponding to ADC resolution
-  *         RESET: ADC data is not within range corresponding to ADC resolution
-  *
-  */  
-#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__)                                          \
-   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_DATA__) <= (0x00FFU))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_DATA__) <= (0x003FU)))   )
-
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
-#else
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
-#endif
-
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
-
-/**
-  * @}
-  */
-    
-    
-/* Include ADC HAL Extension module */
-#include "stm32l1xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* IO operation functions  *****************************************************/
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @{
-  */
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADC_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/* Internal HAL driver functions **********************************************/
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h
deleted file mode 100644
index 56dcdc94c97..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_ADC_EX_H
-#define __STM32L1xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  ADC Configuration injected Channel structure definition
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
-  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
-  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
-  */
-typedef struct 
-{
-  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
-                                               This parameter can be a value of @ref ADC_channels
-                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
-  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
-                                               This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles
-                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times
-                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.      
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
-                                               If set to external trigger source, triggering is on event rising edge.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
-                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef; 
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-   
-/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    (0x00000001U)
-#define ADC_INJECTED_RANK_2    (0x00000002U)
-#define ADC_INJECTED_RANK_3    (0x00000003U)
-#define ADC_INJECTED_RANK_4    (0x00000004U)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000U)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected
-  * @{
-  */
-/* External triggers for injected groups of ADC1 */
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1      ADC_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO     ADC_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4      ADC_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO     ADC_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC1      ADC_EXTERNALTRIGINJEC_T4_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC2      ADC_EXTERNALTRIGINJEC_T4_CC2
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3      ADC_EXTERNALTRIGINJEC_T4_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO     ADC_EXTERNALTRIGINJEC_T7_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T9_CC1      ADC_EXTERNALTRIGINJEC_T9_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T9_TRGO     ADC_EXTERNALTRIGINJEC_T9_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T10_CC1     ADC_EXTERNALTRIGINJEC_T10_CC1
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15    ADC_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START      (0x00000010U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected
-  * @{
-  */
-
-/* List of external triggers of injected group for ADC1:                      */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-#define ADC_EXTERNALTRIGINJEC_T9_CC1         (0x00000000U)
-#define ADC_EXTERNALTRIGINJEC_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO        ((uint32_t)(                                      ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_T2_CC1         ((uint32_t)(                                      ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T3_CC4         ((uint32_t)(                   ADC_CR2_JEXTSEL_2                                      ))
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO        ((uint32_t)(                   ADC_CR2_JEXTSEL_2 |                    ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T4_CC1         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_T4_CC2         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T4_CC3         ((uint32_t)(ADC_CR2_JEXTSEL_3                                                         ))
-#define ADC_EXTERNALTRIGINJEC_T10_CC1        ((uint32_t)(ADC_CR2_JEXTSEL_3                                       | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T7_TRGO        ((uint32_t)(ADC_CR2_JEXTSEL_3                    | ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15       ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */
-
-/**
-  * @brief Selection of channels bank. 
-  * Note: Banks availability depends on devices categories.
-  * This macro is intended to change bank selection quickly on the fly,   
-  * without going through ADC init structure update and execution of function
-  * 'HAL_ADC_Init()'.
-  * @param __HANDLE__: ADC handle
-  * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank.
-  * @retval None
-  */
-#define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__)                          \
-  MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__))
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
- * @brief Configures the ADC channels speed.
- * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5.
- *  - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is
- *    in power down mode.
- *  - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is
- *    in power down mode.
- *  - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in 
- *    power down mode. Otherwise, channel 13 is connected to OPAMP3 output and 
- *    routed through switches COMP1_SW1 and VCOMP to ADC switch matrix.
- *    (Note: OPAMP3 is available on STM32L1 Cat.4 only).
- * @param __CHANNEL__: ADC channel
- * This parameter can be one of the following values:
- * @arg ADC_CHANNEL_3: Channel 3 is selected.
- * @arg ADC_CHANNEL_8: Channel 8 is selected.
- * @arg ADC_CHANNEL_13: Channel 13 is selected.
- * @retval None
- */
-#define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__)                              \
-  ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
-    )?                                                                         \
-     (SET_BIT(COMP->CSR, COMP_CSR_FCH3))                                       \
-     :                                                                         \
-     ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
-       )?                                                                      \
-        (SET_BIT(COMP->CSR, COMP_CSR_FCH8))                                    \
-        :                                                                      \
-        ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
-          )?                                                                   \
-           (SET_BIT(COMP->CSR, COMP_CSR_RCH13))                                \
-           :                                                                   \
-           (SET_BIT(COMP->CSR, 0x00000000))                                    \
-        )                                                                      \
-     )                                                                         \
-  )
-
-#define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__)                              \
-  ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
-    )?                                                                         \
-     (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3))                                     \
-     :                                                                         \
-     ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
-       )?                                                                      \
-        (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8))                                  \
-        :                                                                      \
-        ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
-          )?                                                                   \
-           (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13))                              \
-           :                                                                   \
-           (SET_BIT(COMP->CSR, 0x00000000))                                    \
-        )                                                                      \
-     )                                                                         \
-  )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    
-/**
-  * @}
-  */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Set ADC ranks available in register SQR1.
-  * Register SQR1 bits availability depends on device category.
-  * @param _NbrOfConversion_: Regular channel sequence length 
-  * @retval None
-  */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define __ADC_SQR1_SQXX   (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
-#else
-#define __ADC_SQR1_SQXX   (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 30 and 31.
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro does nothing.
-  * @retval None
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
-#else
-#define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_)                                   \
-  (0x00000000U)
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief Set the ADC's sample time for channel numbers between 20 and 29.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
-#else
-/**
-  * @brief Set the ADC's sample time for channel numbers between 20 and 26.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief Defines the highest channel available in register SMPR1. Channels
-  * availability depends on device category:
-  * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3
-  * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5
-  * @param None
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_29
-#else
-#define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_26
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-
-/**
-  * @brief Define mask of configuration bits of ADC and regular group in
-  * register CR2 (bits of ADC enable, conversion start and injected group are 
-  * excluded of this mask).
-  * @retval None
-  */
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CR2_MASK_ADCINIT()                                                 \
-  (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT)
-#else
-#define ADC_CR2_MASK_ADCINIT()                                                 \
-  (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT)
-#endif
-
-
-/**
-  * @brief Get the maximum ADC conversion cycles on all channels.
-  * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
-  * Approximation of sampling time within 2 ranges, returns the highest value:
-  *   below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles}
-  *   between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles}
-  * Unit: ADC clock cycles
-  * @param __HANDLE__: ADC handle
-  * @retval ADC conversion cycles on all channels
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                            \
-    (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ?            \
-                                                                                                        \
-        ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
-     )
-#else
-#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                            \
-    (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?            \
-                                                                                                        \
-        ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
-     )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief Get the ADC clock prescaler from ADC common control register
-  * and convert it to its decimal number setting (refer to reference manual)
-  * @retval None
-  */
-#define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__)                            \
-    ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE)))
-
-/**
-  * @brief Clear register SMPR0.
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro performs no action.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SMPR1_CLEAR(__HANDLE__)                                                                     \
-      CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |   \
-                                                ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |   \
-                                                ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |   \
-                                                ADC_SMPR1_SMP20                                      ))
-
-#define ADC_SMPR0_CLEAR(__HANDLE__)                                              \
-  (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)))
-#else
-#define ADC_SMPR1_CLEAR(__HANDLE__)                                                                   \
-    CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |   \
-                                              ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |   \
-                                              ADC_SMPR1_SMP20                                      ))
-
-#define ADC_SMPR0_CLEAR(__HANDLE__) __NOP()
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief Clear register CR2.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CR2_CLEAR(__HANDLE__)                                                                  \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
-                                           ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
-                                           ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
-                                           ADC_CR2_DMA      | ADC_CR2_DELS   | ADC_CR2_CFG     |   \
-                                           ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
-  )
-#else
-#define ADC_CR2_CLEAR(__HANDLE__)                                                                  \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
-                                           ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
-                                           ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
-                                           ADC_CR2_DMA      | ADC_CR2_DELS   |                     \
-                                           ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
-  )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief Set the sampling time of selected channel on register SMPR0
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro performs no action.
-  * @param __HANDLE__: ADC handle
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param __CHANNEL__: Channel number.
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__)           \
-    MODIFY_REG((__HANDLE__)->Instance->SMPR0,                                  \
-               ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)),                      \
-               ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__))  )
-#else
-#define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP()
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */     
-
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_4)   )
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )
-
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                      ((REGTRIG) == ADC_SOFTWARE_START)                   )
-
-/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
-  * @{
-  */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */      
-   
-   
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h
deleted file mode 100644
index 84451306598..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h
+++ /dev/null
@@ -1,658 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_COMP_H
-#define __STM32L1xx_HAL_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup COMP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup COMP_Exported_Types COMP Exported Types
-  * @{
-  */
-    
-/** 
-  * @brief  COMP Init structure definition  
-  */
-typedef struct
-{
-
-  uint32_t InvertingInput;        /*!< Selects the inverting input of the comparator.
-                                       This parameter can be a value of @ref COMP_InvertingInput
-                                       Note: Inverting input can be changed on the fly, while comparator is running.
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded (On COMP1, inverting input is fixed to Vrefint). */
-
-  uint32_t NonInvertingInput;     /*!< Selects the non inverting input of the comparator.
-                                       This parameter can be a value of @ref COMPEx_NonInvertingInput */
-
-  uint32_t Output;                /*!< Selects the output redirection of the comparator.
-                                       This parameter can be a value of @ref COMP_Output
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */
-
-  uint32_t Mode;                  /*!< Selects the operating consumption mode of the comparator
-                                       to adjust the speed/consumption.
-                                       This parameter can be a value of @ref COMP_Mode
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */
-                                         
-  uint32_t WindowMode;            /*!< Selects the window mode of the 2 comparators.
-                                       If enabled, non-inverting inputs of the 2 comparators are connected together and are using inputs of COMP2 only (COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP).
-                                       This parameter can be a value of @ref COMP_WindowMode
-                                       Note: This feature must be enabled from COMP2 instance. If COMP1 is selected, this parameter is discarded. */
-
-  uint32_t TriggerMode;           /*!< Selects the trigger mode of the comparator when using interruption on EXTI line (interrupt mode).
-                                       This parameter can be a value of @ref COMP_TriggerMode
-                                       Note: This feature is used with function "HAL_COMP_Start_IT()". In all other functions, this parameter is discarded. */
-
-  uint32_t NonInvertingInputPull; /*!< Selects the internal pulling resistor connected on non inverting input.
-                                       This parameter can be a value of @ref COMP_NonInvertingInputPull
-                                       Note: To avoid extra power consumption, only one resistor should be enabled at a time.
-                                       Note: This feature is available on COMP1 only. If COMP2 is selected, this parameter is discarded. */
-  
-}COMP_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_COMP_STATE_RESET             = 0x00,    /*!< COMP not yet initialized or disabled             */
-  HAL_COMP_STATE_READY             = 0x01,    /*!< COMP initialized and ready for use               */
-  HAL_COMP_STATE_READY_LOCKED      = 0x11,    /*!< COMP initialized but the configuration is locked */
-  HAL_COMP_STATE_BUSY              = 0x02,    /*!< COMP is running                                  */
-  HAL_COMP_STATE_BUSY_LOCKED       = 0x12     /*!< COMP is running and the configuration is locked  */
-}HAL_COMP_StateTypeDef;
-
-/** 
-  * @brief  COMP Handle Structure definition  
-  */ 
-typedef struct __COMP_HandleTypeDef
-{
-  COMP_TypeDef       *Instance;       /*!< Register base address    */
-  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
-  HAL_LockTypeDef    Lock;            /*!< Locking object           */
-  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
-  __IO uint32_t      ErrorCode;       /*!< COMP Error code */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
-  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
-  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-} COMP_HandleTypeDef;
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL COMP Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
-  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
-  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
-} HAL_COMP_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL COMP Callback pointer definition
-  */
-typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
-
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_Error_Code COMP Error Code
-  * @{
-  */
-#define HAL_COMP_ERROR_NONE             (0x00U)   /*!< No error */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Output COMP Output
-  * @{
-  */
-#define COMP_OUTPUT_TIM2IC4                     (0x00000000U)                                               /*!< COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR                (                                        COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC4                     (                    COMP_CSR_OUTSEL_1                    ) /*!< COMP2 output connected to TIM3 Input Capture 4 */
-#define COMP_OUTPUT_TIM3OCREFCLR                (                    COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM3 OCREF Clear */
-#define COMP_OUTPUT_TIM4IC4                     (COMP_CSR_OUTSEL_2                                        ) /*!< COMP2 output connected to TIM4 Input Capture 4 */
-#define COMP_OUTPUT_TIM4OCREFCLR                (COMP_CSR_OUTSEL_2                     | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM4 OCREF Clear */
-#define COMP_OUTPUT_TIM10IC1                    (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1                    ) /*!< COMP2 output connected to TIM10 Input Capture 1 */
-#define COMP_OUTPUT_NONE                        (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output is not connected to other peripherals */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_TIM2IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM3IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM4IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM10IC1)     || \
-                                ((OUTPUT) == COMP_OUTPUT_NONE)           )
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_InvertingInput COMP InvertingInput
-  * @{
-  */
-/* Inverting Input specific to COMP2 */
-#define COMP_INVERTINGINPUT_IO                  (                                      COMP_CSR_INSEL_0) /*!< External I/O (COMP2_INM connected to pin PB3) connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_VREFINT             (                   COMP_CSR_INSEL_1                   ) /*!< VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT          (                   COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< 3/4 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT          (COMP_CSR_INSEL_2                                      ) /*!< 1/2 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_1_4VREFINT          (COMP_CSR_INSEL_2                    | COMP_CSR_INSEL_0) /*!< 1/4 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_DAC1                (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1                   ) /*!< DAC_OUT1 (PA4) connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_DAC2                (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< DAC2_OUT (PA5) connected to comparator 2 inverting input */
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_IO)         || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_VREFINT)    || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_DAC1)       || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_DAC2)         )
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Mode COMP Mode
-  * @{
-  */
-/* Please refer to the electrical characteristics in the device datasheet for
-   the power consumption values */
-#define COMP_MODE_LOWSPEED          (0x00000000U)           /*!< Low Speed */
-#define COMP_MODE_HIGHSPEED         COMP_CSR_SPEED          /*!< High Speed */
-
-#define IS_COMP_MODE(SPEED)    (((SPEED) == COMP_MODE_LOWSPEED) || \
-                                ((SPEED) == COMP_MODE_HIGHSPEED))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_WindowMode COMP WindowMode
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLE               (0x00000000U)  /*!< Window mode disabled: COMP1 non-inverting input is independant */
-#define COMP_WINDOWMODE_ENABLE                COMP_CSR_WNDWE          /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
-                                        ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputLevel COMP OutputLevel
-  * @{
-  */ 
-/* Comparator output is low when the non-inverting input is at a lower        */
-/* voltage than the inverting input.                                          */
-#define COMP_OUTPUTLEVEL_LOW                   (0x00000000U)
-
-/* Comparator output is high when the non-inverting input is at a higher      */
-/* voltage than the inverting input.                                          */
-#define COMP_OUTPUTLEVEL_HIGH                  (0x00000001U)
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_TriggerMode COMP TriggerMode 
-  * @{
-  */
-#define COMP_TRIGGERMODE_NONE                  (0x00000000U)   /*!< No External Interrupt trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING             (0x00000001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_IT_FALLING            (0x00000002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING     (0x00000003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define IS_COMP_TRIGGERMODE(MODE)  (((MODE) == COMP_TRIGGERMODE_NONE)             || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_RISING)        || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_FALLING)       || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING)  )
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent
-  * @{
-  */
-#define COMP_EXTI_LINE_COMP1             EXTI_RTSR_TR21  /*!< External interrupt line 21 Connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2             EXTI_RTSR_TR22  /*!< External interrupt line 22 Connected to COMP2 */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_NonInvertingInputPull COMP NonInvertingInputPull
-  * @{
-  */
-#define COMP_NONINVERTINGINPUT_NOPULL           (0x00000000U)           /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_10KPU            COMP_CSR_10KPU          /*!< Internal 10kOhm pull-up resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_10KPD            COMP_CSR_10KPD          /*!< Internal 10kOhm pull-down resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_400KPU           COMP_CSR_400KPU         /*!< Internal 400kOhm pull-up resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_400KPD           COMP_CSR_400KPD         /*!< Internal 400kOhm pull-down resistor connected to comparator non inverting input */
-
-#define IS_COMP_NONINVERTINGINPUTPULL(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_NOPULL) || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_10KPU)  || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_10KPD)  || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_400KPU) || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_400KPD)   )
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Macro COMP Exported Macro
-  * @{
-  */
-
-/** @defgroup COMP_Handle_Management  COMP Handle Management
-  * @{
-  */
-
-/** @brief Reset COMP handle state
-  * @param  __HANDLE__ COMP handle.
-  * @retval None
-  */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
-                                                     (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
-                                                     (__HANDLE__)->MspInitCallback = NULL;            \
-                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0)
-#else
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-#endif
-
-/**
-  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
-  * @param __HANDLE__ COMP handle
-  * @retval None
-  */
-#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) 
-
-/**
-  * @brief Enables the specified comparator
-  * @param  __HANDLE__ COMP handle.
-  * @retval None.
-  */
-#define __HAL_COMP_ENABLE(__HANDLE__)                                          \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     SET_BIT(COMP->CSR, COMP_CSR_CMP1EN)                                       \
-     :                                                                         \
-     MODIFY_REG(COMP->CSR, COMP_CSR_INSEL, (__HANDLE__)->Init.InvertingInput ) \
-  )
-
-/**
-  * @brief Disables the specified comparator
-  * @param  __HANDLE__ COMP handle.
-  * @retval None.
-  */
-#define __HAL_COMP_DISABLE(__HANDLE__)                                         \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     CLEAR_BIT(COMP->CSR, COMP_CSR_CMP1EN)                                     \
-     :                                                                         \
-     CLEAR_BIT(COMP->CSR, COMP_CSR_INSEL)                                      \
-  )
-
-/** @brief  Checks whether the specified COMP flag is set or not.
-  * @param  __HANDLE__ specifies the COMP Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg COMP_FLAG_LOCK:  lock flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->CSR, (__FLAG__)) == (__FLAG__))   
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI Line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI Line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Check whether the COMP1 EXTI line flag is set or not.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
-     
-/**
-  * @brief  Clear the the COMP1 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Generates a Software interrupt on COMP1 EXTI Line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()              SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
-                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP2 EXTI line.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI Line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI Line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Check whether the COMP2 EXTI line flag is set or not.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
-     
-/**
-  * @brief  Clear the the COMP2 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Generates a Software interrupt on COMP1 EXTI Line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()              SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
-
-/**
-  * @}
-  */ 
-    
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Macro COMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__ specifies the COMP instance.
-  * @retval value of @ref COMP_ExtiLineEvent
-  */
-#define COMP_GET_EXTI_LINE(__INSTANCE__)                                       \
-  ( ( ((__INSTANCE__) == COMP1)                                                \
-    )?                                                                         \
-     (COMP_EXTI_LINE_COMP1)                                                    \
-     :                                                                         \
-     (COMP_EXTI_LINE_COMP2)                                                    \
-  )
-
-/**
-  * @brief Select the COMP register CSR bit CMPxOUT corresponding to the 
-  * selected COMP instance.
-  * @param __HANDLE__: COMP handle
-  * @retval Comparator register CSR bit COMP_CSR_CMP1OUT or COMP_CSR_CMP2OUT
-  */
-#define __COMP_CSR_CMPXOUT(__HANDLE__)                                         \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     (COMP_CSR_CMP1OUT)                                                        \
-     :                                                                         \
-     (COMP_CSR_CMP2OUT)                                                        \
-  )
-
-/**
-  * @brief Verification of COMP state: enabled or disabled
-  * @param __HANDLE__: COMP handle
-  * @retval SET (COMP enabled) or RESET (COMP disabled)
-  */
-#define __COMP_IS_ENABLED(__HANDLE__)                                          \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     (((READ_BIT(COMP->CSR , COMP_CSR_CMP1EN) == COMP_CSR_CMP1EN)              \
-      ) ? SET : RESET)                                                         \
-     :                                                                         \
-     (((READ_BIT(COMP->CSR , COMP_CSR_INSEL) != RESET)                         \
-      ) ? SET : RESET)                                                         \
-  )
-    
-/**
-  * @}
-  */ 
-
-    
-/* Include COMP HAL Extension module */
-#include "stm32l1xx_hal_comp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-/** @addtogroup COMP_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-
-/* Callback in Interrupt mode */
-void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
-  * @{
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h
deleted file mode 100644
index e5fd07b0142..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_COMP_EX_H
-#define __STM32L1xx_HAL_COMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMPEx COMPEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Constants COMPEx Exported Constants
-  * @{
-  */
-
-/** @defgroup COMPEx_NonInvertingInput COMPEx NonInvertingInput
-  * @{
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB6      RI_IOSWITCH_GR6_3       /*!< I/O pin PB6 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB7      RI_IOSWITCH_GR6_4       /*!< I/O pin PB7 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     (0x00000000U)           /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH6         /*!< I/O pin PA6 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF6      RI_IOSWITCH_CH27        /*!< I/O pin PF6 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF7      RI_IOSWITCH_CH28        /*!< I/O pin PF7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF8      RI_IOSWITCH_CH29        /*!< I/O pin PF8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF9      RI_IOSWITCH_CH30        /*!< I/O pin PF9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF10     RI_IOSWITCH_CH31        /*!< I/O pin PF10 connection to COMP1 non-inverting input */
-
-#define COMP_NONINVERTINGINPUT_OPAMP1   COMP_NONINVERTINGINPUT_PA3  /*!< OPAMP1 output connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_OPAMP2   COMP_NONINVERTINGINPUT_PB0  /*!< OPAMP2 output connection to COMP1 non-inverting input */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
-#define COMP_NONINVERTINGINPUT_OPAMP3   COMP_NONINVERTINGINPUT_PC3  /*!< OPAMP3 output connection to COMP1 non-inverting input */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-   
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB6      RI_IOSWITCH_GR6_3       /*!< I/O pin PB6 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB7      RI_IOSWITCH_GR6_4       /*!< I/O pin PB7 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     (0x00000000U)  /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-
-#define COMP_NONINVERTINGINPUT_OPAMP1   COMP_NONINVERTINGINPUT_PA3  /*!< OPAMP1 output connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_OPAMP2   COMP_NONINVERTINGINPUT_PB0  /*!< OPAMP2 output connection to COMP1 non-inverting input */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */   
-   
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     (0x00000000U)  /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF10)    )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)    )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)    )
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup COMPEx_Private_Macro COMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief Specifies whether Routing Interface (RI) needs to be configured for 
-  * switches of comparator non-inverting input.
-  * @param  __HANDLE__ COMP handle.
-  * @retval None.
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__)                    \
-  (((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) &&    \
-   (READ_BIT(COMP->CSR, COMP_CSR_SW1) == RESET)                            )
-#else
-#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__)                    \
-  ((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE)
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @}
-  */ 
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_COMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h
deleted file mode 100644
index 06fbc294106..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CONF_H
-#define __STM32L1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LCD_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    (2097000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
-  #define LSI_VALUE    (37000U) /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */          /*!< Value of the Internal Low Speed oscillator in Hz
-                                     The real value may vary depending on the variations
-                                     in voltage and temperature.*/
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    (32768U) /*!< Value of the External Low Speed oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x000FU)    /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     0U
-#define  DATA_CACHE_ENABLE            0U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1U*/
-
-/* ################## Register callback feature configuration ############### */
-/**
-  * @brief Set below the peripheral configuration  to "1U" to add the support
-  *        of HAL callback registration/deregistration feature for the HAL
-  *        driver(s). This allows user application to provide specific callback
-  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
-  *        the default weak callback functions (see each stm32l0xx_hal_ppp.h file
-  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
-  *        for each PPP peripheral).
-  */
-#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
-#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
-#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
-#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
-#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
-#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
-#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
-#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
-#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
-#define USE_HAL_SDMMC_REGISTER_CALLBACKS      0U
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
-#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
-#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
-#define USE_HAL_UART_REGISTER_CALLBACKS       0U
-#define USE_HAL_USART_REGISTER_CALLBACKS      0U
-#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32l1xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l1xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l1xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l1xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l1xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h
deleted file mode 100644
index 2ce2cac208f..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CORTEX_H
-#define __STM32L1xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */
-  
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group 
-  * @{
-  */
-
-#define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bits for pre-emption priority
-                                                        4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bits for pre-emption priority
-                                                        3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority
-                                                        2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority
-                                                        1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority
-                                                        0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
-#define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)  
-#define  MPU_HARDFAULT_NMI           (MPU_CTRL_HFNMIENA_Msk)
-#define  MPU_PRIVILEGED_DEFAULT      (MPU_CTRL_PRIVDEFENA_Msk)
-#define  MPU_HFNMI_PRIVDEF           (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-/**                                
-  * @}
-  */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-  
-/* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group_Macro  CORTEX Preemption Priority Group 
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */  
-                                  
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
-  * @{
-  */                       
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-                                                                                   
-/* Private functions ---------------------------------------------------------*/   
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
-  * @brief    CORTEX private  functions 
-  * @{
-  */
-
-
-/**
-  * @}
-  */ 
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
-  * @{
-  */  
-/* Initialization and de-initialization functions *****************************/
-void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void     HAL_SYSTICK_IRQHandler(void);
-void     HAL_SYSTICK_Callback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CORTEX_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h
deleted file mode 100644
index 878c46ef429..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_crc.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_CRC_H
-#define STM32L1xx_HAL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  CRC HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
-} HAL_CRC_StateTypeDef;
-
-
-/**
-  * @brief  CRC Handle Structure definition
-  */
-typedef struct
-{
-  CRC_TypeDef                 *Instance;   /*!< Register base address        */
-
-  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
-
-  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
-
-} CRC_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRC handle state.
-  * @param  __HANDLE__ CRC handle.
-  * @retval None
-  */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
-  * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
-  * @brief Store data in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @param __VALUE__  Value to be stored in the ID register
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval None
-  */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
-  * @brief Return the data stored in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval Value of the ID register
-  */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup  CRC_Private_Macros CRC Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h
deleted file mode 100644
index e0d36cc5b1e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CRYP_H
-#define __STM32L1xx_HAL_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRYP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  CRYP Configuration Structure definition  
-  */
-typedef struct
-{  
-  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                             This parameter can be a value of @ref CRYP_Data_Type */
-  
-  uint8_t* pKey;        /*!< The key used for encryption/decryption */
-  
-  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
-                             counter in CTR mode */
-  
-}CRYP_InitTypeDef;
-
-/** 
-  * @brief HAL CRYP State structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
-  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
-  HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */ 
-    
-}HAL_CRYP_STATETypeDef;
-
-/** 
-  * @brief HAL CRYP phase structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
-  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
-}HAL_PhaseTypeDef;
-
-/** 
-  * @brief  CRYP handle Structure definition  
-  */ 
-typedef struct
-{
-  AES_TypeDef                 *Instance;        /*!< Register base address        */
-
-  CRYP_InitTypeDef            Init;             /*!< CRYP required parameters */
-
-  uint8_t                     *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  uint8_t                     *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  __IO uint16_t               CrypInCount;      /*!< Counter of inputed data */
-
-  __IO uint16_t               CrypOutCount;     /*!< Counter of outputed data */
-
-  HAL_StatusTypeDef           Status;           /*!< CRYP peripheral status */
-
-  HAL_PhaseTypeDef            Phase;            /*!< CRYP peripheral phase */
-
-  DMA_HandleTypeDef           *hdmain;          /*!< CRYP In DMA handle parameters */
-
-  DMA_HandleTypeDef           *hdmaout;         /*!< CRYP Out DMA handle parameters */
-
-  HAL_LockTypeDef             Lock;             /*!< CRYP locking object */
-
-  __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
-
-}CRYP_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
-  * @{
-  */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
-  * @{
-  */
-#define CRYP_DATATYPE_32B         (0x00000000U)
-#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B          AES_CR_DATATYPE
-
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
-                                    ((DATATYPE) == CRYP_DATATYPE_1B))  
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction
-  * @{
-  */ 
-#define CRYP_CR_ALGOMODE_DIRECTION              (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
-
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        (0x00000000U)
-#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT  (AES_CR_MODE)
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT        (AES_CR_CHMOD_0)
-#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT  ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT        (AES_CR_CHMOD_1)
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT        ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1))
-/**
-  * @}
-  */
-  
-/** @defgroup CRYP_AES_Interrupts AES Interrupts
-  * @{
-  */ 
-#define CRYP_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
-#define CRYP_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CRYP_AES_Flags AES Flags
-  * @{
-  */ 
-#define CRYP_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
-#define CRYP_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
-#define CRYP_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags
-  * @{
-  */ 
-#define CRYP_CLEARFLAG_CCF                       AES_CR_CCFC   /*!< Computation Complete Flag Clear */
-#define CRYP_CLEARFLAG_RDERR                     AES_CR_ERRC   /*!< Read Error Clear           */
-#define CRYP_CLEARFLAG_WRERR                     AES_CR_ERRC   /*!< Write Error Clear          */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRYP handle state
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
-  * @brief  Enable/Disable the CRYP peripheral.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
-#define __HAL_CRYP_DISABLE(__HANDLE__)                  CLEAR_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
-
-/**
-  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __MODE__ The algorithm mode.
-  * @retval None
-  */
-#define __HAL_CRYP_SET_MODE(__HANDLE__,__MODE__)        SET_BIT((__HANDLE__)->Instance->CR, (__MODE__))
-
-
-/** @brief  Check whether the specified CRYP flag is set or not.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_FLAG_CCF   : Computation Complete Flag
-  *            @arg CRYP_FLAG_RDERR : Read Error Flag
-  *            @arg CRYP_FLAG_WRERR : Write Error Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CRYP_GET_FLAG(__HANDLE__,__FLAG__)         (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the CRYP pending flag.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__)      SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
-
-/**
-  * @brief  Enable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP Interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__,__INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__,__INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
-
-/** @brief  Checks if the specified CRYP interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param __INTERRUPT__: CRYP interrupt source to check
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_IT_CC   : Computation Complete interrupt
-  *            @arg CRYP_IT_ERR : Error interrupt (used for RDERR and WRERR)
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-    (( ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)       \
-     )? SET : RESET                                         \
-    )
-         
-/** @brief  Clear the CRYP pending IT.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __IT__ specifies the IT to clear.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT((__HANDLE__)->Instance->CR, (__IT__))
-
-/**
-  * @}
-  */
-
-/* Include CRYP HAL Extension module */
-#include "stm32l1xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRYP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef     HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef     HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-
-/* MSP functions  *************************************************************/
-void                  HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group2
-  * @{
-  */
-
-/* AES encryption/decryption using polling  ***********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt  *********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA  ***************************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group3
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void                  HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group4
-  * @{
-  */
-
-/* Processing functions  ********************************************************/
-void                  HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group5
-  * @{
-  */
-
-/* Peripheral State functions  **************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h
deleted file mode 100644
index 7034776b2e4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYPEx HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CRYP_EX_H
-#define __STM32L1xx_HAL_CRYP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRYPEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRYPEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h
deleted file mode 100644
index 0db67296f49..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_DAC_H
-#define STM32L1xx_HAL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-#if defined(DAC1)
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
-
-} HAL_DAC_StateTypeDef;
-
-/**
-  * @brief  DAC handle Structure definition
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
-
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
-
-  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
-
-
-  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback)              (struct __DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-} DAC_HandleTypeDef;
-
-/**
-  * @brief   DAC Configuration regular Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
-                                              This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                               This parameter can be a value of @ref DAC_output_buffer */
-
-} DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL DAC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
-  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
-  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
-  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
-
-  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
-  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
-  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
-  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
-
-  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
-  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
-  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
-} HAL_DAC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL DAC Callback pointer definition
-  */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
-  * @{
-  */
-#define DAC_TRIGGER_NONE                0x00000000UL                                                     /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO             (DAC_CR_TEN1)                                                    /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T9_TRGO             (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO             (DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO             (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE            (DAC_CR_TSEL1                                     | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE           (DAC_CR_BOFF1)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      0x00000000U
-
-#define DAC_CHANNEL_2                      0x00000010U
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment DAC data alignment
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    0x00000000U
-#define DAC_ALIGN_12B_L                    0x00000004U
-#define DAC_ALIGN_8B_R                     0x00000008U
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */
-#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
-
-#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition  DAC IT definition
-  * @{
-  */
-#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
-
-#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @retval None
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
-                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
-                                                     } while(0)
-#else
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __DAC_Channel__ specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Disable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __DAC_Channel__ specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Set DHR12R1 alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
-
-
-/** @brief  Set DHR12R2 alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
-
-
-/** @brief  Set DHR12RD alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Check whether the specified DAC interrupt source is enabled or not.
-  * @param __HANDLE__ DAC handle
-  * @param __INTERRUPT__ DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
-                                                             & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to get.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-
-/**
-  * @}
-  */
-
-/* Include DAC HAL Extended module */
-#include "stm32l1xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                    uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
-                                               pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h
deleted file mode 100644
index 22f55390746..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_DAC_EX_H
-#define STM32L1xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-#if defined(DAC1)
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL State structures definition
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
-  * @{
-  */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-
-HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Private_Functions
-  * @{
-  */
-
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h
deleted file mode 100644
index 57728e72c3c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_def.h
-  * @author  MCD Application Team
-  * @brief   This file contains HAL common defines, enumeration, macros and
-  *          structures definitions.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DEF
-#define __STM32L1xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include <stddef.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL Status structures definition
-  */
-typedef enum
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
-
-/**
-  * @brief  HAL Lock structures definition
-  */
-typedef enum
-{
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)           \
-                        do{                                                  \
-                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
-                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \
-                          } while(0)
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose:
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1)
-
-  /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
-
-#else
-  #define __HAL_LOCK(__HANDLE__)                                               \
-                                do{                                            \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)       \
-                                    {                                          \
-                                       return HAL_BUSY;                        \
-                                    }                                          \
-                                    else                                       \
-                                    {                                          \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;        \
-                                    }                                          \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                             \
-                                  do{                                          \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;       \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
-  * @brief  __RAM_FUNC definition
-  */
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options.
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC  __attribute__((section(".RamFunc")))
-
-#endif
-
-/**
-  * @brief  __NOINLINE definition
-  */
-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
-/* ARM & GNUCompiler
-   ----------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32L1xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h
deleted file mode 100644
index 2baafbcea0b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_DMA_H
-#define STM32L1xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-
-/**
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
-                                           from memory to memory or from peripheral to memory.
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
-                                           This parameter can be a value of @ref DMA_Memory_data_size */
-
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_mode
-                                           @note The circular buffer mode cannot be used if the memory-to-memory
-                                                 data transfer is configured on the selected Channel */
-
-  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
-}HAL_DMA_StateTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-
-/**
-  * @brief  HAL DMA Callback ID structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Channel_TypeDef    *Instance;                                                     /*!< Register base address                */
-
-  DMA_InitTypeDef       Init;                                                           /*!< DMA communication parameters         */
-
-  HAL_LockTypeDef       Lock;                                                           /*!< DMA locking object                   */
-
-  __IO HAL_DMA_StateTypeDef  State;                                                     /*!< DMA transfer state                   */
-
-  void                  *Parent;                                                        /*!< Parent object state                  */
-
-  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer complete callback       */
-
-  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA Half transfer complete callback  */
-
-  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer error callback          */
-
-  void                  (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer abort callback          */
-
-  __IO uint32_t         ErrorCode;                                                      /*!< DMA Error code                       */
-
-  DMA_TypeDef           *DmaBaseAddress;                                                /*!< DMA Channel Base Address             */
-
-  uint32_t              ChannelIndex;                                                   /*!< DMA Channel Index                    */
-
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @{
-  */
-#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */
-#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */
-#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */
-#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */
-#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @{
-  */
-#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @{
-  */
-#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @{
-  */
-#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @{
-  */
-#define DMA_PDATAALIGN_BYTE          0x00000000U       /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0   /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1   /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{
-  */
-#define DMA_MDATAALIGN_BYTE          0x00000000U       /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0   /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1   /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @{
-  */
-#define DMA_NORMAL                0x00000000U                /*!< Normal mode                                    */
-#define DMA_CIRCULAR              DMA_CCR_CIRC               /*!< Circular mode                                  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0    /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1    /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL      /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @{
-  */
-#define DMA_IT_TC                         DMA_CCR_TCIE
-#define DMA_IT_HT                         DMA_CCR_HTIE
-#define DMA_IT_TE                         DMA_CCR_TEIE
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @{
-  */
-#define DMA_FLAG_GL1                      DMA_ISR_GIF1
-#define DMA_FLAG_TC1                      DMA_ISR_TCIF1
-#define DMA_FLAG_HT1                      DMA_ISR_HTIF1
-#define DMA_FLAG_TE1                      DMA_ISR_TEIF1
-#define DMA_FLAG_GL2                      DMA_ISR_GIF2
-#define DMA_FLAG_TC2                      DMA_ISR_TCIF2
-#define DMA_FLAG_HT2                      DMA_ISR_HTIF2
-#define DMA_FLAG_TE2                      DMA_ISR_TEIF2
-#define DMA_FLAG_GL3                      DMA_ISR_GIF3
-#define DMA_FLAG_TC3                      DMA_ISR_TCIF3
-#define DMA_FLAG_HT3                      DMA_ISR_HTIF3
-#define DMA_FLAG_TE3                      DMA_ISR_TEIF3
-#define DMA_FLAG_GL4                      DMA_ISR_GIF4
-#define DMA_FLAG_TC4                      DMA_ISR_TCIF4
-#define DMA_FLAG_HT4                      DMA_ISR_HTIF4
-#define DMA_FLAG_TE4                      DMA_ISR_TEIF4
-#define DMA_FLAG_GL5                      DMA_ISR_GIF5
-#define DMA_FLAG_TC5                      DMA_ISR_TCIF5
-#define DMA_FLAG_HT5                      DMA_ISR_HTIF5
-#define DMA_FLAG_TE5                      DMA_ISR_TEIF5
-#define DMA_FLAG_GL6                      DMA_ISR_GIF6
-#define DMA_FLAG_TC6                      DMA_ISR_TCIF6
-#define DMA_FLAG_HT6                      DMA_ISR_HTIF6
-#define DMA_FLAG_TE6                      DMA_ISR_TEIF6
-#define DMA_FLAG_GL7                      DMA_ISR_GIF7
-#define DMA_FLAG_TC7                      DMA_ISR_TCIF7
-#define DMA_FLAG_HT7                      DMA_ISR_HTIF7
-#define DMA_FLAG_TE7                      DMA_ISR_TEIF7
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
-
-
-/* Interrupt & Flag management */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-/**
-  * @brief  Return the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Return the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Return the current DMA Channel transfer error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
-   DMA_ISR_GIF7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx: Transfer complete flag
-  *            @arg DMA_FLAG_HTx: Half transfer complete flag
-  *            @arg DMA_FLAG_TEx: Transfer error flag
-  *            @arg DMA_FLAG_GLx: Global interrupt flag
-  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *            @arg DMA_FLAG_GLx: Global interrupt flag
-    *         Where x can be from 1 to 7 to select the DMA Channel x flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
-(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
-
-#else
-/**
-  * @brief  Return the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Return the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Return the current DMA Channel transfer error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
-   DMA_ISR_GIF7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
-  *            @arg DMA_ISR_GIFx:    Global interrupt flag
-  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
-
-/**
-  * @brief  Clear the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *            @arg DMA_FLAG_GLx: Global interrupt flag
-  *         Where x can be from 1 to 7 to select the DMA Channel x flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief  Enable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
-  * @param  __HANDLE__ DMA handle
-  * @retval The number of remaining data units in the current DMA Channel transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @{
-  */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
deleted file mode 100644
index d2de5483cf5..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_EXTI_H
-#define STM32L1xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup EXTI EXTI
-  * @brief EXTI HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
-  * @{
-  */
-typedef enum
-{
-  HAL_EXTI_COMMON_CB_ID          = 0x00U
-} EXTI_CallbackIDTypeDef;
-
-/**
-  * @brief  EXTI Handle structure definition
-  */
-typedef struct
-{
-  uint32_t Line;                    /*!<  Exti line number */
-  void (* PendingCallback)(void);   /*!<  Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
-  * @brief  EXTI Configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Line;      /*!< The Exti line to be configured. This parameter
-                           can be a value of @ref EXTI_Line */
-  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
-                           This parameter can be a combination of @ref EXTI_Mode */
-  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
-                           can be a value of @ref EXTI_Trigger */
-  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
-                           This parameter is only possible for line 0 to 15. It
-                           can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_Line  EXTI Line
-  * @{
-  */
-#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
-#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
-#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
-#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
-#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
-#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
-#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
-#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
-#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
-#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
-#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
-#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
-#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
-#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
-#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
-#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
-#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_LINE_18                       (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */
-#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the Comparator 1 output */
-#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the Comparator 2 output */
-#if defined(EXTI_IMR_IM23)
-#define EXTI_LINE_23                       (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the channel acquisition interrupt */
-#endif /* EXTI_IMR_IM23 */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Mode  EXTI Mode
-  * @{
-  */
-#define EXTI_MODE_NONE                      0x00000000u
-#define EXTI_MODE_INTERRUPT                 0x00000001u
-#define EXTI_MODE_EVENT                     0x00000002u
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Trigger  EXTI Trigger
-  * @{
-  */
-
-#define EXTI_TRIGGER_NONE                   0x00000000u
-#define EXTI_TRIGGER_RISING                 0x00000001u
-#define EXTI_TRIGGER_FALLING                0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
-  * @brief
-  * @{
-  */
-#define EXTI_GPIOA                          0x00000000u
-#define EXTI_GPIOB                          0x00000001u
-#define EXTI_GPIOC                          0x00000002u
-#define EXTI_GPIOD                          0x00000003u
-#if defined (GPIOE)
-#define EXTI_GPIOE                          0x00000004u
-#endif /* GPIOE */
-#if defined (GPIOF)
-#define EXTI_GPIOF                          0x00000005u
-#endif /* GPIOF */
-#if defined (GPIOG)
-#define EXTI_GPIOG                          0x00000006u
-#endif /* GPIOG */
-#define EXTI_GPIOH                          0x00000007u
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-/**
-  * @brief  EXTI Line property definition
-  */
-#define EXTI_PROPERTY_SHIFT                  24u
-#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)
-
-/**
-  * @brief  EXTI bit usage
-  */
-#define EXTI_PIN_MASK                       0x0000001Fu
-
-/**
-  * @brief  EXTI Mask for interrupt & event mode
-  */
-#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
-  * @brief  EXTI Mask for trigger possibilities
-  */
-#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
-  * @brief  EXTI Line number
-  */
-#if defined(EXTI_IMR_IM23)
-#define EXTI_LINE_NB                        24UL
-#else
-#define EXTI_LINE_NB                        23UL
-#endif /* EXTI_IMR_IM23 */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
-  * @{
-  */
-#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
-                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \
-                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \
-                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-
-#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
-                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#if !defined (GPIOE)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOF)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#else
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOF) || \
-                                         ((__PORT__) == EXTI_GPIOG) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#endif /* GPIOE */
-
-#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
-  * @brief    EXTI Exported Functions
-  * @{
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
-  * @brief    Configuration functions
-  * @{
-  */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32l1xx_HAL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h
deleted file mode 100644
index adf109cd673..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash.h
-  * @author  MCD Application Team
-  * @brief   Header file of Flash HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_FLASH_H
-#define __STM32L1xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-   
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-  
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE      (50000U) /* 50 s */
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEPROGRAM(_VALUE_)   ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
-
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
-                                       ((__LATENCY__) == FLASH_LATENCY_1))
-
-/**
-  * @}
-  */  
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */  
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE              = 0U, 
-  FLASH_PROC_PAGEERASE         = 1U,
-  FLASH_PROC_PROGRAM           = 2U,
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-  
-  __IO uint32_t               NbPagesToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context*/
-
-  __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
-
-  __IO uint32_t               Page;             /*!< Internal variable to define the current page which is erasing */
-
-  HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
-
-  __IO uint32_t               ErrorCode;        /*!< FLASH error code                    
-                                                     This parameter can be a value of @ref FLASH_Error_Codes  */
-} FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */  
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
-  * @{
-  */
-
-#define HAL_FLASH_ERROR_NONE      0x00U  /*!< No error */
-#define HAL_FLASH_ERROR_PGA       0x01U  /*!< Programming alignment error */
-#define HAL_FLASH_ERROR_WRP       0x02U  /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV      0x04U  /*!< Option validity error */
-#define HAL_FLASH_ERROR_SIZE      0x08U  /*!<  */
-#define HAL_FLASH_ERROR_RD        0x10U  /*!< Read protected error */
-#define HAL_FLASH_ERROR_OPTVUSR   0x20U  /*!< Option UserValidity Error. */
-#define HAL_FLASH_ERROR_OPERATION 0x40U  /*!< Not used */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Page_Size FLASH size information
-  * @{
-  */ 
-
-#if defined (FLASH_CUT1) || defined (FLASH_CUT2)
-#define FLASH_SIZE                      (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFU) * 1024U)
-#else /*FLASH_CUT3 || FLASH_CUT4 || FLASH_CUT5 || FLASH_CUT6*/
-#define FLASH_SIZE                      (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U)
-#endif
-#define FLASH_PAGE_SIZE           (256U)  /*!< FLASH Page Size in bytes */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */ 
-#define FLASH_TYPEPROGRAM_WORD       (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */ 
-#define FLASH_LATENCY_0            (0x00000000U)    /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1            FLASH_ACR_LATENCY         /*!< FLASH One Latency cycle */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupts FLASH Interrupts 
-  * @{
-  */
-
-#define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
-#define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Flags FLASH Flags 
-  * @{
-  */ 
-
-#define FLASH_FLAG_BSY             FLASH_SR_BSY        /*!< FLASH Busy flag */
-#define FLASH_FLAG_EOP             FLASH_SR_EOP        /*!< FLASH End of Programming flag */
-#define FLASH_FLAG_ENDHV           FLASH_SR_ENDHV      /*!< FLASH End of High Voltage flag */
-#define FLASH_FLAG_READY           FLASH_SR_READY      /*!< FLASH Ready flag after low power mode */
-#define FLASH_FLAG_WRPERR          FLASH_SR_WRPERR     /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR          FLASH_SR_PGAERR     /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_SIZERR          FLASH_SR_SIZERR     /*!< FLASH Size error flag  */
-#define FLASH_FLAG_OPTVERR         FLASH_SR_OPTVERR    /*!< FLASH Option Validity error flag  */
-/* Cat2 & Cat3*/
-#if defined(FLASH_SR_RDERR)
-#define FLASH_FLAG_RDERR           FLASH_SR_RDERR    /*!< Read protected error flag  */
-#endif /* FLASH_SR_RDERR */
-/* Cat3, Cat4 & Cat5*/
-#if defined(FLASH_SR_OPTVERRUSR)
-#define FLASH_FLAG_OPTVERRUSR      FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag  */
-#endif /* FLASH_SR_OPTVERRUSR */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys FLASH Keys 
-  * @{
-  */ 
-
-#define FLASH_PDKEY1               (0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2               (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
-                                                              to unlock the RUN_PD bit in FLASH_ACR */
-
-#define FLASH_PEKEY1               (0x89ABCDEFU) /*!< Flash program erase key1 */
-#define FLASH_PEKEY2               (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
-                                                               to unlock the write access to the FLASH_PECR register and
-                                                               data EEPROM */
-
-#define FLASH_PRGKEY1              (0x8C9DAEBFU) /*!< Flash program memory key1 */
-#define FLASH_PRGKEY2              (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
-                                                               to unlock the program memory */
-
-#define FLASH_OPTKEY1              (0xFBEAD9C8U) /*!< Flash option key1 */
-#define FLASH_OPTKEY2              (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
-                                                              unlock the write access to the option byte block */
-/**
-  * @}
-  */
-/**
-  * @}
-  */  
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features 
- *  @{
- */
- 
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts
- *  @brief macros to handle FLASH interrupts
- * @{
- */ 
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  SET_BIT((FLASH->PECR), (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__ specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_FLAG_BSY         FLASH Busy flag
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_ENDHV       FLASH End of High Voltage flag
-  *            @arg @ref FLASH_FLAG_READY       FLASH Ready flag after low power mode
-  *            @arg @ref FLASH_FLAG_PGAERR      FLASH Programming Alignment error flag
-  *            @arg @ref FLASH_FLAG_SIZERR      FLASH Size error flag
-  *            @arg @ref FLASH_FLAG_OPTVERR     FLASH Option validity error error flag
-@if STM32L100xB
-@elif STM32L100xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L151xB
-@elif STM32L151xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L152xB
-@elif STM32L152xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L100xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L151xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L152xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L162xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@else
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@endif
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag 
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_PGAERR      FLASH Programming Alignment error flag
-  *            @arg @ref FLASH_FLAG_SIZERR      FLASH Size error flag
-  *            @arg @ref FLASH_FLAG_OPTVERR     FLASH Option validity error error flag
-@if STM32L100xB
-@elif STM32L100xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L151xB
-@elif STM32L151xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L152xB
-@elif STM32L152xBA
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-@elif STM32L100xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L151xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L152xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@elif STM32L162xC
-  *            @arg @ref FLASH_FLAG_RDERR       FLASH Read Protection error flag (PCROP)
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@else
-  *            @arg @ref FLASH_FLAG_OPTVERRUSR  FLASH Option User validity error
-@endif
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag 
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   ((FLASH->SR) = (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Include FLASH HAL Extended module */
-#include "stm32l1xx_hal_flash_ex.h"  
-#include "stm32l1xx_hal_flash_ramfunc.h"  
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-
-/* FLASH IRQ handler function */
-void       HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
-void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_FLASH_GetError(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function -------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h
deleted file mode 100644
index 0d5cd2a0e84..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h
+++ /dev/null
@@ -1,968 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of Flash HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_FLASH_EX_H
-#define __STM32L1xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */
-#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
-
-#elif defined(FLASH_SR_RDERR)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_RDERR)
-
-#elif defined(FLASH_SR_OPTVERRUSR)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_OPTVERRUSR)
-
-#else
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
-
-#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
-
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
- || defined(STM32L151xBA) || defined(STM32L152xBA)
-     
-/******* Devices with FLASH 128K *******/
-#define FLASH_NBPAGES_MAX       512U /* 512 pages from page 0 to page 511U */
-
-#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
-   || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
-
-/******* Devices with FLASH 256K *******/
-#define FLASH_NBPAGES_MAX       1025U /* 1025 pages from page 0 to page 1024U */
-
-#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
-   || defined(STM32L162xD) || defined(STM32L162xDX)
-
-/******* Devices with FLASH 384K *******/
-#define FLASH_NBPAGES_MAX       1536U /* 1536 pages from page 0 to page 1535U */
-
-#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-
-/******* Devices with FLASH 512K *******/
-#define FLASH_NBPAGES_MAX       2048U /* 2048 pages from page 0 to page 2047U */
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-#define WRP_MASK_LOW                 (0x0000FFFFU)
-#define WRP_MASK_HIGH                (0xFFFF0000U)
-
-/**
-  * @}
-  */  
-
-/** @addtogroup FLASHEx_Private_Macros
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(__VALUE__)   (((__VALUE__) == FLASH_TYPEERASE_PAGES))
-
-#define IS_OPTIONBYTE(__VALUE__)        (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
-#define IS_WRPSTATE(__VALUE__)          (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
-                                         ((__VALUE__) == OB_WRPSTATE_ENABLE))
-                                         
-#define IS_OB_WRP(__PAGE__)             (((__PAGE__) != 0x0000000U))
-
-#define IS_OB_RDP(__LEVEL__)            (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
-                                         ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
-                                         ((__LEVEL__) == OB_RDP_LEVEL_2))
-                                         
-#define IS_OB_BOR_LEVEL(__LEVEL__)      (((__LEVEL__) == OB_BOR_OFF)     || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL1)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL2)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL3)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL4)  || \
-                                         ((__LEVEL__) == OB_BOR_LEVEL5))
-
-#define IS_OB_IWDG_SOURCE(__SOURCE__)   (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(__SOURCE__)   (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(__SOURCE__)  (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
-
-#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
-    
-#define IS_OBEX(__VALUE__)              (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
-
-#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
-
-#define IS_OBEX(__VALUE__)              ((__VALUE__) == OPTIONBYTE_PCROP)
-
-#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
-
-#define IS_OBEX(__VALUE__)              ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
-
-#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
-
-#if defined(FLASH_OBR_SPRMOD)
-
-#define IS_PCROPSTATE(__VALUE__)        (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
-                                         ((__VALUE__) == OB_PCROP_STATE_ENABLE))  
-
-#define IS_OB_PCROP(__PAGE__)           (((__PAGE__) != 0x0000000U))
-#endif /* FLASH_OBR_SPRMOD */
-
-#if defined(FLASH_OBR_nRST_BFB2)
-    
-#define IS_OB_BOOT_BANK(__BANK__)     (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
-
-#endif /* FLASH_OBR_nRST_BFB2 */
-
-#define IS_TYPEERASEDATA(__VALUE__)     (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
-                                         ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
-                                         ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
-#define IS_TYPEPROGRAMDATA(__VALUE__)   (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
-                                         ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
-
-
-/** @defgroup FLASHEx_Address FLASHEx Address
-  * @{
-  */
-
-#define IS_FLASH_DATA_ADDRESS(__ADDRESS__)          (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
-
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA)  \
- || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
- || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
- || defined(STM32L162xCA)
-
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))  
-
-#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))  
-#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))  
-#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))  
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
-
-#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
-  * @{
-  */  
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< TypeErase: Page Erase only.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-  uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
-                             This parameter must be a value belonging to FLASH Programm address (depending on the devices)  */
-  
-  uint32_t NbPages;     /*!< NbPages: Number of pages to be erased.
-                             This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
-  
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes PROGRAM structure definition
-  */
-typedef struct
-{
-  uint32_t  OptionType;       /*!< OptionType: Option byte to be configured.
-                                   This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t  WRPState;         /*!< WRPState: Write protection activation or deactivation.
-                                   This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t  WRPSector0To31;   /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */  
-  
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-  uint32_t  WRPSector32To63;  /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */  
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-  uint32_t  WRPSector64To95;  /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-  uint32_t  WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
-                                   Sectors 96 to 111 for STM32L1xxxDX devices.
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */  
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
-                              
-  uint8_t   RDPLevel;         /*!< RDPLevel: Set the read protection level.
-                                   This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint8_t   BORLevel;         /*!< BORLevel: Set the BOR Level.
-                                   This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
-                                
-  uint8_t   USERConfig;       /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-                                   This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, 
-                                   @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
-} FLASH_OBProgramInitTypeDef;
-
-#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
-/**
-  * @brief  FLASH Advanced Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;          /*!< OptionType: Option byte to be configured for extension .
-                                     This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
-
-#if defined(FLASH_OBR_SPRMOD)
-  uint32_t PCROPState;          /*!< PCROPState: PCROP activation or deactivation.
-                                     This parameter can be a value of @ref FLASHEx_PCROP_State */
-
-  uint32_t  PCROPSector0To31;   /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
-                                     This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
-  
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
-  uint32_t  PCROPSector32To63;  /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
-                                     This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
-#endif /* FLASH_OBR_SPRMOD */
- 
-#if defined(FLASH_OBR_nRST_BFB2)
-  uint16_t BootConfig;          /*!< BootConfig: specifies Option bytes for boot config
-                                     This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
-#endif /* FLASH_OBR_nRST_BFB2*/
-} FLASH_AdvOBProgramInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
-  * @{
-  */  
-
-/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
-  * @{
-  */
-#define FLASH_TYPEERASE_PAGES           (0x00U)  /*!<Page erase only*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
-  * @{
-  */
-#define OPTIONBYTE_WRP            (0x01U)  /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP            (0x02U)  /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER           (0x04U)  /*!<USER option byte configuration*/
-#define OPTIONBYTE_BOR            (0x08U)  /*!<BOR option byte configuration*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
-  * @{
-  */
-#define OB_WRPSTATE_DISABLE        (0x00U)  /*!<Disable the write protection of the desired sectors*/
-#define OB_WRPSTATE_ENABLE         (0x01U)  /*!<Enable the write protection of the desired sectors*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
-  * @{
-  */
-  
-/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_WRP1_PAGES0TO15    (0x00000001U) /* Write protection of Sector0 */  
-#define OB_WRP1_PAGES16TO31   (0x00000002U) /* Write protection of Sector1 */  
-#define OB_WRP1_PAGES32TO47   (0x00000004U) /* Write protection of Sector2 */  
-#define OB_WRP1_PAGES48TO63   (0x00000008U) /* Write protection of Sector3 */  
-#define OB_WRP1_PAGES64TO79   (0x00000010U) /* Write protection of Sector4 */  
-#define OB_WRP1_PAGES80TO95   (0x00000020U) /* Write protection of Sector5 */  
-#define OB_WRP1_PAGES96TO111  (0x00000040U) /* Write protection of Sector6 */  
-#define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */  
-#define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */  
-#define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */  
-#define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */ 
-#define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */ 
-#define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */ 
-#define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */ 
-#define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */ 
-#define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */ 
-#define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */ 
-#define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */ 
-#define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */ 
-#define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */ 
-#define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */ 
-#define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */ 
-#define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */ 
-#define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */ 
-#define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */ 
-#define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */ 
-#define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */ 
-#define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */ 
-#define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */ 
-#define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */ 
-#define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */ 
-#define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */ 
-  
-#define OB_WRP1_ALLPAGES      ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
-  
-/**
-  * @}
-  */ 
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
-  * @{
-  */
-  
-/* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_WRP2_PAGES512TO527   (0x00000001U) /* Write protection of Sector32 */  
-#define OB_WRP2_PAGES528TO543   (0x00000002U) /* Write protection of Sector33 */  
-#define OB_WRP2_PAGES544TO559   (0x00000004U) /* Write protection of Sector34 */  
-#define OB_WRP2_PAGES560TO575   (0x00000008U) /* Write protection of Sector35 */  
-#define OB_WRP2_PAGES576TO591   (0x00000010U) /* Write protection of Sector36 */  
-#define OB_WRP2_PAGES592TO607   (0x00000020U) /* Write protection of Sector37 */  
-#define OB_WRP2_PAGES608TO623   (0x00000040U) /* Write protection of Sector38 */  
-#define OB_WRP2_PAGES624TO639   (0x00000080U) /* Write protection of Sector39 */  
-#define OB_WRP2_PAGES640TO655   (0x00000100U) /* Write protection of Sector40 */  
-#define OB_WRP2_PAGES656TO671   (0x00000200U) /* Write protection of Sector41 */  
-#define OB_WRP2_PAGES672TO687   (0x00000400U) /* Write protection of Sector42 */  
-#define OB_WRP2_PAGES688TO703   (0x00000800U) /* Write protection of Sector43 */  
-#define OB_WRP2_PAGES704TO719   (0x00001000U) /* Write protection of Sector44 */  
-#define OB_WRP2_PAGES720TO735   (0x00002000U) /* Write protection of Sector45 */  
-#define OB_WRP2_PAGES736TO751   (0x00004000U) /* Write protection of Sector46 */  
-#define OB_WRP2_PAGES752TO767   (0x00008000U) /* Write protection of Sector47 */  
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)   \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-
-#define OB_WRP2_PAGES768TO783   (0x00010000U) /* Write protection of Sector48 */  
-#define OB_WRP2_PAGES784TO799   (0x00020000U) /* Write protection of Sector49 */  
-#define OB_WRP2_PAGES800TO815   (0x00040000U) /* Write protection of Sector50 */  
-#define OB_WRP2_PAGES816TO831   (0x00080000U) /* Write protection of Sector51 */  
-#define OB_WRP2_PAGES832TO847   (0x00100000U) /* Write protection of Sector52 */  
-#define OB_WRP2_PAGES848TO863   (0x00200000U) /* Write protection of Sector53 */  
-#define OB_WRP2_PAGES864TO879   (0x00400000U) /* Write protection of Sector54 */  
-#define OB_WRP2_PAGES880TO895   (0x00800000U) /* Write protection of Sector55 */  
-#define OB_WRP2_PAGES896TO911   (0x01000000U) /* Write protection of Sector56 */  
-#define OB_WRP2_PAGES912TO927   (0x02000000U) /* Write protection of Sector57 */  
-#define OB_WRP2_PAGES928TO943   (0x04000000U) /* Write protection of Sector58 */  
-#define OB_WRP2_PAGES944TO959   (0x08000000U) /* Write protection of Sector59 */  
-#define OB_WRP2_PAGES960TO975   (0x10000000U) /* Write protection of Sector60 */  
-#define OB_WRP2_PAGES976TO991   (0x20000000U) /* Write protection of Sector61 */  
-#define OB_WRP2_PAGES992TO1007  (0x40000000U) /* Write protection of Sector62 */
-#define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-      
-#define OB_WRP2_ALLPAGES        ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
-  * @{
-  */
-  
-/* Pages for devices with FLASH >= 256KB*/
-#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */
-#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */
-#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */
-#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */
-#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */
-#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */
-#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */
-#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */
-#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */
-#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */
-#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */
-#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */
-#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */
-#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */
-#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */
-#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */
-#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */
-#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */
-#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */
-#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */
-#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */
-#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */
-#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */
-#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */
-#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */
-#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */
-#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */
-#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */
-#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */
-#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */
-#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */
-#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */
-
-#define OB_WRP3_ALLPAGES        ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
-  * @{
-  */
-  
-/* Pages for Cat5 devices*/
-#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/   
-#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/   
-#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/   
-#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/   
-#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ 
-#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ 
-#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ 
-#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ 
-#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ 
-#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ 
-#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ 
-#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ 
-#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ 
-#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ 
-#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ 
-#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ 
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-
-#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ 
-#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ 
-#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ 
-#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ 
-#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ 
-#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ 
-#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ 
-#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ 
-#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ 
-#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ 
-#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ 
-#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ 
-#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ 
-#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ 
-#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ 
-#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ 
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-
-#define OB_WRP4_ALLPAGES        ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
-  * @{
-  */ 
-#define OB_RDP_LEVEL_0         ((uint8_t)0xAAU)
-#define OB_RDP_LEVEL_1         ((uint8_t)0xBBU)
-#define OB_RDP_LEVEL_2         ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 
-                                                it is no more possible to go back to level 1 or 0 */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
-  * @{
-  */
-
-#define OB_BOR_OFF       ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD 
-                                              power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
-#define OB_BOR_LEVEL1    ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply    */
-#define OB_BOR_LEVEL2    ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply    */
-#define OB_BOR_LEVEL3    ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply    */
-#define OB_BOR_LEVEL4    ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply  */
-#define OB_BOR_LEVEL5    ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply    */
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
-  * @{
-  */
-
-#define OB_IWDG_SW                     ((uint8_t)0x10U)  /*!< Software WDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00U)  /*!< Hardware WDG selected */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
-  * @{
-  */
-
-#define OB_STOP_NORST                  ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
-  * @{
-  */
-
-#define OB_STDBY_NORST                 ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
-
-/**
-  * @}
-  */
-
-#if defined(FLASH_OBR_SPRMOD)
-    
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */ 
-  
-#define OPTIONBYTE_PCROP        (0x01U)  /*!<PCROP option byte configuration*/
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_OBR_SPRMOD */
-
-#if defined(FLASH_OBR_nRST_BFB2)
-
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */ 
-  
-#define OPTIONBYTE_BOOTCONFIG   (0x02U)  /*!<BOOTConfig option byte configuration*/
-
-/**
-  * @}
-  */
-
-#endif /* FLASH_OBR_nRST_BFB2 */
-
-#if defined(FLASH_OBR_SPRMOD)
-
-/** @defgroup  FLASHEx_PCROP_State FLASHEx PCROP State
-  * @{
-  */
-#define OB_PCROP_STATE_DISABLE        (0x00U)  /*!<Disable PCROP for selected sectors */
-#define OB_PCROP_STATE_ENABLE         (0x01U)  /*!<Enable PCROP for selected sectors */
-    
-/**
-  * @}
-  */
-
-/** @defgroup  FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
-  * @{
-  */
-#define OB_PCROP_DESELECTED     ((uint16_t)0x0000U)            /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PCROP_SELECTED       ((uint16_t)FLASH_OBR_SPRMOD)  /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i   */
-
-/**
-  * @}
-  */
-#endif /* FLASH_OBR_SPRMOD */
-
-#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
- || defined(STM32L162xC)
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
-  * @{
-  */
-  
-/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_PCROP1_PAGES0TO15    (0x00000001U) /* PC Read/Write  protection of Sector0 */  
-#define OB_PCROP1_PAGES16TO31   (0x00000002U) /* PC Read/Write  protection of Sector1 */  
-#define OB_PCROP1_PAGES32TO47   (0x00000004U) /* PC Read/Write  protection of Sector2 */  
-#define OB_PCROP1_PAGES48TO63   (0x00000008U) /* PC Read/Write  protection of Sector3 */  
-#define OB_PCROP1_PAGES64TO79   (0x00000010U) /* PC Read/Write  protection of Sector4 */  
-#define OB_PCROP1_PAGES80TO95   (0x00000020U) /* PC Read/Write  protection of Sector5 */  
-#define OB_PCROP1_PAGES96TO111  (0x00000040U) /* PC Read/Write  protection of Sector6 */  
-#define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write  protection of Sector7 */  
-#define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write  protection of Sector8 */  
-#define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write  protection of Sector9 */  
-#define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write  protection of Sector10 */ 
-#define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write  protection of Sector11 */ 
-#define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write  protection of Sector12 */ 
-#define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write  protection of Sector13 */ 
-#define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write  protection of Sector14 */ 
-#define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write  protection of Sector15 */ 
-#define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write  protection of Sector16 */ 
-#define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write  protection of Sector17 */ 
-#define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write  protection of Sector18 */ 
-#define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write  protection of Sector19 */ 
-#define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write  protection of Sector20 */ 
-#define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write  protection of Sector21 */ 
-#define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write  protection of Sector22 */ 
-#define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write  protection of Sector23 */ 
-#define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write  protection of Sector24 */ 
-#define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write  protection of Sector25 */ 
-#define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write  protection of Sector26 */ 
-#define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write  protection of Sector27 */ 
-#define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write  protection of Sector28 */ 
-#define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write  protection of Sector29 */ 
-#define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write  protection of Sector30 */ 
-#define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write  protection of Sector31 */ 
-  
-#define OB_PCROP1_ALLPAGES      (0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
-  
-/**
-  * @}
-  */ 
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
-
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
-  * @{
-  */
-  
-/* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_PCROP2_PAGES512TO527   (0x00000001U) /* PC Read/Write  protection of Sector32 */  
-#define OB_PCROP2_PAGES528TO543   (0x00000002U) /* PC Read/Write  protection of Sector33 */  
-#define OB_PCROP2_PAGES544TO559   (0x00000004U) /* PC Read/Write  protection of Sector34 */  
-#define OB_PCROP2_PAGES560TO575   (0x00000008U) /* PC Read/Write  protection of Sector35 */  
-#define OB_PCROP2_PAGES576TO591   (0x00000010U) /* PC Read/Write  protection of Sector36 */  
-#define OB_PCROP2_PAGES592TO607   (0x00000020U) /* PC Read/Write  protection of Sector37 */  
-#define OB_PCROP2_PAGES608TO623   (0x00000040U) /* PC Read/Write  protection of Sector38 */  
-#define OB_PCROP2_PAGES624TO639   (0x00000080U) /* PC Read/Write  protection of Sector39 */  
-#define OB_PCROP2_PAGES640TO655   (0x00000100U) /* PC Read/Write  protection of Sector40 */  
-#define OB_PCROP2_PAGES656TO671   (0x00000200U) /* PC Read/Write  protection of Sector41 */  
-#define OB_PCROP2_PAGES672TO687   (0x00000400U) /* PC Read/Write  protection of Sector42 */  
-#define OB_PCROP2_PAGES688TO703   (0x00000800U) /* PC Read/Write  protection of Sector43 */  
-#define OB_PCROP2_PAGES704TO719   (0x00001000U) /* PC Read/Write  protection of Sector44 */  
-#define OB_PCROP2_PAGES720TO735   (0x00002000U) /* PC Read/Write  protection of Sector45 */  
-#define OB_PCROP2_PAGES736TO751   (0x00004000U) /* PC Read/Write  protection of Sector46 */  
-#define OB_PCROP2_PAGES752TO767   (0x00008000U) /* PC Read/Write  protection of Sector47 */  
-#define OB_PCROP2_PAGES768TO783   (0x00010000U) /* PC Read/Write  protection of Sector48 */  
-#define OB_PCROP2_PAGES784TO799   (0x00020000U) /* PC Read/Write  protection of Sector49 */  
-#define OB_PCROP2_PAGES800TO815   (0x00040000U) /* PC Read/Write  protection of Sector50 */  
-#define OB_PCROP2_PAGES816TO831   (0x00080000U) /* PC Read/Write  protection of Sector51 */  
-#define OB_PCROP2_PAGES832TO847   (0x00100000U) /* PC Read/Write  protection of Sector52 */  
-#define OB_PCROP2_PAGES848TO863   (0x00200000U) /* PC Read/Write  protection of Sector53 */  
-#define OB_PCROP2_PAGES864TO879   (0x00400000U) /* PC Read/Write  protection of Sector54 */  
-#define OB_PCROP2_PAGES880TO895   (0x00800000U) /* PC Read/Write  protection of Sector55 */  
-#define OB_PCROP2_PAGES896TO911   (0x01000000U) /* PC Read/Write  protection of Sector56 */  
-#define OB_PCROP2_PAGES912TO927   (0x02000000U) /* PC Read/Write  protection of Sector57 */  
-#define OB_PCROP2_PAGES928TO943   (0x04000000U) /* PC Read/Write  protection of Sector58 */  
-#define OB_PCROP2_PAGES944TO959   (0x08000000U) /* PC Read/Write  protection of Sector59 */  
-#define OB_PCROP2_PAGES960TO975   (0x10000000U) /* PC Read/Write  protection of Sector60 */  
-#define OB_PCROP2_PAGES976TO991   (0x20000000U) /* PC Read/Write  protection of Sector61 */  
-#define OB_PCROP2_PAGES992TO1007  (0x40000000U) /* PC Read/Write  protection of Sector62 */
-#define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write  protection of Sector63 */
-
-#define OB_PCROP2_ALLPAGES        (0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
-
-/**
-  * @}
-  */ 
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
-
-/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
-  * @{
-  */
-#define FLASH_TYPEERASEDATA_BYTE            (0x00U)  /*!<Erase byte (8-bit) at a specified address.*/
-#define FLASH_TYPEERASEDATA_HALFWORD        (0x01U)  /*!<Erase a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEERASEDATA_WORD            (0x02U)  /*!<Erase a word (32-bit) at a specified address.*/
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
-  * @{
-  */
-#define FLASH_TYPEPROGRAMDATA_BYTE            (0x00U)  /*!<Program byte (8-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_HALFWORD        (0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_WORD            (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTBYTE        (0x04U)  /*!<Fast Program byte (8-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD    (0x08U)  /*!<Fast Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTWORD        (0x10U)  /*!<Fast Program a word (32-bit) at a specified address.*/
-
-/**
-  * @}
-  */
-
-#if defined(FLASH_OBR_nRST_BFB2)
-    
-/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
-  * @{
-  */
-
-#define OB_BOOT_BANK2                 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank 2 
-                                                            or Bank 1, depending on the activation of the bank */
-#define OB_BOOT_BANK1                 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank1(Default) */
-
-/**
-  * @}
-  */
-#endif /* FLASH_OBR_nRST_BFB2 */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
- *  @{
- */
- 
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_LATENCY_0  FLASH Zero Latency cycle
-  *            @arg @ref FLASH_LATENCY_1  FLASH One Latency cycle
-  * @retval none
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)  do  { \
-                                                  if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
-                                                  MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
-                                              } while(0U)
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
-  *          This parameter can be one of the following values:
-  *            @arg @ref FLASH_LATENCY_0  FLASH Zero Latency cycle
-  *            @arg @ref FLASH_LATENCY_1  FLASH One Latency cycle
-  */ 
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @brief  Enable the FLASH 64-bit access.
-  * @note    Read access 64 bit is used.
-  * @note    This bit cannot be written at the same time as the LATENCY and 
-  *          PRFTEN bits.
-  * @retval none
-  */ 
-#define __HAL_FLASH_ACC64_ENABLE()    (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
-
-  /**
-  * @brief  Disable the FLASH 64-bit access.
-  * @note     Read access 32 bit is used
-  * @note     To reset this bit, the LATENCY should be zero wait state and the 
-  *               prefetch off.
-  * @retval none
-  */ 
-#define __HAL_FLASH_ACC64_DISABLE()   (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    do  { __HAL_FLASH_ACC64_ENABLE(); \
-                                                  SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
-                                                } while(0U)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()     CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Enable the FLASH power down during Sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()      SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Disable the FLASH power down during Sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()     CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Enable the Flash Run power down mode.
-  * @note   Writing this bit  to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                             FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                           } while (0U)
-
-/**
-  * @brief  Disable the Flash Run power down mode.
-  * @note   Writing this bit to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                              FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                            } while (0U)
-                                            
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
-    
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-
-#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
-
-#if defined(FLASH_OBR_SPRMOD)
-
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-
-#endif /* FLASH_OBR_SPRMOD */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group3
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-void              HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
-void              HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h
deleted file mode 100644
index 49a2f2e562e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_FLASH_RAMFUNC_H
-#define __STM32L1xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
-  * @{
-  */
-
-/*
-  * @brief  FLASH memory functions that should be executed from internal SRAM.
-  *         These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c"
-  *         file.
-  */
-  
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
-  * @{
-  */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
-  * @{
-  */
-
-#if defined(FLASH_PECR_PARALLBANK)
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
-
-#endif /* FLASH_PECR_PARALLBANK */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
-  * @{
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error);
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4
-  * @{
-  */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_FLASH_RAMFUNC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h
deleted file mode 100644
index 4cf5263bd23..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_GPIO_H
-#define __STM32L1xx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-/**
-  * @brief   GPIO Init structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode */
-
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull */
-
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-} GPIO_InitTypeDef;
-
-/**
-  * @brief  GPIO Bit SET and Bit RESET enumeration
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-} GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-
-/** @defgroup GPIO_pins GPIO pins
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
-
-#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode GPIO mode
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0x00WX00YZ
-  *           - W  : EXTI trigger detection on 3 bits
-  *           - X  : EXTI mode (IT or Event) on 2 bits
-  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
-  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
-#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
-#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed GPIO speed
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW       (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM    (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH      (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_pull GPIO pull
-  * @brief GPIO Pull-Up or Pull-Down Activation
-  * @{
-  */
-#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-#define GPIO_MODE_Pos                           0U
-#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
-#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
-#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
-#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
-#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos                         4U
-#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos                           16U
-#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
-#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
-#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos                        20U
-#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
-                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
-                                ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extension module */
-#include "stm32l1xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  *  @brief    GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions
- *  @brief    Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
-  *  @brief    IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h
deleted file mode 100644
index ebddd83d02e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_GPIO_EX_H
-#define __STM32L1xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
-  * @{
-  */
-
-/* AF 0 selection */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping                 */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /*!< TAMPER  Alternate Function mapping             */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD and JTAG) Alternate Function mapping  */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping               */
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /*!< RTC_OUT Alternate Function mapping             */
-
-/* AF 1 selection */
-#define GPIO_AF1_TIM2           ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */
-
-/* AF 2 selection */
-#define GPIO_AF2_TIM3           ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4           ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-#define GPIO_AF2_TIM5           ((uint8_t)0x02)  /*!< TIM5 Alternate Function mapping */
-
-#endif /*  STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */
-
-/* AF 3 selection */
-#define GPIO_AF3_TIM9            ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */
-#define GPIO_AF3_TIM10           ((uint8_t)0x03)  /*!< TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11           ((uint8_t)0x03)  /*!< TIM11 Alternate Function mapping */
-
-
-/* AF 4 selection */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */
-
-/* AF 5 selection */
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1/I2S1 Alternate Function mapping      */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2/I2S2 Alternate Function mapping */
-
-/* AF 6 selection */
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\
-    defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /*!< SPI3/I2S3 Alternate Function mapping */
-
-#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-
-/* AF 7 selection */
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping  */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping  */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping  */
-
-/* AF 8 selection */
-#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\
-    defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
-    defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-#define GPIO_AF8_UART4        ((uint8_t)0x08)  /*!< UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5        ((uint8_t)0x08)  /*!< UART5 Alternate Function mapping  */
-
-#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-
-/* AF 9 selection */
-
-/* AF 10 selection */
-
-/* AF 11 selection */
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-#define GPIO_AF11_LCD            ((uint8_t)0x0B)  /*!< LCD Alternate Function mapping */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-/* AF 12 selection */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-#define GPIO_AF12_FSMC            ((uint8_t)0x0C)  /*!< FSMC Alternate Function mapping */
-#define GPIO_AF12_SDIO            ((uint8_t)0x0C)  /*!< SDIO Alternate Function mapping */
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-/* AF 13 selection */
-
-/* AF 14 selection */
-#define GPIO_AF14_TIM_IC1         ((uint8_t)0x0E)  /*!< TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC2         ((uint8_t)0x0E)  /*!< TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC3         ((uint8_t)0x0E)  /*!< TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC4         ((uint8_t)0x0E)  /*!< TIMER INPUT CAPTURE Alternate Function mapping */
-
-/* AF 15 selection */
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /*!< EVENTOUT Alternate Function mapping */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
-  * @{
-  */
-
-
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
-
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U :\
-                                   ((__GPIOx__) == (GPIOH))? 5U :\
-                                   ((__GPIOx__) == (GPIOF))? 6U : 7U)
-#endif
-
-#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U : 5U)
-#endif
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U : 5U)
-#endif
-
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h
deleted file mode 100644
index 208f2a2b887..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2c.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_I2C_H
-#define __STM32L1xx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
-                                  This parameter must be set to a value lower than 400kHz */
-
-  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
-                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
-  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
-
-  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
-
-  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
-  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
-
-} I2C_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : Abort (Abort user request on going)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
-  *          b4     (not used)
-  *             x  : Should be set to 0
-  *          b3
-  *             0  : Ready or Busy (No Listen mode ongoing)
-  *             1  : Listen (Peripheral in Address Listen Mode)
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-} HAL_I2C_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :\n
-  *          b7     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b6\n
-  *             0  : None\n
-  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
-  *          b5\n
-  *             0  : None\n
-  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
-  *          b4\n
-  *             0  : None\n
-  *             1  : Master (HAL I2C communication is in Master Mode)\n
-  *          b3-b2-b1-b0  (not used)\n
-  *             xxxx : Should be set to 0000
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */
-#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */
-#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */
-#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */
-#define HAL_I2C_WRONG_START             0x00000200U    /*!< Wrong start Error     */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition
-  * @{
-  */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-typedef struct __I2C_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
-{
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
-
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
-
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
-
-  uint16_t                   XferSize;       /*!< I2C transfer size                        */
-
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
-
-  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
-
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
-                                                  context for internal usage               */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
-
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
-
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
-
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
-
-  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
-
-  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
-
-  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
-
-  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
-
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
-
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
-
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL I2C Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
-  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
-  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
-  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
-  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
-  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
-  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
-  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
-  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
-
-  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
-  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
-
-} HAL_I2C_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2C Callback pointer definition
-  */
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
-  * @{
-  */
-#define I2C_DUTYCYCLE_2                 0x00000000U
-#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
-/**
-  * @}
-  */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         0x00004000U
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE        0x00000000U
-#define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
-/**
-  * @}
-  */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE        0x00000000U
-#define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
-/**
-  * @}
-  */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE          0x00000000U
-#define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            0x00000001U
-#define I2C_MEMADD_SIZE_16BIT           0x00000010U
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
-  * @{
-  */
-#define I2C_DIRECTION_RECEIVE           0x00000000U
-#define I2C_DIRECTION_TRANSMIT          0x00000001U
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
-  * @{
-  */
-#define  I2C_FIRST_FRAME                0x00000001U
-#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U
-#define  I2C_NEXT_FRAME                 0x00000004U
-#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U
-#define  I2C_LAST_FRAME_NO_STOP         0x00000010U
-#define  I2C_LAST_FRAME                 0x00000020U
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  I2C_OTHER_FRAME                (0x00AA0000U)
-#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
-#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
-#define I2C_IT_ERR                      I2C_CR2_ITERREN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */
-
-#define I2C_FLAG_OVR                    0x00010800U
-#define I2C_FLAG_AF                     0x00010400U
-#define I2C_FLAG_ARLO                   0x00010200U
-#define I2C_FLAG_BERR                   0x00010100U
-#define I2C_FLAG_TXE                    0x00010080U
-#define I2C_FLAG_RXNE                   0x00010040U
-#define I2C_FLAG_STOPF                  0x00010010U
-#define I2C_FLAG_ADD10                  0x00010008U
-#define I2C_FLAG_BTF                    0x00010004U
-#define I2C_FLAG_ADDR                   0x00010002U
-#define I2C_FLAG_SB                     0x00010001U
-#define I2C_FLAG_DUALF                  0x00100080U
-#define I2C_FLAG_GENCALL                0x00100010U
-#define I2C_FLAG_TRA                    0x00100004U
-#define I2C_FLAG_BUSY                   0x00100002U
-#define I2C_FLAG_MSL                    0x00100001U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
-
-/** @brief  Enable or disable the specified I2C interrupts.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  *            @arg I2C_FLAG_TXE: Data register empty flag
-  *            @arg I2C_FLAG_RXNE: Data register not empty flag
-  *            @arg I2C_FLAG_STOPF: Stop detection flag
-  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
-  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
-  *            @arg I2C_FLAG_ADDR: Address sent flag
-  *                                Address matched flag
-  *            @arg I2C_FLAG_SB: Start bit flag
-  *            @arg I2C_FLAG_DUALF: Dual flag
-  *            @arg I2C_FLAG_GENCALL: General call header flag
-  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
-  *            @arg I2C_FLAG_BUSY: Bus busy flag
-  *            @arg I2C_FLAG_MSL: Master/Slave flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
-                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
-                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
-
-/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
-
-/** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR1;       \
-    tmpreg = (__HANDLE__)->Instance->SR2;       \
-    UNUSED(tmpreg);                             \
-  } while(0)
-
-/** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \
-  do{                                                  \
-    __IO uint32_t tmpreg = 0x00U;                      \
-    tmpreg = (__HANDLE__)->Instance->SR1;              \
-    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \
-    UNUSED(tmpreg);                                    \
-  } while(0)
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions  ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  * @{
-  */
-/* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-#define I2C_FLAG_MASK                    0x0000FFFFU
-#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */
-#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macros I2C Private Macros
-  * @{
-  */
-
-#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
-#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
-#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
-
-/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
-  * @{
-  */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
-                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                   ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
-                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \
-                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
-                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
-                                                       ((REQUEST) == I2C_LAST_FRAME)               || \
-                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \
-                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
-                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h
deleted file mode 100644
index 61a3d0d651a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_i2s.h
+++ /dev/null
@@ -1,561 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_I2S_H
-#define STM32L1xx_HAL_I2S_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/**
-  * @brief I2S Init structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the I2S operating mode.
-                                     This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                     This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
-                                     This parameter can be a value of @ref I2S_Clock_Polarity */
-} I2S_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
-} HAL_I2S_StateTypeDef;
-
-/**
-  * @brief I2S handle Structure definition
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
-typedef struct __I2S_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-{
-  SPI_TypeDef                *Instance;    /*!< I2S registers base address */
-
-  I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
-
-  uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
-
-  __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
-
-  __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
-
-  uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
-
-  __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
-
-  __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
-                                              (This field is initialized at the
-                                               same value as transfer size at the
-                                               beginning of the transfer and
-                                               decremented when a sample is received
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-  DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
-
-  __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
-
-  __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
-
-  __IO uint32_t              ErrorCode;    /*!< I2S Error code
-                                                This parameter can be a value of @ref I2S_Error */
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
-  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
-  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
-  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
-  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
-  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
-
-#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
-} I2S_HandleTypeDef;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL I2S Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
-  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
-  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
-  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
-  HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
-  HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
-  HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
-
-} HAL_I2S_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2S Callback pointer definition
-  */
-typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
-
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-/** @defgroup I2S_Error I2S Error
-  * @{
-  */
-#define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
-#define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
-#define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
-#define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
-#define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
-#define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-#define HAL_I2S_ERROR_BUSY_LINE_RX       (0x00000040U)  /*!< Busy Rx Line error          */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                (0x00000000U)
-#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             (0x00000000U)
-#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               (192000U)
-#define I2S_AUDIOFREQ_96K                (96000U)
-#define I2S_AUDIOFREQ_48K                (48000U)
-#define I2S_AUDIOFREQ_44K                (44100U)
-#define I2S_AUDIOFREQ_32K                (32000U)
-#define I2S_AUDIOFREQ_22K                (22050U)
-#define I2S_AUDIOFREQ_16K                (16000U)
-#define I2S_AUDIOFREQ_11K                (11025U)
-#define I2S_AUDIOFREQ_8K                 (8000U)
-#define I2S_AUDIOFREQ_DEFAULT            (2U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                     (0x00000000U)
-#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
-  * @{
-  */
-#define I2S_IT_TXE                       SPI_CR2_TXEIE
-#define I2S_IT_RXNE                      SPI_CR2_RXNEIE
-#define I2S_IT_ERR                       SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
-  * @{
-  */
-#define I2S_FLAG_TXE                     SPI_SR_TXE
-#define I2S_FLAG_RXNE                    SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                     SPI_SR_UDR
-#define I2S_FLAG_OVR                     SPI_SR_OVR
-#define I2S_FLAG_FRE                     SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                     SPI_SR_BSY
-
-#if defined(SPI_CR2_FRF)
-#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
-                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
-#else
-#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
-                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_CHSIDE | SPI_SR_BSY)
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Disable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
-                                                __IO uint32_t tmpreg_ovr = 0x00U; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
-                                                UNUSED(tmpreg_ovr); \
-                                              }while(0U)
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
-                                                __IO uint32_t tmpreg_udr = 0x00U;\
-                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
-                                                UNUSED(tmpreg_udr); \
-                                              }while(0U)
-/** @brief Flush the I2S DR Register.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__)  do{\
-                                                __IO uint32_t tmpreg_dr = 0x00U;\
-                                                tmpreg_dr = ((__HANDLE__)->Instance->DR);\
-                                                UNUSED(tmpreg_dr); \
-                                              }while(0U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of I2S SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun error flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_CHSIDE: Channel side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
-                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of I2S CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
-                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if I2S Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the I2S Mode.
-  *         This parameter can be a value of @ref I2S_Mode
-  * @retval None
-  */
-#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
-                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
-                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
-                               ((__MODE__) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
-                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
-                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
-                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
-                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
-
-/** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the I2S serial clock steady state.
-  *         This parameter can be a value of @ref I2S_Clock_Polarity
-  * @retval None
-  */
-#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
-                               ((__CPOL__) == I2S_CPOL_HIGH))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h
deleted file mode 100644
index 6aa5a8155a4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_irda.h
+++ /dev/null
@@ -1,684 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_irda.h
-  * @author  MCD Application Team
-  * @brief   Header file of IRDA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_IRDA_H
-#define __STM32L1xx_HAL_IRDA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IRDA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
-  * @{
-  */
-/**
-  * @brief IRDA Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref IRDA_Word_Length */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref IRDA_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref IRDA_Mode */
-
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value to be programmed
-                                           in the IrDA low-power Baud Register, for defining pulse width on which
-                                           burst acceptance/rejection will be decided. This value is used as divisor
-                                           of system clock to achieve required pulse width. */
-
-  uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
-                                           This parameter can be a value of @ref IRDA_Low_Power */
-} IRDA_InitTypeDef;
-
-/**
-  * @brief HAL IRDA State structures definition
-  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains IRDA state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initialisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized. HAL IRDA Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initialisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef enum
-{
-  HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error
-                                                   Value is allowed for gState only */
-} HAL_IRDA_StateTypeDef;
-
-/**
-  * @brief IRDA handle Structure definition
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-typedef struct __IRDA_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-{
-  USART_TypeDef               *Instance;        /*!<  USART registers base address       */
-
-  IRDA_InitTypeDef            Init;             /*!<  IRDA communication parameters      */
-
-  uint8_t                     *pTxBuffPtr;      /*!<  Pointer to IRDA Tx transfer Buffer */
-
-  uint16_t                    TxXferSize;       /*!<  IRDA Tx Transfer size              */
-
-  __IO uint16_t               TxXferCount;      /*!<  IRDA Tx Transfer Counter           */
-
-  uint8_t                     *pRxBuffPtr;      /*!<  Pointer to IRDA Rx transfer Buffer */
-
-  uint16_t                    RxXferSize;       /*!<  IRDA Rx Transfer size              */
-
-  __IO uint16_t               RxXferCount;      /*!<  IRDA Rx Transfer Counter           */
-
-  DMA_HandleTypeDef           *hdmatx;          /*!<  IRDA Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef           *hdmarx;          /*!<  IRDA Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef             Lock;             /*!<  Locking object                     */
-
-  __IO HAL_IRDA_StateTypeDef  gState;           /*!<  IRDA state information related to global Handle management
-                                                   and also related to Tx operations.
-                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO HAL_IRDA_StateTypeDef  RxState;          /*!<  IRDA state information related to Rx operations.
-                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO uint32_t               ErrorCode;        /*!< IRDA Error code                    */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
-
-  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
-
-  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
-
-  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
-
-
-  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-} IRDA_HandleTypeDef;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL IRDA Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
-  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
-  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
-  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
-  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
-  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
-  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
-  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
-
-  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
-  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
-
-} HAL_IRDA_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL IRDA Callback pointer definition
-  */
-typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
-
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
-  * @{
-  */
-/** @defgroup IRDA_Error_Code IRDA Error Code
-  * @{
-  */
-#define HAL_IRDA_ERROR_NONE        0x00000000U   /*!< No error            */
-#define HAL_IRDA_ERROR_PE          0x00000001U   /*!< Parity error        */
-#define HAL_IRDA_ERROR_NE          0x00000002U   /*!< Noise error         */
-#define HAL_IRDA_ERROR_FE          0x00000004U   /*!< Frame error         */
-#define HAL_IRDA_ERROR_ORE         0x00000008U   /*!< Overrun error       */
-#define HAL_IRDA_ERROR_DMA         0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)   /*!< Invalid Callback error  */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
-  * @{
-  */
-#define IRDA_WORDLENGTH_8B         0x00000000U
-#define IRDA_WORDLENGTH_9B         ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Parity  IRDA Parity
-  * @{
-  */
-#define IRDA_PARITY_NONE           0x00000000U
-#define IRDA_PARITY_EVEN           ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD            ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Mode IRDA Transfer Mode
-  * @{
-  */
-#define IRDA_MODE_RX               ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX               ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX            ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
-  * @{
-  */
-#define IRDA_POWERMODE_LOWPOWER    ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL      0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Flags IRDA Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define IRDA_FLAG_TXE              ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC               ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE             ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE             ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE              ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE               ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE               ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE               ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  * @{
-  */
-#define IRDA_IT_PE                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define IRDA_IT_TXE                ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define IRDA_IT_TC                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define IRDA_IT_RXNE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define IRDA_IT_LBD                ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define IRDA_IT_CTS                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define IRDA_IT_ERR                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
-  * @{
-  */
-
-/** @brief Reset IRDA handle gstate & RxState
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the IRDA DR register
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
-  *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
-  *            @arg IRDA_FLAG_ORE:  OverRun Error flag
-  *            @arg IRDA_FLAG_NE:   Noise Error flag
-  *            @arg IRDA_FLAG_FE:   Framing Error flag
-  *            @arg IRDA_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    UNUSED(tmpreg);                             \
-  } while(0U)
-
-/** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-/** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__ specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:  Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_ERR: Error interrupt
-  *            @arg IRDA_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
-
-/** @brief  Macro to enable the IRDA's one bit sample method
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
-
-/** @brief  Macro to disable the IRDA's one bit sample method
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Disable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
-  * @{
-  */
-
-/** @brief IRDA interruptions flag mask
-  *
-  */
-#define IRDA_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                  USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-#define IRDA_CR1_REG_INDEX         1U
-#define IRDA_CR2_REG_INDEX         2U
-#define IRDA_CR3_REG_INDEX         3U
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros   IRDA Private Macros
-  * @{
-  */
-#define IS_IRDA_WORD_LENGTH(LENGTH)   (((LENGTH) == IRDA_WORDLENGTH_8B) || \
-                                       ((LENGTH) == IRDA_WORDLENGTH_9B))
-
-#define IS_IRDA_PARITY(PARITY)        (((PARITY) == IRDA_PARITY_NONE) || \
-                                       ((PARITY) == IRDA_PARITY_EVEN) || \
-                                       ((PARITY) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_MODE(MODE)            ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
-
-#define IS_IRDA_POWERMODE(MODE)       (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
-                                       ((MODE) == IRDA_POWERMODE_NORMAL))
-
-#define IS_IRDA_BAUDRATE(BAUDRATE)    ((BAUDRATE) < 115201U)
-
-#define IRDA_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(4U*(_BAUD_)))
-
-#define IRDA_DIVMANT(_PCLK_, _BAUD_)  (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_)  ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
-
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define IRDA_BRR(_PCLK_, _BAUD_)      (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
-                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
-                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h
deleted file mode 100644
index 9b98faecd03..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_iwdg.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_iwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of IWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_IWDG_H
-#define STM32L1xx_HAL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IWDG IWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  IWDG Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
-                            This parameter can be a value of @ref IWDG_Prescaler */
-
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
-  * @brief  IWDG Handle Structure definition
-  */
-typedef struct
-{
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
-
-  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-} IWDG_HandleTypeDef;
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
-  * @{
-  */
-#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the IWDG peripheral.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
-  * @brief  Reload IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
-  * @{
-  */
-/* Initialization/Start functions  ********************************************/
-HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
-  * @{
-  */
-
-/**
-  * @brief  IWDG Key Register BitMask
-  */
-#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
-  * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
-  * @brief  Check IWDG prescaler value.
-  * @param  __PRESCALER__  IWDG prescaler value
-  * @retval None
-  */
-#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
-  * @brief  Check IWDG reload value.
-  * @param  __RELOAD__  IWDG reload value
-  * @retval None
-  */
-#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h
deleted file mode 100644
index b02afc16e68..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_lcd.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_lcd.h
-  * @author  MCD Application Team
-  * @brief   Header file of LCD Controller HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_LCD_H
-#define __STM32L1xx_HAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup LCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Types LCD Exported Types
-  * @{
-  */
-
-/** 
-  * @brief LCD Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Prescaler;       /*!< Configures the LCD Prescaler. 
-                                 This parameter can be one value of @ref LCD_Prescaler */
-  uint32_t Divider;         /*!< Configures the LCD Divider.
-                                 This parameter can be one value of @ref LCD_Divider */
-  uint32_t Duty;            /*!< Configures the LCD Duty.
-                                 This parameter can be one value of @ref LCD_Duty */
-  uint32_t Bias;            /*!< Configures the LCD Bias.
-                                 This parameter can be one value of @ref LCD_Bias */ 
-  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
-                                 This parameter can be one value of @ref LCD_Voltage_Source */  
-  uint32_t Contrast;        /*!< Configures the LCD Contrast.
-                                 This parameter can be one value of @ref LCD_Contrast */
-  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
-                                 This parameter can be one value of @ref LCD_DeadTime */
-  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
-                                 This parameter can be one value of @ref LCD_PulseOnDuration */
-  uint32_t HighDrive;      /*!< Configures the LCD High Drive.
-                                 This parameter can be one value of @ref LCD_HighDrive */
-  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
-                                 This parameter can be one value of @ref LCD_BlinkMode */
-  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
-                                 This parameter can be one value of @ref LCD_BlinkFrequency */
-  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
-                                 This parameter can be set to ENABLE or DISABLE. */ 
-}LCD_InitTypeDef;
-
-/** 
-  * @brief HAL LCD State structures definition
-  */ 
-typedef enum
-{
-  HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
-  HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_LCD_StateTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition
-  */  
-typedef struct
-{
-  LCD_TypeDef                   *Instance;  /* LCD registers base address */
-  
-  LCD_InitTypeDef               Init;       /* LCD communication parameters */
-
-  HAL_LockTypeDef               Lock;       /* Locking object */
-
-  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
-  
-  __IO uint32_t                 ErrorCode;  /* LCD Error code */
-  
-}LCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Constants LCD Exported Constants
-  * @{
-  */
-
-/** @defgroup LCD_Error_Codes   LCD Error Codes
-  * @{
-  */
-
-#define HAL_LCD_ERROR_NONE      (0x00U)    /*!< No error */
-#define HAL_LCD_ERROR_FCRSF     (0x01U)    /*!< Synchro flag timeout error */
-#define HAL_LCD_ERROR_UDR       (0x02U)    /*!< Update display request flag timeout error */
-#define HAL_LCD_ERROR_UDD       (0x04U)    /*!< Update display done flag timeout error */
-#define HAL_LCD_ERROR_ENS       (0x08U)    /*!< LCD enabled status flag timeout error */
-#define HAL_LCD_ERROR_RDY       (0x10U)    /*!< LCD Booster ready timeout error */
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Prescaler LCD Prescaler
-  * @{
-  */
-
-#define LCD_PRESCALER_1        (0x00000000U)           /*!< CLKPS = LCDCLK        */
-#define LCD_PRESCALER_2        (0x00400000U)           /*!< CLKPS = LCDCLK/2      */
-#define LCD_PRESCALER_4        (0x00800000U)           /*!< CLKPS = LCDCLK/4      */
-#define LCD_PRESCALER_8        (0x00C00000U)           /*!< CLKPS = LCDCLK/8      */
-#define LCD_PRESCALER_16       (0x01000000U)           /*!< CLKPS = LCDCLK/16     */
-#define LCD_PRESCALER_32       (0x01400000U)           /*!< CLKPS = LCDCLK/32     */
-#define LCD_PRESCALER_64       (0x01800000U)           /*!< CLKPS = LCDCLK/64     */
-#define LCD_PRESCALER_128      (0x01C00000U)           /*!< CLKPS = LCDCLK/128    */
-#define LCD_PRESCALER_256      (0x02000000U)           /*!< CLKPS = LCDCLK/256    */
-#define LCD_PRESCALER_512      (0x02400000U)           /*!< CLKPS = LCDCLK/512    */
-#define LCD_PRESCALER_1024     (0x02800000U)           /*!< CLKPS = LCDCLK/1024   */
-#define LCD_PRESCALER_2048     (0x02C00000U)           /*!< CLKPS = LCDCLK/2048   */
-#define LCD_PRESCALER_4096     (0x03000000U)           /*!< CLKPS = LCDCLK/4096   */
-#define LCD_PRESCALER_8192     (0x03400000U)           /*!< CLKPS = LCDCLK/8192   */
-#define LCD_PRESCALER_16384    (0x03800000U)           /*!< CLKPS = LCDCLK/16384  */
-#define LCD_PRESCALER_32768    ((uint32_t)LCD_FCR_PS)  /*!< CLKPS = LCDCLK/32768  */
-
-#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
-
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Divider LCD Divider
-  * @{
-  */
-
-#define LCD_DIVIDER_16    (0x00000000U)           /*!< LCD frequency = CLKPS/16 */
-#define LCD_DIVIDER_17    (0x00040000U)           /*!< LCD frequency = CLKPS/17 */
-#define LCD_DIVIDER_18    (0x00080000U)           /*!< LCD frequency = CLKPS/18 */
-#define LCD_DIVIDER_19    (0x000C0000U)           /*!< LCD frequency = CLKPS/19 */
-#define LCD_DIVIDER_20    (0x00100000U)           /*!< LCD frequency = CLKPS/20 */
-#define LCD_DIVIDER_21    (0x00140000U)           /*!< LCD frequency = CLKPS/21 */
-#define LCD_DIVIDER_22    (0x00180000U)           /*!< LCD frequency = CLKPS/22 */
-#define LCD_DIVIDER_23    (0x001C0000U)           /*!< LCD frequency = CLKPS/23 */
-#define LCD_DIVIDER_24    (0x00200000U)           /*!< LCD frequency = CLKPS/24 */
-#define LCD_DIVIDER_25    (0x00240000U)           /*!< LCD frequency = CLKPS/25 */
-#define LCD_DIVIDER_26    (0x00280000U)           /*!< LCD frequency = CLKPS/26 */
-#define LCD_DIVIDER_27    (0x002C0000U)           /*!< LCD frequency = CLKPS/27 */
-#define LCD_DIVIDER_28    (0x00300000U)           /*!< LCD frequency = CLKPS/28 */
-#define LCD_DIVIDER_29    (0x00340000U)           /*!< LCD frequency = CLKPS/29 */
-#define LCD_DIVIDER_30    (0x00380000U)           /*!< LCD frequency = CLKPS/30 */
-#define LCD_DIVIDER_31    ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
-
-#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_31))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LCD_Duty LCD Duty
-  * @{
-  */
-  
-#define LCD_DUTY_STATIC                 (0x00000000U)                     /*!< Static duty */
-#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
-#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
-#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
-#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
-
-#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
-                               ((__DUTY__) == LCD_DUTY_1_2)     || \
-                               ((__DUTY__) == LCD_DUTY_1_3)     || \
-                               ((__DUTY__) == LCD_DUTY_1_4)     || \
-                               ((__DUTY__) == LCD_DUTY_1_8))
-
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup LCD_Bias LCD Bias
-  * @{
-  */
-  
-#define LCD_BIAS_1_4                    (0x00000000U)           /*!< 1/4 Bias */
-#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
-#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
-
-#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
-                               ((__BIAS__) == LCD_BIAS_1_2) || \
-                               ((__BIAS__) == LCD_BIAS_1_3))
-/**
-  * @}
-  */ 
-    
-/** @defgroup LCD_Voltage_Source LCD Voltage Source
-  * @{
-  */
-  
-#define LCD_VOLTAGESOURCE_INTERNAL      (0x00000000U)           /*!< Internal voltage source for the LCD */
-#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
-
-#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
-                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
-
-/**
-  * @}
-  */  
-
-/** @defgroup LCD_Interrupts LCD Interrupts
-  * @{
-  */
-#define LCD_IT_SOF                      LCD_FCR_SOFIE
-#define LCD_IT_UDD                      LCD_FCR_UDDIE
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
-  * @{
-  */
-
-#define LCD_PULSEONDURATION_0           (0x00000000U)                   /*!< Pulse ON duration = 0 pulse   */
-#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
-#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
-#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
-#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
-#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
-#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
-#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
-
-#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_HighDrive LCD HighDrive
-  * @{
-  */
-
-#define LCD_HIGHDRIVE_0           (0x00000000U)                   /*!< Low resistance Drive   */
-#define LCD_HIGHDRIVE_1           (LCD_FCR_HD)                    /*!< High resistance Drive  */
-
-#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
-                                         ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_DeadTime LCD Dead Time
-  * @{
-  */
-
-#define LCD_DEADTIME_0                  (0x00000000U)                     /*!< No dead Time  */
-#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
-#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
-#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
-#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
-#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
-#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
-#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
-
-#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
-                                    ((__TIME__) == LCD_DEADTIME_1) || \
-                                    ((__TIME__) == LCD_DEADTIME_2) || \
-                                    ((__TIME__) == LCD_DEADTIME_3) || \
-                                    ((__TIME__) == LCD_DEADTIME_4) || \
-                                    ((__TIME__) == LCD_DEADTIME_5) || \
-                                    ((__TIME__) == LCD_DEADTIME_6) || \
-                                    ((__TIME__) == LCD_DEADTIME_7))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_BlinkMode LCD Blink Mode
-  * @{
-  */
-
-#define LCD_BLINKMODE_OFF               (0x00000000U)           /*!< Blink disabled            */
-#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
-#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to 
-                                                                    8 pixels according to the programmed duty)  */
-#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
-
-#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
-                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
-/**
-  * @}
-  */    
-
-/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
-  * @{
-  */
-
-#define LCD_BLINKFREQUENCY_DIV8         (0x00000000U)                         /*!< The Blink frequency = fLCD/8    */
-#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
-#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
-#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
-#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
-#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
-#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
-#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
-
-#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Contrast LCD Contrast
-  * @{
-  */
-
-#define LCD_CONTRASTLEVEL_0               (0x00000000U)                 /*!< Maximum Voltage = 2.60V    */
-#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
-#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
-#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
-#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
-#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V    */
-#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V    */
-#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.51V    */
-
-#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
-/**
-  * @}
-  */
-      
-/** @defgroup LCD_MuxSegment LCD Mux Segment
-  * @{
-  */
-
-#define LCD_MUXSEGMENT_DISABLE            (0x00000000U)                 /*!< SEG pin multiplexing disabled */
-#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
-
-#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
-                                      ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
-/**
-  * @}
-  */
-      
-/** @defgroup LCD_Flag LCD Flag
-  * @{
-  */
-
-#define LCD_FLAG_ENS                    LCD_SR_ENS
-#define LCD_FLAG_SOF                    LCD_SR_SOF
-#define LCD_FLAG_UDR                    LCD_SR_UDR
-#define LCD_FLAG_UDD                    LCD_SR_UDD
-#define LCD_FLAG_RDY                    LCD_SR_RDY
-#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR
-
-/**
-  * @}
-  */   
-
-/** @defgroup LCD_RAMRegister LCD RAMRegister
-  * @{
-  */
-
-#define LCD_RAM_REGISTER0               (0x00000000U) /*!< LCD RAM Register 0  */
-#define LCD_RAM_REGISTER1               (0x00000001U) /*!< LCD RAM Register 1  */
-#define LCD_RAM_REGISTER2               (0x00000002U) /*!< LCD RAM Register 2  */
-#define LCD_RAM_REGISTER3               (0x00000003U) /*!< LCD RAM Register 3  */
-#define LCD_RAM_REGISTER4               (0x00000004U) /*!< LCD RAM Register 4  */
-#define LCD_RAM_REGISTER5               (0x00000005U) /*!< LCD RAM Register 5  */
-#define LCD_RAM_REGISTER6               (0x00000006U) /*!< LCD RAM Register 6  */
-#define LCD_RAM_REGISTER7               (0x00000007U) /*!< LCD RAM Register 7  */
-#define LCD_RAM_REGISTER8               (0x00000008U) /*!< LCD RAM Register 8  */
-#define LCD_RAM_REGISTER9               (0x00000009U) /*!< LCD RAM Register 9  */
-#define LCD_RAM_REGISTER10              (0x0000000AU) /*!< LCD RAM Register 10 */
-#define LCD_RAM_REGISTER11              (0x0000000BU) /*!< LCD RAM Register 11 */
-#define LCD_RAM_REGISTER12              (0x0000000CU) /*!< LCD RAM Register 12 */
-#define LCD_RAM_REGISTER13              (0x0000000DU) /*!< LCD RAM Register 13 */
-#define LCD_RAM_REGISTER14              (0x0000000EU) /*!< LCD RAM Register 14 */
-#define LCD_RAM_REGISTER15              (0x0000000FU) /*!< LCD RAM Register 15 */
-
-#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
-
-/**
-  * @}
-  */  
-   
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Macros LCD Exported Macros
-  * @{
-  */
-
-/** @brief Reset LCD handle state
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @retval None
-  */
-#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
-
-/** @brief  macros to enables or disables the LCD
-  * @param  __HANDLE__ specifies the LCD Handle.  
-  * @retval None
-  */     
-#define __HAL_LCD_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-#define __HAL_LCD_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-
-/** @brief  Macros to enable or disable the low resistance divider. Displays with high 
-  *         internal resistance may need a longer drive time to achieve 
-  *         satisfactory contrast. This function is useful in this case if some 
-  *         additional power consumption can be tolerated.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
-  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
-  * @retval None
-  */
-#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                                \
-                              do{                                              \
-                                  SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                               \
-                              do{                                              \
-                                  CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-/**
-  * @brief  Macro to configure the LCD pulses on duration.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __DURATION__ specifies the LCD pulse on duration in terms of 
-  *         CK_PS (prescaled LCD clock period) pulses.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_PULSEONDURATION_0: 0 pulse
-  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
-  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
-  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
-  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
-  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
-  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
-  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
-  * @retval None
-  */
-#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD dead time.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __DEADTIME__ specifies the LCD dead time.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_DEADTIME_0: No dead Time
-  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame 
-  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
-  * @retval None
-  */
-#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                        \
-        do{                                                                        \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                        \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD Contrast.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __CONTRAST__ specifies the LCD Contrast.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
-  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
-  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
-  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
-  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
-  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
-  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
-  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
-  * @retval None
-  */
-#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                       \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           } while(0) 
-
-/**
-  * @brief  Macro to configure the LCD Blink mode and Blink frequency.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __BLINKMODE__ specifies the LCD blink mode.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
-  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
-  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8 
-  *                                       pixels according to the programmed duty)
-  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM 
-  *                                       (all pixels)
-  * @param  __BLINKFREQUENCY__ specifies the LCD blink frequency.
-  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
-  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
-  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
-  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64 
-  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
-  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
-  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
-  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
-  * @retval None
-  */
-#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)  \
-        do{                                                                    \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
-            LCD_WaitForSynchro(__HANDLE__);                                    \
-          }while(0)
-
-/** @brief  Enables or disables the specified LCD interrupt.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __INTERRUPT__ specifies the LCD interrupt source to be enabled or disabled.
-  *          This parameter can be one of the following values:
-  *     @arg LCD_IT_SOF: Start of Frame Interrupt
-  *     @arg LCD_IT_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                                \
-                         do{                                                          \
-                             SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));   \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)         
-#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                               \
-                         do{                                                          \
-                             CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)
-
-/** @brief  Checks whether the specified LCD interrupt is enabled or not.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __IT__ specifies the LCD interrupt source to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_IT_SOF: Start of Frame Interrupt
-  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
-  * @note If the device is in STOP mode (PCLK not provided) UDD will not 
-  *          generate an interrupt even if UDDIE = 1. 
-  *          If the display is not enabled the UDD interrupt will never occur.
-  * @retval The state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
-
-/** @brief  Checks whether the specified LCD flag is set or not.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
-  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR 
-  *             goes from 0 to 1. On deactivation it reflects the real status of 
-  *             LCD so it becomes 0 at the end of the last displayed frame.  
-  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at 
-  *             the beginning of a new frame, at the same time as the display data is 
-  *             updated.
-  *        @arg LCD_FLAG_UDR: Update Display Request flag.
-  *        @arg LCD_FLAG_UDD: Update Display Done flag. 
-  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status 
-  *             of the step-up converter.
-  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. 
-  *             This flag is set by hardware each time the LCD_FCR register is updated 
-  *             in the LCDCLK domain. 
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-
-/** @brief  Clears the specified LCD pending flag.
-  * @param  __HANDLE__ specifies the LCD Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *        This parameter can be any combination of the following values:
-  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
-  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CLR = (__FLAG__))
-
-/**
-  * @}
-  */
-  
-/* Exported functions ------------------------------------------------------- */
-
-/** @addtogroup LCD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization/de-initialization methods  **********************************/
-HAL_StatusTypeDef     HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group2
-  * @{
-  */
-
-/* IO operation methods *******************************************************/
-HAL_StatusTypeDef     HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
-HAL_StatusTypeDef     HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral State methods  **************************************************/
-HAL_LCD_StateTypeDef  HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
-uint32_t              HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Private_Functions
-  * @{
-  */
-
-/* Private functions ---------------------------------------------------------*/
-HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_LCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h
deleted file mode 100644
index 937b75ace33..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_nor.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_nor.h
-  * @author  MCD Application Team
-  * @brief   Header file of NOR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_NOR_H
-#define STM32L1xx_HAL_NOR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(FSMC_BANK1)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_fsmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup NOR
-  * @{
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup NOR_Exported_Types NOR Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL SRAM State structures definition
-  */
-typedef enum
-{
-  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
-  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
-  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
-  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
-} HAL_NOR_StateTypeDef;
-
-/**
-  * @brief  FSMC NOR Status typedef
-  */
-typedef enum
-{
-  HAL_NOR_STATUS_SUCCESS  = 0U,
-  HAL_NOR_STATUS_ONGOING,
-  HAL_NOR_STATUS_ERROR,
-  HAL_NOR_STATUS_TIMEOUT
-} HAL_NOR_StatusTypeDef;
-
-/**
-  * @brief  FSMC NOR ID typedef
-  */
-typedef struct
-{
-  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
-
-  uint16_t Device_Code1;
-
-  uint16_t Device_Code2;
-
-  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
-                                    These codes can be accessed by performing read operations with specific
-                                    control signals and addresses set.They can also be accessed by issuing
-                                    an Auto Select command                                                   */
-} NOR_IDTypeDef;
-
-/**
-  * @brief  FSMC NOR CFI typedef
-  */
-typedef struct
-{
-  /*!< Defines the information stored in the memory's Common flash interface
-       which contains a description of various electrical and timing parameters,
-       density information and functions supported by the memory                   */
-
-  uint16_t CFI_1;
-
-  uint16_t CFI_2;
-
-  uint16_t CFI_3;
-
-  uint16_t CFI_4;
-} NOR_CFITypeDef;
-
-/**
-  * @brief  NOR handle Structure definition
-  */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-typedef struct __NOR_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
-
-{
-  FSMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
-
-  FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
-
-  FSMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
-
-  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
-
-  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
-
-  uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-  void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
-  void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-} NOR_HandleTypeDef;
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL NOR Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
-  HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
-} HAL_NOR_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL NOR Callback pointer definition
-  */
-typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup NOR_Exported_Macros NOR Exported Macros
-  * @{
-  */
-/** @brief Reset NOR handle state
-  * @param  __HANDLE__ specifies the NOR handle.
-  * @retval None
-  */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
-                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
-  * @{
-  */
-
-/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
-                               FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
-  * @{
-  */
-
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
-                                     uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
-                                        uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
-                                           pNOR_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
-  * @{
-  */
-
-/* NOR Control functions  *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-/**
-  * @}
-  */
-
-/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
-  * @{
-  */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
-  * @{
-  */
-/* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x0061)
-#define CFI2_ADDRESS             ((uint16_t)0x0062)
-#define CFI3_ADDRESS             ((uint16_t)0x0063)
-#define CFI4_ADDRESS             ((uint16_t)0x0064)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFF)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x00)
-#define NOR_MEMORY_16B           ((uint8_t)0x01)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       (0x60000000U)
-#define NOR_MEMORY_ADRESS2       (0x64000000U)
-#define NOR_MEMORY_ADRESS3       (0x68000000U)
-#define NOR_MEMORY_ADRESS4       (0x6C000000U)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Macros NOR Private Macros
-  * @{
-  */
-/**
-  * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS NOR base address
-  * @param  __NOR_MEMORY_WIDTH_ NOR memory width
-  * @param  __ADDRESS__ NOR memory address
-  * @retval NOR shifted address value
-  */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
-  ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
-              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
-              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
-  * @brief  NOR memory write data to specified address.
-  * @param  __ADDRESS__ NOR memory address
-  * @param  __DATA__ Data to write
-  * @retval None
-  */
-#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
-                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
-                                               __DSB();                                                    \
-                                             } while(0)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* FSMC_BANK1 */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h
deleted file mode 100644
index f2170be23ae..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp.h
-  * @author  MCD Application Team
-  * @brief   Header file of OPAMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_OPAMP_H
-#define STM32L1xx_HAL_OPAMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup OPAMP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  OPAMP Init structure definition  
-  */
-  
-typedef struct
-{
-  uint32_t PowerSupplyRange;            /*!< Specifies the power supply range: above or under 2.4V.
-                                             This parameter must be a value of @ref OPAMP_PowerSupplyRange
-                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
-
-  uint32_t PowerMode;                   /*!< Specifies the power mode Normal or Low-Power.
-                                             This parameter must be a value of @ref OPAMP_PowerMode */
-
-  uint32_t Mode;                        /*!< Specifies the OPAMP mode
-                                             This parameter must be a value of @ref OPAMP_Mode 
-                                             mode is either Standalone or Follower */
-
-  uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone mode
-                                               - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
-                                                 This parameter must be a value of @ref OPAMP_InvertingInput 
-                                                 InvertingInput is either VM0 or VM1
-                                               - In Follower mode:     i.e when mode is OPAMP_FOLLOWER_MODE
-                                                 This parameter is Not Applicable */ 
-
-  uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:
-                                             This parameter must be a value of @ref OPAMP_NonInvertingInput
-                                             Note: Non-inverting input availability depends on OPAMP instance:
-                                                   OPAMP1: Non-inverting input is either IO0, DAC_Channel1
-                                                   OPAMP2: Non-inverting input is either IO0, DAC_Channel1, DAC_Channel2
-                                                   OPAMP3: Non-inverting input is either IO0, DAC_Channel2 (OPAMP3 availability depends on STM32L1 devices) */
-
-  uint32_t UserTrimming;                /*!< Specifies the trimming mode 
-                                             This parameter must be a value of @ref OPAMP_UserTrimming 
-                                             UserTrimming is either factory or user trimming.
-                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
-
-  uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden)
-                                             16 is typical default value */
-  
-  uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden)
-                                             16 is typical default value */
-  
-  uint32_t TrimmingValuePLowPower;      /*!< Specifies the offset trimming value (PMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden)
-                                             16 is typical default value */
-
-  uint32_t TrimmingValueNLowPower;      /*!< Specifies the offset trimming value (NMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden)
-                                             16 is typical default value */
-
-}OPAMP_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-
-typedef enum
-{
-  HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPAMP is not yet Initialized          */
-  
-  HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
-  HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
- 
-  HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */                                                                           
-  HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005  /*!< OPAMP is locked
-                                                         only system reset allows reconfiguring the opamp. */
-    
-}HAL_OPAMP_StateTypeDef;
-
-/** 
-  * @brief OPAMP Handle Structure definition
-  */ 
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-typedef struct __OPAMP_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-{
-  OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
-  OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
-  HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
-  HAL_LockTypeDef   Lock;                           /*!< Locking object          */
-  __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
-  
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-void (* MspInitCallback)                (struct __OPAMP_HandleTypeDef *hopamp);
-void (* MspDeInitCallback)              (struct __OPAMP_HandleTypeDef *hopamp);
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-} OPAMP_HandleTypeDef;
-
-/** 
-  * @brief HAl_OPAMP_TrimmingValueTypeDef definition 
-  */ 
-
-typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
-
-/**
-  * @}
-  */
-
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL OPAMP Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_OPAMP_MSPINIT_CB_ID                     = 0x01U,  /*!< OPAMP MspInit Callback ID           */
-  HAL_OPAMP_MSPDEINIT_CB_ID                   = 0x02U,  /*!< OPAMP MspDeInit Callback ID         */
-  HAL_OPAMP_ALL_CB_ID                         = 0x03U   /*!< OPAMP All ID                        */
-}HAL_OPAMP_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL OPAMP Callback pointer definition
-  */
-typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
-  * @{
-  */
-
-/**
-  * OTR register Mask 
-  */
-#define OPAMP_TRIM_VALUE_MASK   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW
-    
-/**
-  * CSR register Mask 
-  */
-#define OPAMP_CSR_INSTANCE_OFFSET   ( 8U) /* Offset of each OPAMP instance into register CSR */
-#define OPAMP_OTR_INSTANCE_OFFSET   (10U) /* Offset of each OPAMP instance into register OTR */
-    
-        
-/** @defgroup OPAMP_Mode OPAMP Mode
-  * @{
-  */
-#define OPAMP_STANDALONE_MODE            0x00000000U  /*!< OPAMP standalone mode */
-#define OPAMP_FOLLOWER_MODE              0x00000001U  /*!< OPAMP follower mode */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput
-  * @{
-  */
-#define OPAMP_NONINVERTINGINPUT_IO0       0x00000000U   /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH1   0x00000001U   /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH2   0x00000002U   /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_InvertingInput OPAMP InvertingInput
-  * @{
-  */
-/* Note: Literal "OPAMP_SEC_INVERTINGINPUT_IO1" is a legacy naming of "OPAMP_INVERTINGINPUT_IO1". It is equivalent and must be replaced by "OPAMP_INVERTINGINPUT_IO1". */
-#define OPAMP_INVERTINGINPUT_IO0         0x00000000U   /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_INVERTINGINPUT_IO1         0x00000001U   /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_PowerMode OPAMP PowerMode
-  * @{
-  */
-#define OPAMP_POWERMODE_NORMAL        0x00000000U
-#define OPAMP_POWERMODE_LOWPOWER      0x00000001U
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
-  * @{
-  */
-#define OPAMP_POWERSUPPLY_LOW          0x00000000U             /*!< Power supply range low (VDDA lower than 2.4V) */
-#define OPAMP_POWERSUPPLY_HIGH         OPAMP_CSR_AOP_RANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
-  * @{
-  */
-#define OPAMP_TRIMMING_FACTORY         0x00000000U                           /*!< Factory trimming */
-#define OPAMP_TRIMMING_USER           OPAMP_OTR_OT_USER                      /*!< User trimming */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming
-  * @{
-  */
-#define OPAMP_FACTORYTRIMMING_DUMMY    0xFFFFFFFFU                                      /*!< Dummy value if trimming value could not be retrieved */
-
-#define OPAMP_FACTORYTRIMMING_P        0U                                               /*!< Offset trimming P */
-#define OPAMP_FACTORYTRIMMING_N        POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
-  * @{
-  */
-
-/* Offset trimming time: during calibration, minimum time needed between two  */
-/* steps to have 1 mV accuracy.                                               */
-/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
-/* Unit: ms.                                                                  */
-#define OPAMP_TRIMMING_DELAY               ((uint32_t) 1)
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Macro OPAMP Private Macro
-  * @{
-  */
-
-/** @brief Reset OPAMP handle state
-  * @param  __HANDLE__ OPAMP handle.
-  * @retval None
-  */
-#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Macro OPAMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief Select the OPAMP bit OPAxPD (power-down) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_OPAXPD(__HANDLE__)                                           \
-  (OPAMP_CSR_OPA1PD << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bit S3SELx (switch 3) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_S3SELX(__HANDLE__)                                           \
-  (OPAMP_CSR_S3SEL1 << ((OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET) & 0x1fU))
-
-/**
-  * @brief Select the OPAMP bit S4SELx (switch 4) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_S4SELX(__HANDLE__)                                           \
-  (OPAMP_CSR_S4SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit S5SELx (switch 5) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_S5SELX(__HANDLE__)                                           \
-  (OPAMP_CSR_S5SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit S3SELx (switch 6) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_S6SELX(__HANDLE__)                                           \
-  (OPAMP_CSR_S6SEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit OPAxCAL_L (offset calibration for differential 
-  * pair P) corresponding to the selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_OPAXCAL_L(__HANDLE__)                                        \
-  (OPAMP_CSR_OPA1CAL_L << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bit OPAxCAL_H (offset calibration for differential 
-  * pair N) corresponding to the selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_OPAXCAL_H(__HANDLE__)                                        \
-  (OPAMP_CSR_OPA1CAL_H << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit OPAxLPM (low power mode) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_OPAXLPM(__HANDLE__)                                          \
-  (OPAMP_CSR_OPA1LPM << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bits of all switches corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_ALL_SWITCHES(__HANDLE__)                                     \
-  ( ( ((__HANDLE__)->Instance != OPAMP2)                                       \
-    )?                                                                         \
-     (                                                                         \
-       ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))  \
-       |                                                                       \
-       (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__)))        \
-     )                                                                         \
-    :                                                                          \
-     (                                                                         \
-       ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (OPAMP_INSTANCE_DECIMAL(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))  \
-       |                                                                       \
-       (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__)))        \
-       |                                                                       \
-       (OPAMP_CSR_S7SEL2)                                                      \
-     )                                                                         \
-  )
-    
-/**
-  * @brief Select the OPAMP bit ANAWSELx (switch SanA) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_ANAWSELX(__HANDLE__)                                         \
-  (OPAMP_CSR_ANAWSEL1 << (OPAMP_INSTANCE_DECIMAL(__HANDLE__)))
-
-/**
-  * @brief Select the OPAMP bit OPAxCALOUT in function of the selected 
-  * OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define OPAMP_CSR_OPAXCALOUT(__HANDLE__)                                       \
-  (OPAMP_CSR_OPA1CALOUT << (OPAMP_INSTANCE_DECIMAL(__HANDLE__)))
-
-/**
-  * @brief Select the OPAMP trimming bits position value (position of LSB) 
-  * in register OPAMP_OTR or register OPAMP_LPOTR in function of the selected
-  * OPAMP instance and the transistors differential pair high (PMOS) or 
-  * low (NMOS).
-  * @param __HANDLE__: OPAMP handle
-  * @param __TRIM_HIGH_LOW__: transistors differential pair high or low.
-  * Must be a value of @ref OPAMP_FactoryTrimming.
-  * @retval None
-  */
-#define OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__)          \
-  ((OPAMP_INSTANCE_DECIMAL((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__))
-    
-/**
-  * @brief Shift the OPAMP trimming bits to register OPAMP_OTR or register 
-  * OPAMP_LPOTR in function of the selected OPAMP instance and the transistors
-  * differential pair high (PMOS) or low (NMOS).
-  * @param __HANDLE__: OPAMP handle
-  * @param __TRIM_HIGH_LOW__: transistors differential pair high or low.
-  * Must be a value of @ref OPAMP_FactoryTrimming.
-  * @param __TRIMMING_VALUE__: Trimming value
-  * @retval None
-  */
-#define OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \
-  ((__TRIMMING_VALUE__) << (OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__))))
-    
-/**
-  * @brief Check that trimming value is within correct range
-  * @param TRIMMINGVALUE: OPAMP trimming value
-  * @retval None
-  */
-#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 30U)
-
-#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
-                                               ((INPUT) == OPAMP_FOLLOWER_MODE))
-
-#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
-                                         ((INPUT) == OPAMP_INVERTINGINPUT_IO1)   )
-
-#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
-                                      ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
-
-#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
-                                            ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )
-
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
-                                     ((TRIMMING) == OPAMP_TRIMMING_USER))
-
-#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
-                                            ((TRIMMING) == OPAMP_FACTORYTRIMMING_P)   )
-
-/**
-  * @}
-  */
-
-
-/* Include OPAMP HAL Extension module */
-#include "stm32l1xx_hal_opamp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group2
-  * @{
-  */
-
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
-
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-/* OPAMP callback registering/unregistering */
-HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
-HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
-
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group4
-  * @{
-  */
-
-/* Peripheral State functions  **************************************************/
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h
deleted file mode 100644
index b648f20b741..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_opamp_ex.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of OPAMP HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_OPAMP_EX_H
-#define STM32L1xx_HAL_OPAMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup OPAMPEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants ---------------------------------------------------------*/
-/** @defgroup OPAMPEx_Exported_Constants OPAMPEx Exported Constants
-  * @{
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#define OPAMP_CSR_OPAXPD_ALL                                                   \
-  (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD | OPAMP_CSR_OPA3PD)
-    
-#define OPAMP_CSR_OPAXCAL_L_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA3CAL_L)
-
-#define OPAMP_CSR_OPAXCAL_H_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H | OPAMP_CSR_OPA3CAL_H)
-    
-#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS                                      \
-  (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \
-   OPAMP_CSR_ANAWSEL1                                                        | \
-   OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \
-   OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2                                     | \
-   OPAMP_CSR_S3SEL3 | OPAMP_CSR_S4SEL3 | OPAMP_CSR_S5SEL3 | OPAMP_CSR_S6SEL3 | \
-   OPAMP_CSR_ANAWSEL3                                                         )
-#else
-#define OPAMP_CSR_OPAXPD_ALL                                                   \
-  (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD)
-    
-#define OPAMP_CSR_OPAXCAL_L_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L)
-
-#define OPAMP_CSR_OPAXCAL_H_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H)
-    
-#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS                                      \
-  (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \
-   OPAMP_CSR_ANAWSEL1                                                        | \
-   OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \
-   OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2                                      )
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-    
-/** @defgroup OPAMPEx_Exported_Macro OPAMPEx Exported Macro
-  * @{
-  */
-    
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-/**
-  * @brief Enable internal analog switch SW1 to connect OPAMP3 ouput to ADC
-  * switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting input
-  * (OPAMP3 available on STM32L1 devices Cat.4 only).
-  * @retval None
-  */
-#define __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()    __HAL_RI_SWITCH_COMP1_SW1_CLOSE()
-
-/**
-  * @brief Disable internal analog switch SW1 to disconnect OPAMP3 ouput from 
-  * ADC switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting
-  * input.
-  * @retval None
-  */
-#define __HAL_OPAMP_OPAMP3OUT_DISCONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_OPEN()
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-    
-/**
-  * @}
-  */
-      
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup OPAMPEx_Private_Macro OPAMPEx Private Macro
-  * @{
-  */
-   
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-/**
-  * @brief Get the OPAMP instance in decimal number for further
-  * processing needs by HAL OPAMP driver functions.
-  * @param __HANDLE__: OPAMP handle
-  * @retval "0" for OPAMP1, "1" for OPAMP2, "2" for OPAMP3
-  */
-#define OPAMP_INSTANCE_DECIMAL(__HANDLE__)                                     \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     ((uint32_t)0UL)                                                             \
-     :                                                                         \
-     ( ( ((__HANDLE__)->Instance == OPAMP2)                                    \
-       )?                                                                      \
-        ((uint32_t)1UL)                                                          \
-        :                                                                      \
-        ((uint32_t)2UL)                                                          \
-     )                                                                         \
-  )
-#else
-/**
-  * @brief Get the OPAMP instance in decimal number for further
-  * processing needs by HAL OPAMP driver functions.
-  * @param __HANDLE__: OPAMP handle
-  * @retval "0" for OPAMP1, "1" for OPAMP2
-  */
-#define OPAMP_INSTANCE_DECIMAL(__HANDLE__)                                     \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     ((uint32_t)0UL)                                                             \
-     :                                                                         \
-     ((uint32_t)1UL)                                                             \
-  )
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/**
-  * @brief Check OPAMP non-inverting input in function of OPAMPx instance
-  * @param __HANDLE__: OPAMP handle
-  * @param INPUT: OPAMP non-inverting input                                        
-  * @retval None
-  */
-#define IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(__HANDLE__, INPUT)          \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     (                                                                         \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0)     ||                          \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1)                             \
-     )                                                                         \
-     :                                                                         \
-     ( ( ((__HANDLE__)->Instance == OPAMP2)                                    \
-       )?                                                                      \
-        (                                                                      \
-         ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0)     ||                       \
-         ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) ||                       \
-         ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2)                          \
-        )                                                                      \
-        :                                                                      \
-        (                                                                      \
-         ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0)     ||                       \
-         ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2)                          \
-        )                                                                      \
-     )                                                                         \
-  )
-#else
-/**
-  * @brief Check OPAMP non-inverting input in function of OPAMPx instance
-  * @param __HANDLE__: OPAMP handle
-  * @param INPUT: OPAMP non-inverting input                                        
-  * @retval None
-  */
-#define IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(__HANDLE__, INPUT)          \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     (                                                                         \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0)     ||                          \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1)                             \
-     )                                                                         \
-     :                                                                         \
-     (                                                                         \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0)     ||                          \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) ||                          \
-      ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2)                             \
-     )                                                                         \
-  )
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-    
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMPEx_Exported_Functions
-  * @{
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
-  * @{
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3);
-#else
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-/**
-  * @}
-  */
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup OPAMPEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_HAL_OPAMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h
deleted file mode 100644
index 9534168daa0..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd.h
+++ /dev/null
@@ -1,995 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_PCD_H
-#define STM32L1xx_HAL_PCD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_usb.h"
-
-#if defined (USB)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PCD State structure definition
-  */
-typedef enum
-{
-  HAL_PCD_STATE_RESET   = 0x00,
-  HAL_PCD_STATE_READY   = 0x01,
-  HAL_PCD_STATE_ERROR   = 0x02,
-  HAL_PCD_STATE_BUSY    = 0x03,
-  HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum
-{
-  LPM_L0 = 0x00, /* on */
-  LPM_L1 = 0x01, /* LPM L1 sleep */
-  LPM_L2 = 0x02, /* suspend */
-  LPM_L3 = 0x03, /* off */
-} PCD_LPM_StateTypeDef;
-
-typedef enum
-{
-  PCD_LPM_L0_ACTIVE = 0x00, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-} PCD_LPM_MsgTypeDef;
-
-typedef enum
-{
-  PCD_BCD_ERROR                     = 0xFF,
-  PCD_BCD_CONTACT_DETECTION         = 0xFE,
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
-
-} PCD_BCD_MsgTypeDef;
-
-
-
-
-
-typedef USB_TypeDef        PCD_TypeDef;
-typedef USB_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_EPTypeDef      PCD_EPTypeDef;
-
-
-/**
-  * @brief  PCD Handle Structure definition
-  */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-typedef struct __PCD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address             */
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
-  __IO uint8_t            USB_Address; /*!< USB Address                       */
-  PCD_EPTypeDef           IN_ep[8];   /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[8];  /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
-  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
-  uint32_t                Setup[12];   /*!< Setup packet buffer               */
-  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
-  uint32_t                BESL;
-
-  void                    *pData;      /*!< Pointer to upper stack Handler */
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
-  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
-  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
-  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
-  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
-  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
-  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
-
-  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
-  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
-  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
-  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
-
-  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
-  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Include PCD HAL Extended module */
-#include "stm32l1xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup PCD_Speed PCD Speed
-  * @{
-  */
-#define PCD_SPEED_FULL               USBD_FS_SPEED
-/**
-  * @}
-  */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
-  * @{
-  */
-#define PCD_PHY_ULPI                 1U
-#define PCD_PHY_EMBEDDED             2U
-#define PCD_PHY_UTMI                 3U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition
-  * @brief  PCD Error Code definition
-  * @{
-  */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
-  *  @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
-
-
-#define __HAL_PCD_ENABLE(__HANDLE__)                                  (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                                 (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance)\
-                                                                        & (__INTERRUPT__)) == (__INTERRUPT__))
-
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR)\
-                                                                       &= (uint16_t)(~(__INTERRUPT__)))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR = USB_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
-  do { \
-    EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
-    EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
-  } while(0U)
-
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
-  * @brief  HAL USB OTG PCD Callback ID enumeration definition
-  * @{
-  */
-typedef enum
-{
-  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
-  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
-  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
-  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
-  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
-  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
-  HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
-
-  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
-  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
-
-} HAL_PCD_CallbackIDTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
-  * @brief  HAL USB OTG PCD Callback pointer definition
-  * @{
-  */
-
-typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
-typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
-
-/**
-  * @}
-  */
-
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
-                                           HAL_PCD_CallbackIDTypeDef CallbackID,
-                                           pPCD_CallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
-                                             HAL_PCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_DataOutStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_DataInStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* I/O operation functions  ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                  uint16_t ep_mps, uint8_t ep_type);
-
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                     uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                      uint8_t *pBuf, uint32_t len);
-
-
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
-uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
-  * @{
-  */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
-  * @{
-  */
-
-
-#define USB_WAKEUP_EXTI_LINE                                          (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
-  * @{
-  */
-#define PCD_EP0MPS_64                                                 EP_MPS_64
-#define PCD_EP0MPS_32                                                 EP_MPS_32
-#define PCD_EP0MPS_16                                                 EP_MPS_16
-#define PCD_EP0MPS_08                                                 EP_MPS_8
-/**
-  * @}
-  */
-
-/** @defgroup PCD_ENDP PCD ENDP
-  * @{
-  */
-#define PCD_ENDP0                                                     0U
-#define PCD_ENDP1                                                     1U
-#define PCD_ENDP2                                                     2U
-#define PCD_ENDP3                                                     3U
-#define PCD_ENDP4                                                     4U
-#define PCD_ENDP5                                                     5U
-#define PCD_ENDP6                                                     6U
-#define PCD_ENDP7                                                     7U
-/**
-  * @}
-  */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
-  * @{
-  */
-#define PCD_SNG_BUF                                                   0U
-#define PCD_DBL_BUF                                                   1U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-
-/********************  Bit definition for USB_COUNTn_RX register  *************/
-#define USB_CNTRX_NBLK_MSK                    (0x1FU << 10)
-#define USB_CNTRX_BLSIZE                      (0x1U << 15)
-
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue)  (*(__IO uint16_t *)\
-                                                    (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum)             (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer                           USB_EPStartXfer
-
-/**
-  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wType Endpoint Type.
-  * @retval None
-  */
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
-                                                              & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
-
-
-/**
-  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval Endpoint Type
-  */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-/**
-  * @brief free buffer used from the application realizing it to the line
-  *         toggles bit SW_BUF in the double buffered endpoint register
-  * @param USBx USB device.
-  * @param   bEpNum, bDir
-  * @retval None
-  */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
-  do { \
-    if ((bDir) == 0U) \
-    { \
-      /* OUT double buffered endpoint */ \
-      PCD_TX_DTOG((USBx), (bEpNum)); \
-    } \
-    else if ((bDir) == 1U) \
-    { \
-      /* IN double buffered endpoint */ \
-      PCD_RX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0)
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
-    /* toggle first bit ? */ \
-    if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG1; \
-    } \
-    /* toggle second bit ?  */ \
-    if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG2; \
-    } \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_TX_STATUS */
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
-    /* toggle first bit ? */ \
-    if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG1; \
-    } \
-    /* toggle second bit ? */ \
-    if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG2; \
-    } \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_RX_STATUS */
-
-/**
-  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wStaterx new state.
-  * @param  wStatetx new state.
-  * @retval None
-  */
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
-    /* toggle first bit ? */ \
-    if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG1; \
-    } \
-    /* toggle second bit ? */ \
-    if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPRX_DTOG2; \
-    } \
-    /* toggle first bit ? */ \
-    if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG1; \
-    } \
-    /* toggle second bit ?  */ \
-    if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
-    { \
-      _wRegVal ^= USB_EPTX_DTOG2; \
-    } \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_TXRX_STATUS */
-
-/**
-  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
-  *         /STAT_RX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval status
-  */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
-  * @brief  sets directly the VALID tx/rx-status into the endpoint register
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
-  * @brief  checks stall condition in an endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval TRUE = endpoint in stall condition.
-  */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_KIND(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
-  } while(0) /* PCD_SET_EP_KIND */
-
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_CLEAR_EP_KIND */
-
-/**
-  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_CLEAR_RX_EP_CTR */
-
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
-  } while(0) /* PCD_CLEAR_TX_EP_CTR */
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_RX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wEPVal; \
-    \
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
-  } while(0) /* PCD_RX_DTOG */
-
-#define PCD_TX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wEPVal; \
-    \
-    _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
-  } while(0) /* PCD_TX_DTOG */
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
-    \
-    if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
-    { \
-      PCD_RX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0) /* PCD_CLEAR_RX_DTOG */
-
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
-    \
-    if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
-    { \
-      PCD_TX_DTOG((USBx), (bEpNum)); \
-    } \
-  } while(0) /* PCD_CLEAR_TX_DTOG */
-
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  bAddr Address.
-  * @retval None
-  */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
-  do { \
-    uint16_t _wRegVal; \
-    \
-    _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
-    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
-  } while(0) /* PCD_SET_EP_ADDRESS */
-
-/**
-  * @brief  Gets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
-                                                    + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
-                                                    + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-
-
-/**
-  * @brief  sets address of the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wAddr address to be set (must be word aligned).
-  * @retval None
-  */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
-  do { \
-    __IO uint16_t *_wRegVal; \
-    uint32_t _wRegBase = (uint32_t)USBx; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
-    *_wRegVal = ((wAddr) >> 1) << 1; \
-  } while(0) /* PCD_SET_EP_TX_ADDRESS */
-
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
-  do { \
-    __IO uint16_t *_wRegVal; \
-    uint32_t _wRegBase = (uint32_t)USBx; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
-    *_wRegVal = ((wAddr) >> 1) << 1; \
-  } while(0) /* PCD_SET_EP_RX_ADDRESS */
-
-/**
-  * @brief  Gets address of the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval address of the buffer.
-  */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  pdwReg Register pointer
-  * @param  wCount Counter.
-  * @param  wNBlocks no. of Blocks.
-  * @retval None
-  */
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
-  do { \
-    (wNBlocks) = (wCount) >> 5; \
-    if (((wCount) & 0x1fU) == 0U) \
-    { \
-      (wNBlocks)--; \
-    } \
-    *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
-  } while(0) /* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
-  do { \
-    (wNBlocks) = (wCount) >> 1; \
-    if (((wCount) & 0x1U) != 0U) \
-    { \
-      (wNBlocks)++; \
-    } \
-    *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
-  } while(0) /* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
-  do { \
-    uint32_t wNBlocks; \
-    if ((wCount) == 0U) \
-    { \
-      *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
-      *(pdwReg) |= USB_CNTRX_BLSIZE; \
-    } \
-    else if((wCount) <= 62U) \
-    { \
-      PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
-    } \
-    else \
-    { \
-      PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
-    } \
-  } while(0) /* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *pdwReg; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
-  } while(0)
-
-/**
-  * @brief  sets counter for the tx/rx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wCount Counter value.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wRegVal; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
-    *_wRegVal = (uint16_t)(wCount); \
-  } while(0)
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
-  do { \
-    uint32_t _wRegBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wRegVal; \
-    \
-    _wRegBase += (uint32_t)(USBx)->BTABLE; \
-    _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
-    PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
-  } while(0)
-
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval Counter value
-  */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
-
-/**
-  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wBuf0Addr buffer 0 address.
-  * @retval Counter value
-  */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
-  do { \
-    PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF0_ADDR */
-
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
-  do { \
-    PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF1_ADDR */
-
-/**
-  * @brief  Sets addresses in a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @param  wBuf1Addr = buffer 1 address.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
-  do { \
-    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
-    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
-  } while(0) /* PCD_SET_EP_DBUF_ADDR */
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
-  *         EP_DBUF_IN  = IN
-  * @param  wCount: Counter value
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    if ((bDir) == 0U) \
-      /* OUT endpoint */ \
-    { \
-      PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
-    } \
-    else \
-    { \
-      if ((bDir) == 1U) \
-      { \
-        /* IN endpoint */ \
-        PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
-      } \
-    } \
-  } while(0) /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    uint32_t _wBase = (uint32_t)(USBx); \
-    __IO uint16_t *_wEPRegVal; \
-    \
-    if ((bDir) == 0U) \
-    { \
-      /* OUT endpoint */ \
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
-    } \
-    else \
-    { \
-      if ((bDir) == 1U) \
-      { \
-        /* IN endpoint */ \
-        _wBase += (uint32_t)(USBx)->BTABLE; \
-        _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
-        *_wEPRegVal = (uint16_t)(wCount); \
-      } \
-    } \
-  } while(0) /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
-  do { \
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-  } while(0) /* PCD_SET_EP_DBUF_CNT */
-
-/**
-  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h
deleted file mode 100644
index b35bad5ede9..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PCD HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_PCD_EX_H
-#define STM32L1xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-#if defined (USB)
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @{
-  */
-
-
-
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
-                                       uint16_t ep_kind, uint32_t pmaadress);
-
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
-
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h
deleted file mode 100644
index d7fdc08497d..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PWR_H
-#define __STM32L1xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-
-/* Internal constants --------------------------------------------------------*/
-
-/** @addtogroup PWR_Private_Constants
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD  (0x00010000U)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-/**
-  * @}
-  */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00
-#define PWR_CSR_OFFSET           0x04
-#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
-  * @{
-  */
-/* --- CR Register ---*/
-/* Alias word address of LPSDSR bit */
-#define LPSDSR_BIT_NUMBER        POSITION_VAL(PWR_CR_LPSDSR)
-#define CR_LPSDSR_BB             ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
-
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER           POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
-
-/* Alias word address of LPRUN bit */
-#define LPRUN_BIT_NUMBER         POSITION_VAL(PWR_CR_LPRUN)
-#define CR_LPRUN_BB              ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER          POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
-
-/* Alias word address of FWU bit */
-#define FWU_BIT_NUMBER           POSITION_VAL(PWR_CR_FWU)
-#define CR_FWU_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
-
-/* Alias word address of ULP bit */
-#define ULP_BIT_NUMBER           POSITION_VAL(PWR_CR_ULP)
-#define CR_ULP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
-  * @{
-  */
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
-#define CSR_EWUP_BB(VAL)         ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7  /* External input analog voltage
-                                                            (Compare internally to VREFINT) */
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 (0x00000000U)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           (0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          (0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
-
- /**
- * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON           (0x00000000U)
-#define PWR_LOWPOWERREGULATOR_ON       PWR_CR_LPSDSR
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI             ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE             ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI              ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE              ((uint8_t)0x02)
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
-  * @{
-  */
-
-#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR_VOS_0
-#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR_VOS_1
-#define PWR_REGULATOR_VOLTAGE_SCALE3       PWR_CR_VOS
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                    PWR_CSR_WUF
-#define PWR_FLAG_SB                    PWR_CSR_SBF
-#define PWR_FLAG_PVDO                  PWR_CSR_PVDO
-#define PWR_FLAG_VREFINTRDY            PWR_CSR_VREFINTRDYF
-#define PWR_FLAG_VOS                   PWR_CSR_VOSF
-#define PWR_FLAG_REGLP                 PWR_CSR_REGLPF
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
-  *                                                System frequency up to 32 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
-  *                                                System frequency up to 16 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
-  *                                                System frequency up to 4.2 MHz
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
-  *                  was received from the WKUP pin or from the RTC alarm (Alarm B),
-  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
-  *                  An additional wakeup event is detected if the WKUP pin is enabled
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
-  *                 This bit indicates the state of the internal voltage reference, VREFINT.
-  *            @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
-  *                 the internal regulator to be ready after the voltage range is changed.
-  *                 The VOSF bit indicates that the regulator has reached the voltage level
-  *                 defined with bits VOS of PWR_CR register.
-  *            @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
-  *                 mode, this bit stays at 1 until the regulator is ready in main mode.
-  *                 A polling on this bit is recommended to wait for the regulator main mode.
-  *                 This bit is reset by hardware when the regulator is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
-
-/**
-  * @brief Enable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                   \
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-
-
-/**
-  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD EXTI flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
-  * @{
-  */
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
-
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-
-
-/**
-  * @}
-  */
-
-
-
-/* Include PWR HAL Extension module */
-#include "stm32l1xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-
-
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h
deleted file mode 100644
index 0c71d688f4b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PWR_EX_H
-#define __STM32L1xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
- *  @{
- */
-
-
-/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
-  * @{
-  */
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
-
-#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP1
-#define PWR_WAKEUP_PIN2                 PWR_CSR_EWUP2
-#define PWR_WAKEUP_PIN3                 PWR_CSR_EWUP3
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#else
-#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP1
-#define PWR_WAKEUP_PIN2                 PWR_CSR_EWUP2
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2))
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
- *  @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Peripheral Control methods  ************************************************/
-uint32_t HAL_PWREx_GetVoltageRange(void);
-void HAL_PWREx_EnableFastWakeUp(void);
-void HAL_PWREx_DisableFastWakeUp(void);
-void HAL_PWREx_EnableUltraLowPower(void);
-void HAL_PWREx_DisableUltraLowPower(void);
-void HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h
deleted file mode 100644
index 2cc00c4bf35..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h
+++ /dev/null
@@ -1,1898 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RCC_H
-#define __STM32L1xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-
-/** @defgroup RCC_Timeout RCC Timeout
-  * @{
-  */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
-#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
-#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
-#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Register_Offset Register offsets
-  * @{
-  */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET             0x00
-#define RCC_CFGR_OFFSET           0x08
-#define RCC_CIR_OFFSET            0x0C
-#define RCC_CSR_OFFSET            0x34
-/**
-  * @}
-  */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER      RCC_CR_HSION_Pos
-#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
-/* Alias word address of MSION bit */
-#define RCC_MSION_BIT_NUMBER      RCC_CR_MSION_Pos
-#define RCC_CR_MSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER      RCC_CR_HSEON_Pos
-#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER      RCC_CR_CSSON_Pos
-#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER      RCC_CR_PLLON_Pos
-#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER      RCC_CSR_LSION_Pos
-#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER       RCC_CSR_RMVF_Pos
-#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER      RCC_CSR_LSEON_Pos
-#define RCC_CSR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER     RCC_CSR_LSEBYP_Pos
-#define RCC_CSR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER      RCC_CSR_RTCEN_Pos
-#define RCC_CSR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
-
-/* Alias word address of RTCRST bit */
-#define RCC_RTCRST_BIT_NUMBER     RCC_CSR_RTCRST_Pos
-#define RCC_CSR_RTCRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
-
-/**
-  * @}
-  */
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX                     ((uint8_t)1U)
-#define CSR_REG_INDEX                    ((uint8_t)2U)
-
-#define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Private_Macros
-  * @{
-  */
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                             ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                             ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_1) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_2) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_3) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_4) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_5) || \
-                                            ((__RANGE__) == RCC_MSIRANGE_6))
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
-                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
-
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
-                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
-                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
-                                 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
-                                 ((__MUL__) == RCC_PLL_MUL48))
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
-                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
-                                ((__DIV__) == RCC_MCODIV_16))
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK)   || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)      || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)      || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
-                              This parameter can be a value of @ref RCC_PLL_Config */
-
-  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
-                              This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
-  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
-
-  uint32_t PLLDIV;        /*!< PLLDIV: Division factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Division_Factor*/
-} RCC_PLLInitTypeDef;
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;        /*!< The oscillators to be configured.
-                                       This parameter can be a value of @ref RCC_Oscillator_Type */
-
-  uint32_t HSEState;              /*!< The new state of the HSE.
-                                       This parameter can be a value of @ref RCC_HSE_Config */
-
-  uint32_t LSEState;              /*!< The new state of the LSE.
-                                       This parameter can be a value of @ref RCC_LSE_Config */
-
-  uint32_t HSIState;              /*!< The new state of the HSI.
-                                       This parameter can be a value of @ref RCC_HSI_Config */
-
-  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
-
-  uint32_t LSIState;              /*!< The new state of the LSI.
-                                       This parameter can be a value of @ref RCC_LSI_Config */
-
-  uint32_t MSIState;              /*!< The new state of the MSI.
-                                       This parameter can be a value of @ref RCC_MSI_Config */
-
-  uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
-
-  uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
-                                        This parameter can be a value of @ref RCC_MSI_Clock_Range */
-
-  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
-
-} RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-
-#define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI        /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE        /*!< HSE clock selected as PLL entry clock source */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
-#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
-#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
-#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
-#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
-#define RCC_OSCILLATORTYPE_MSI             (0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
-#define RCC_HSE_ON                       (0x00000001U)                     /*!< HSE clock activation */
-#define RCC_HSE_BYPASS                   (0x00000005U)                     /*!< External clock source for HSE clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
-#define RCC_LSE_ON                       (0x00000001U)                       /*!< LSE clock activation */
-#define RCC_LSE_BYPASS                   (0x00000005U)                       /*!< External clock source for LSE clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
-#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
-  * @{
-  */
-
-#define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
-#define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
-#define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
-#define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
-#define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
-#define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
-#define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
-#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Config MSI Config
-  * @{
-  */
-#define RCC_MSI_OFF                      (0x00000000U)
-#define RCC_MSI_ON                       (0x00000001U)
-
-#define RCC_MSICALIBRATION_DEFAULT       (0x00000000U)   /* Default MSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
-#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
-#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_MSI      RCC_CFGR_SWS_MSI            /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
-  * @{
-  */
-#define RCC_RTC_HSE_DIV_2               0x00000000U /*!< HSE is divided by 2 for RTC clock  */
-#define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
-#define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
-#define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV2        (RCC_RTC_HSE_DIV_2  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV4        (RCC_RTC_HSE_DIV_4  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_RTC_HSE_DIV_8  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV16       (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
-  * @{
-  */
-
-#define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
-#define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
-#define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
-  * @{
-  */
-
-#define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
-#define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
-#define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
-#define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
-#define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
-#define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
-#define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
-#define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
-#define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                         (0x00000000U)
-#define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    ((uint32_t)RCC_CFGR_MCO_DIV1)
-#define RCC_MCODIV_2                    ((uint32_t)RCC_CFGR_MCO_DIV2)
-#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO_DIV4)
-#define RCC_MCODIV_8                    ((uint32_t)RCC_CFGR_MCO_DIV8)
-#define RCC_MCODIV_16                   ((uint32_t)RCC_CFGR_MCO_DIV16)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK           RCC_CFGR_MCO_NOCLOCK
-#define RCC_MCO1SOURCE_SYSCLK            RCC_CFGR_MCO_SYSCLK
-#define RCC_MCO1SOURCE_MSI               RCC_CFGR_MCO_MSI
-#define RCC_MCO1SOURCE_HSI               RCC_CFGR_MCO_HSI
-#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO_LSE
-#define RCC_MCO1SOURCE_LSI               RCC_CFGR_MCO_LSI
-#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO_HSE
-#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO_PLL
-
-/**
-  * @}
-  */
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
-#define RCC_IT_MSIRDY                    ((uint8_t)RCC_CIR_MSIRDYF)   /*!< MSI Ready Interrupt flag */
-#define RCC_IT_LSECSS                    ((uint8_t)RCC_CIR_LSECSSF)   /*!< LSE Clock Security System Interrupt flag */
-#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: XXXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XXX  : Register index
-  *                 - 001: CR register
-  *                 - 010: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */
-#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos))  /*!< CSS on LSE failure Detection */
-#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos))  /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
-#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
-#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
-
-#define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-#define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_COMP_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_USB_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-#define __HAL_RCC_DAC_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_COMP_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */\
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_SYSCFG_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM9_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB_FORCE_RESET()       (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
-
-#define __HAL_RCC_CRC_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
-#define __HAL_RCC_FLITF_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
-#define __HAL_RCC_DMA1_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
-
-#define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00000000U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
-
-#define __HAL_RCC_CRC_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
-#define __HAL_RCC_FLITF_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()      (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_WWDG_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USB_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_PWR_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_COMP_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()    (RCC->APB1RSTR = 0x00000000U)
-#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USB_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_PWR_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_COMP_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()      (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_SYSCFG_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-#define __HAL_RCC_ADC1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()    (RCC->APB2RSTR = 0x00000000U)
-#define __HAL_RCC_SYSCFG_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#define __HAL_RCC_ADC1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
-
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
-
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
-
-/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
-
-/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)
-#define __HAL_RCC_USB_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U)
-#define __HAL_RCC_COMP_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)
-#define __HAL_RCC_USB_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U)
-#define __HAL_RCC_COMP_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U)
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()         ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U)
-#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U)
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U)
-#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U)
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U)
-#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U)
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U)
-#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U)
-#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U)
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U)
-#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U)
-#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U)
-#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U)
-#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U)
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U)
-#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U)
-#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U)
-#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U)
-#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U)
-#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U)
-#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U)
-#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U)
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
-#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U)
-#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U)
-#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U)
-#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()      ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U)
-#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration  LSI Configuration
-  * @{
-  */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  */
-#define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__ specifies the new state of the HSE.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
-  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      if ((__STATE__) == RCC_HSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_HSE_OFF)                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
-                      }                                                     \
-                    }while(0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__ specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
-  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
-                    do{                                                     \
-                      if ((__STATE__) == RCC_LSE_ON)                        \
-                      {                                                     \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_OFF)                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
-                      }                                                     \
-                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
-                      {                                                     \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);                  \
-                        SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
-                      }                                                     \
-                      else                                                  \
-                      {                                                     \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
-                        CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
-                      }                                                     \
-                    }while(0U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Configuration  MSI Configuration
-  * @{
-  */
-
-/** @brief  Macro to enable Internal Multi Speed oscillator (MSI).
-  * @note   After enabling the MSI, the application software should wait on MSIRDY
-  *         flag to be set indicating that MSI clock is stable and can be used as
-  *         system clock source.
-  */
-#define __HAL_RCC_MSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE)
-
-/** @brief  Macro to disable the Internal Multi Speed oscillator (MSI).
-  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   MSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the MSI.
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE)
-
-/** @brief  Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal MSI RC.
-  * @param  _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
-  *         (default is RCC_MSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0xFF.
-  */
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
-
-/* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
-  * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
-  *           around 2.097 MHz. The MSI clock does not change after wake-up from
-  *           STOP mode.
-  * @note    The MSI clock range can be modified on the fly.
-  * @param  _MSIRANGEVALUE_ specifies the MSI Clock range.
-  *   This parameter must be one of the following values:
-  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
-  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
-  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
-  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
-  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
-  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
-  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
-  */
-#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
-          RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
-
-/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @retval MSI clock range.
-  *         This parameter must be one of the following values:
-  *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
-  *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
-  *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
-  *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
-  *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
-  *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
-  *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
-  */
-#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{
-  */
-
-/** @brief Macro to enable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-
-/** @brief Macro to disable the main PLL.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  */
-#define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *
-  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
-  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
-  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
-  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
-  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
-  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
-  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
-  *             @arg @ref RCC_PLL_MUL24  PLLVCO = PLL clock entry x 24
-  *             @arg @ref RCC_PLL_MUL32  PLLVCO = PLL clock entry x 32
-  *             @arg @ref RCC_PLL_MUL48  PLLVCO = PLL clock entry x 48
-  * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
-  *          Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
-  *          in Range 3.
-  *
-  * @param  __PLLDIV__ specifies the division factor for PLL VCO input clock
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
-  *             @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
-  *             @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
-  *
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
-          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
-
-/** @brief  Get oscillator clock selected as PLL input clock
-  * @retval The clock source used for PLL entry. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
-  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the system clock source.
-  * @param  __SYSCLKSOURCE__ specifies the system clock source.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
-  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{
-  */
-
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_MSI          MSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSI          LSI clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSE          LSE clock selected as MCO clock
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
-  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
-  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
-  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
-  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/**
-  * @}
-  */
-
-  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{
-  */
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it cannot be changed unless the
-  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
-  *
-  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
-            if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
-            {                                                                             \
-              MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
-            }                                                                             \
-          } while (0U)
-
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
-                                      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
-                                      RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
-                                    } while (0U)
-
-/** @brief Macro to get the RTC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
-  */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
-
-/**
-  * @brief   Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
-  *
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref RCC_RTC_HSE_DIV_2  HSE divided by 2 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_4  HSE divided by 4 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_8  HSE divided by 8 selected as RTC clock
-  *         @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
-  *
-  */
-#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
-
-/** @brief Macro to enable the the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE)
-
-/** @brief Macro to disable the the RTC clock.
-  * @note  These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE)
-
-/** @brief  Macro to force the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE)
-
-/** @brief  Macros to release the Backup domain reset.
-  */
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief Enable RCC interrupt.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits.
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
-  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
-  *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
-  *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
-  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
-  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
-  *            @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
-  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
-  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
-  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
-  *            @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
-  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
-  *            @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
-  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
-  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
-  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
-  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
-  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
-  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
-  * @note (*) This bit is available in high and medium+ density devices only.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extension module */
-#include "stm32l1xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void              HAL_RCC_EnableCSS(void);
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-void              HAL_RCC_DisableCSS(void);
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h
deleted file mode 100644
index 89f0a48d27b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,1030 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RCC_EX_H
-#define __STM32L1xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */
-
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-
-#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
- || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
- || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-/* Alias word address of LSECSSON bit */
-#define LSECSSON_BITNUMBER      RCC_CSR_LSECSSON_Pos
-#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Private_Macros
-  * @{
-  */
-#if defined(LCD)
-
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
-
-#else /* Not LCD LINE */
-
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
-
-#endif /* LCD */
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#if defined(LCD)
-
-  uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#endif /* LCD */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_RTC           (0x00000001U)
-
-#if defined(LCD)
-
-#define RCC_PERIPHCLK_LCD           (0x00000002U)
-
-#endif /* LCD */
-
-/**
-  * @}
-  */
-
-#if defined(RCC_LSECSS_SUPPORT)
-/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
-  * @{
-  */
-#define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
-/**
-  * @}
-  */
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
- || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_AES_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_AES_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
- || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_LCD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
- || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
- || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
-
-#define __HAL_RCC_OPAMP_CLK_ENABLE()      __HAL_RCC_COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
-#define __HAL_RCC_OPAMP_CLK_DISABLE()     __HAL_RCC_COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
-
-/** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  */
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-    * @}
-    */
-
-
-/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
-  * @brief  Forces or releases AHB peripheral reset.
-  * @{
-  */
-#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
- || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
-#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_AES_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
-#define __HAL_RCC_AES_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
-#define __HAL_RCC_FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
- || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
-#define __HAL_RCC_LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/** @brief  Forces or releases APB1 peripheral reset.
-  */
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
- || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
-
-#define __HAL_RCC_OPAMP_FORCE_RESET()     __HAL_RCC_COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */
-#define __HAL_RCC_OPAMP_RELEASE_RESET()   __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-/** @brief  Forces or releases APB2 peripheral reset.
-  */
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
- || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
-
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
- || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
- || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
-
-#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()      __HAL_RCC_COMP_CLK_SLEEP_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
-#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()     __HAL_RCC_COMP_CLK_SLEEP_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-/** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-
-#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
- || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)
-#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
- || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_LCD_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)
-#define __HAL_RCC_LCD_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
- || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
-
-#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       __HAL_RCC_COMP_IS_CLK_ENABLED()
-#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      __HAL_RCC_COMP_IS_CLK_DISABLED()
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
-  * @brief  Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-
-#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
- || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)
-#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)
-#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)
-#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)
-#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
- || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
- || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)
-#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)
-#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
- || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
- || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
- || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
- || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)
-#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)
-#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)
-#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
- || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
- || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
- || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
-
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
-#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()      __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)
-#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-
-#if defined(RCC_LSECSS_SUPPORT)
-
-/**
-  * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
-  * @retval None
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Enable event on RCC LSE CSS EXTI Line 19.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable event on RCC LSE CSS EXTI Line 19.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
-
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
-
-/**
-  * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                      \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0U)
-
-/**
-  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                       \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0U)
-
-/**
-  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
-  * @retval EXTI RCC LSE CSS Line Status.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
-
-/**
-  * @brief Clear the RCC LSE CSS EXTI flag.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
-
-#endif /* RCC_LSECSS_SUPPORT */
-
-#if defined(LCD)
-
-/** @defgroup RCCEx_LCD_Configuration LCD Configuration
-  * @brief  Macros to configure clock source of LCD peripherals.
-  * @{
-  */
-
-/** @brief Macro to configures LCD clock (LCDCLK).
-  *  @note   LCD and RTC use the same configuration
-  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
-  *          LCD clock source.
-  *
-  *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
-  *          This parameter can be one of the following values:
-  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
-  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
-  */
-#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
-
-/** @brief Macro to get the LCD clock source.
-  */
-#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
-
-/** @brief Macro to get the LCD clock pre-scaler.
-  */
-#define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
-
-/**
-  * @}
-  */
-
-#endif /* LCD */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-#if defined(RCC_LSECSS_SUPPORT)
-
-void              HAL_RCCEx_EnableLSECSS(void);
-void              HAL_RCCEx_DisableLSECSS(void);
-void              HAL_RCCEx_EnableLSECSS_IT(void);
-void              HAL_RCCEx_LSECSS_IRQHandler(void);
-void              HAL_RCCEx_LSECSS_Callback(void);
-
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h
deleted file mode 100644
index 24024f814af..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h
+++ /dev/null
@@ -1,814 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RTC_H
-#define __STM32L1xx_HAL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
-
-} HAL_RTCStateTypeDef;
-
-/**
-  * @brief  RTC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-} RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity */
-
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  uint32_t DayLightSaving;  /*!< This interface is deprecated. To manage Daylight
-                                 Saving Time, please use HAL_RTC_DST_xxx functions */
-
-  uint32_t StoreOperation;  /*!< This interface is deprecated. To manage Daylight
-                                 Saving Time, please use HAL_RTC_DST_xxx functions */
-} RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-} RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-} RTC_AlarmTypeDef;
-
-/**
-  * @brief  RTC Handle Structure definition
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-typedef struct __RTC_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm A Event callback         */
-
-  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm B Event callback         */
-
-  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);        /*!< RTC TimeStamp Event callback       */
-
-  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);      /*!< RTC WakeUpTimer Event callback     */
-
-  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 1 Event callback        */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 2 Event callback        */
-
-  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 3 Event callback        */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);               /*!< RTC Msp Init callback              */
-
-  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);             /*!< RTC Msp DeInit callback            */
-
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-} RTC_HandleTypeDef;
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL LPTIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00U,    /*!< RTC Alarm A Event Callback ID      */
-  HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01U,    /*!< RTC Alarm B Event Callback ID      */
-  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02U,    /*!< RTC TimeStamp Event Callback ID    */
-  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03U,    /*!< RTC WakeUp Timer Event Callback ID */
-  HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04U,    /*!< RTC Tamper 1 Callback ID           */
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05U,    /*!< RTC Tamper 2 Callback ID           */
-  HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06U,    /*!< RTC Tamper 3 Callback ID           */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  HAL_RTC_MSPINIT_CB_ID                 = 0x0EU,    /*!< RTC Msp Init callback ID           */
-  HAL_RTC_MSPDEINIT_CB_ID               = 0x0FU     /*!< RTC Msp DeInit callback ID         */
-} HAL_RTC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RTC Callback pointer definition
-  */
-typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */
-#define RTC_HOURFORMAT_24              (0x00000000U)
-#define RTC_HOURFORMAT_12              (0x00000040U)
-
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH       (0x00000000U)
-#define RTC_OUTPUT_POLARITY_LOW        (0x00100000U)
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      (0x00000000U)
-#define RTC_OUTPUT_TYPE_PUSHPULL       (0x00040000U)
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider
-  * @{
-  */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Time_Definitions Time Definitions
-  * @{
-  */
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AM_PM_Definitions AM PM Definitions
-  * @{
-  */
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving
-  * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H       (0x00020000U)
-#define RTC_DAYLIGHTSAVING_ADD1H       (0x00010000U)
-#define RTC_DAYLIGHTSAVING_NONE        (0x00000000U)
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions StoreOperation
-  * @{
-  */
-#define RTC_STOREOPERATION_RESET        (0x00000000U)
-#define RTC_STOREOPERATION_SET          (0x00040000U)
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
-  * @{
-  */
-#define RTC_FORMAT_BIN                      (0x000000000U)
-#define RTC_FORMAT_BCD                      (0x000000001U)
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Year_Date_Definitions Year Definitions
-  * @{
-  */
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions Month Definitions
-  * @{
-  */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
-
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
-  * @{
-  */
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarm_Definitions Alarm Definitions
-  * @{
-  */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions
-  * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      (0x00000000U)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   (0x40000000U)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions
-  * @{
-  */
-#define RTC_ALARMMASK_NONE                (0x00000000U)
-#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 (0x80808080U)
-
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarms_Definitions Alarms Definitions
-  * @{
-  */
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief  Reset RTC handle state
-  * @param  __HANDLE__ RTC handle.
-  * @retval None
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0)
-#else
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
-                            (__HANDLE__)->Instance->WPR = 0x53U;   \
-                          } while(0U)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
-                          } while(0U)
-
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)  (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
-                                                           } while(0U)
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
-                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
-                                                           } while(0U)
-
-/**
-  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Clear the RTC Alarm associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extended module */
-#include "stm32l1xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-
-void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-/* RTC Daylight Saving Time functions *****************************************/
-void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-#define RTC_TIMEOUT_VALUE  1000U
-
-#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -------------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h
deleted file mode 100644
index 1c3a2242dd2..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,1218 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RTC_EX_H
-#define __STM32L1xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RTC Tamper structure definition
-  */
-typedef struct
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-} RTC_TamperTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RTCEx_Output_selection_Definition RTCEx Output Selection Definition
-  * @{
-  */
-#define RTC_TR_RESERVED_MASK    (0x007F7F7FU)
-#define RTC_DR_RESERVED_MASK    (0x00FFFF3FU)
-#define RTC_INIT_MASK           (0xFFFFFFFFU)
-#define RTC_RSF_MASK            (0xFFFFFF5FU)
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
-                                            RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \
-                                            RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \
-                                            RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
-                                            RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \
-                                            RTC_FLAG_RECALPF))
-#else
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
-                                            RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \
-                                            RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \
-                                            RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
-                                            RTC_FLAG_TAMP1F | \
-                                            RTC_FLAG_RECALPF))
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Backup_Registers_Definition RTCEx Backup Registers Definition
-  * @{
-  */
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFFU)
-#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x1FFFU)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
-  * @{
-  */
-#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)
-#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)
-#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)
-#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)
-#define RTC_IT_TAMP1                      ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP1E))
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_IT_TAMP2                      ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP2E))
-#define RTC_IT_TAMP3                      ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP3E))
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions Flags Definitions
-  * @{
-  */
-#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
-#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
-#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
-#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
-#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
-#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
-#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
-#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
-#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions
-  * @{
-  */
-#define RTC_OUTPUT_DISABLE             (0x00000000U)
-#define RTC_OUTPUT_ALARMA              (0x00200000U)
-#define RTC_OUTPUT_ALARMB              (0x00400000U)
-#define RTC_OUTPUT_WAKEUP              (0x00600000U)
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
-  * @{
-  */
-#if RTC_BKP_NUMBER > 0
-#define RTC_BKP_DR0                       (0x00000000U)
-#define RTC_BKP_DR1                       (0x00000001U)
-#define RTC_BKP_DR2                       (0x00000002U)
-#define RTC_BKP_DR3                       (0x00000003U)
-#define RTC_BKP_DR4                       (0x00000004U)
-#endif /* RTC_BKP_NUMBER > 0 */
-
-#if RTC_BKP_NUMBER > 5
-#define RTC_BKP_DR5                       (0x00000005U)
-#define RTC_BKP_DR6                       (0x00000006U)
-#define RTC_BKP_DR7                       (0x00000007U)
-#define RTC_BKP_DR8                       (0x00000008U)
-#define RTC_BKP_DR9                       (0x00000009U)
-#define RTC_BKP_DR10                      (0x0000000AU)
-#define RTC_BKP_DR11                      (0x0000000BU)
-#define RTC_BKP_DR12                      (0x0000000CU)
-#define RTC_BKP_DR13                      (0x0000000DU)
-#define RTC_BKP_DR14                      (0x0000000EU)
-#define RTC_BKP_DR15                      (0x0000000FU)
-#define RTC_BKP_DR16                      (0x00000010U)
-#define RTC_BKP_DR17                      (0x00000011U)
-#define RTC_BKP_DR18                      (0x00000012U)
-#define RTC_BKP_DR19                      (0x00000013U)
-#endif /* RTC_BKP_NUMBER > 5 */
-
-#if RTC_BKP_NUMBER > 20
-#define RTC_BKP_DR20                      (0x00000014U)
-#define RTC_BKP_DR21                      (0x00000015U)
-#define RTC_BKP_DR22                      (0x00000016U)
-#define RTC_BKP_DR23                      (0x00000017U)
-#define RTC_BKP_DR24                      (0x00000018U)
-#define RTC_BKP_DR25                      (0x00000019U)
-#define RTC_BKP_DR26                      (0x0000001AU)
-#define RTC_BKP_DR27                      (0x0000001BU)
-#define RTC_BKP_DR28                      (0x0000001CU)
-#define RTC_BKP_DR29                      (0x0000001DU)
-#define RTC_BKP_DR30                      (0x0000001EU)
-#define RTC_BKP_DR31                      (0x0000001FU)
-#endif /* RTC_BKP_NUMBER > 20 */
-
-#define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING          (0x00000000U)
-#define RTC_TIMESTAMPEDGE_FALLING         (0x00000008U)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
-  * @{
-  */
-#define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
-#define RTC_TAMPER_3                    RTC_TAFCR_TAMP3E
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_RTC_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET))
-#else
-#define IS_RTC_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
-  * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       (0x00000000U)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      (0x00000002U)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTCex Tamper Filter Definitions
-  * @{
-  */
-#define RTC_TAMPERFILTER_DISABLE   (0x00000000U)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   (0x00000800U)  /*!< Tamper is activated after 2 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   (0x00001000U)  /*!< Tamper is activated after 4 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   (0x00001800U)  /*!< Tamper is activated after 8 
-                                                                consecutive samples at the active level. */
-
-#define IS_RTC_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
-  * @{
-  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  (0x00000000U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  (0x00000100U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   (0x00000200U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (0x00000300U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   (0x00000400U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (0x00000500U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (0x00000600U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (0x00000700U)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 256   */
-
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions TimeStampOnTamperDetection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                          ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE  (0x00000000U)            /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TAMPER_PULLUP_DISABLE (RTC_TAFCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                       ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-/**
-  * @}
-  */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        (0x00000000U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         (0x00000001U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         (0x00000002U)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (0x00000003U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      (0x00000004U)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (0x00000006U)
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions
-  * @{
-  */
-#define RTC_CALIBSIGN_POSITIVE            (0x00000000U)
-#define RTC_CALIBSIGN_NEGATIVE            (0x00000080U)
-
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
-                                 ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   (0x00000000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   (0x00002000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    (0x00004000U) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 8s, else 2exp18 RTCCLK seconds */
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    (0x00008000U) /*!<  The number of RTCCLK pulses added
-                                                                       during a X -second window = Y - CALM[8:0]
-                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  (0x00000000U) /*!<  The number of RTCCLK pulses subbstited
-                                                                       during a 32-second window =   CALM[8:0] */
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions
-  * @{
-  */
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions
-  * @{
-  */
-#define RTC_SHIFTADD1S_RESET      (0x00000000U)
-#define RTC_SHIFTADD1S_SET        (0x80000000U)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value
-  * @{
-  */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions
-  * @{
-  */
-#define RTC_CALIBOUTPUT_512HZ            (0x00000000U)
-#define RTC_CALIBOUTPUT_1HZ              (0x00080000U)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-/**
-  * @}
-  */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value
-  * @{
-  */
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDMASK_ALL         (0x00000000U)  /*!< All Alarm SS fields are masked. 
-                                                                        There is no comparison on sub seconds 
-                                                                        for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      (0x01000000U)  /*!< SS[14:1] are don't care in Alarm 
-                                                                        comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      (0x02000000U)  /*!< SS[14:2] are don't care in Alarm 
-                                                                        comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      (0x03000000U)  /*!< SS[14:3] are don't care in Alarm 
-                                                                        comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      (0x04000000U)  /*!< SS[14:4] are don't care in Alarm 
-                                                                        comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      (0x05000000U)  /*!< SS[14:5] are don't care in Alarm 
-                                                                        comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      (0x06000000U)  /*!< SS[14:6] are don't care in Alarm 
-                                                                        comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      (0x07000000U)  /*!< SS[14:7] are don't care in Alarm 
-                                                                        comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      (0x08000000U)  /*!< SS[14:8] are don't care in Alarm 
-                                                                        comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      (0x09000000U)  /*!< SS[14:9] are don't care in Alarm 
-                                                                        comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     (0x0A000000U)  /*!< SS[14:10] are don't care in Alarm 
-                                                                        comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     (0x0B000000U)  /*!< SS[14:11] are don't care in Alarm 
-                                                                        comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     (0x0C000000U)  /*!< SS[14:12] are don't care in Alarm 
-                                                                        comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     (0x0D000000U)  /*!< SS[14:13] are don't care in Alarm 
-                                                                        comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        (0x0E000000U)  /*!< SS[14] is don't care in Alarm 
-                                                                        comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        (0x0F000000U)  /*!< SS[14:0] are compared and must match 
-                                                                        to activate alarm. */
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-/**
-  * @}
-  */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
-  * @{
-  */
-/**
-  * @brief Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the Coarse calibration process.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
-
-/**
-  * @brief  Disable the Coarse calibration process.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *             @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *          This parameter can be:
-  *             @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E)
-
-/**
-  * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E)
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\
-  || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\
-  || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\
-  || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Enable the RTC Tamper2 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E)
-
-/**
-  * @brief  Disable the RTC Tamper2 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E)
-
-/**
-  * @brief  Enable the RTC Tamper3 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E)
-
-/**
-  * @brief  Disable the RTC Tamper3 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E)
-
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET) : \
-                                                           ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP2F) != RESET) ? SET : RESET) : \
-                                                           (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP3F) != RESET) ? SET : RESET))
-#else
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET)
-
-#endif
-
-/**
-  * @brief  Enable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled
-  *          This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt (*)
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
-  * @note   (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC,
-  *         STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA,
-  *         STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE
-  *         STM32L151xDX, STM32L152xDX, STM32L162xDX
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)         SET_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE)
-
-/**
-  * @brief  Disable the RTC Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt (*)
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
-  * @note   (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC,
-  *         STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA,
-  *         STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE
-  *         STM32L151xDX, STM32L152xDX, STM32L162xDX
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)        CLEAR_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE)
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt (*)
-  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt (*)
-  * @note   (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC,
-  *         STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA,
-  *         STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE
-  *         STM32L151xDX, STM32L152xDX, STM32L162xDX
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAFCR) & RTC_TAFCR_TAMPIE) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)              (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC TimeStamp Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  *            @arg RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
-  *            @arg RTC_FLAG_WUTWF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F
-  *            @arg RTC_FLAG_TAMP2F  (*)
-  *            @arg RTC_FLAG_TAMP3F  (*)
-  * @note   (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC,
-  *         STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA,
-  *         STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE
-  *         STM32L151xDX, STM32L152xDX, STM32L162xDX
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\
-  || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\
-  || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\
-  || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_SHPF
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F
-  *            @arg RTC_FLAG_TAMP2F  (*)
-  *            @arg RTC_FLAG_TAMP3F  (*)
-  * @note   (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC,
-  *         STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA,
-  *         STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE
-  *         STM32L151xDX, STM32L152xDX, STM32L162xDX
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Clear the RTC WakeUp Timer associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
-  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
-  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0);
-
-/**
-  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
-  * @retval Line Status.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
-  * @retval None.
-  */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-/**
-  * @}
-  */
-
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
-  * @{
-  */
-void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-#else
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Extended RTC features functions *******************************************/
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
-  * @{
-  */
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  (0x00080000U)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       (0x00100000U)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h
deleted file mode 100644
index 783a8646c6e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sd.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sd.h
-  * @author  MCD Application Team
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_SD_H
-#define STM32L1xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(SDIO)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_sdmmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SD SD
-  * @brief SD HAL module driver
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
-  * @{
-  */   
-typedef enum
-{
-  HAL_SD_STATE_RESET                  = 0x00000000U,  /*!< SD not yet initialized or disabled  */
-  HAL_SD_STATE_READY                  = 0x00000001U,  /*!< SD initialized and ready for use    */
-  HAL_SD_STATE_TIMEOUT                = 0x00000002U,  /*!< SD Timeout state                    */
-  HAL_SD_STATE_BUSY                   = 0x00000003U,  /*!< SD process ongoing                  */
-  HAL_SD_STATE_PROGRAMMING            = 0x00000004U,  /*!< SD Programming State                */
-  HAL_SD_STATE_RECEIVING              = 0x00000005U,  /*!< SD Receiving State                  */
-  HAL_SD_STATE_TRANSFER               = 0x00000006U,  /*!< SD Transfer State                  */
-  HAL_SD_STATE_ERROR                  = 0x0000000FU   /*!< SD is in error state                */
-}HAL_SD_StateTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
-  * @{
-  */   
-typedef uint32_t HAL_SD_CardStateTypeDef;
-
-#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
-#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
-#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
-#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
-#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
-#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
-#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
-#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
-#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
-  * @{
-  */
-#define SD_InitTypeDef      SDIO_InitTypeDef 
-#define SD_TypeDef          SDIO_TypeDef
-
-/** 
-  * @brief  SD Card Information Structure definition
-  */ 
-typedef struct
-{
-  uint32_t CardType;                     /*!< Specifies the card Type                         */
-  
-  uint32_t CardVersion;                  /*!< Specifies the card version                      */
-
-  uint32_t Class;                        /*!< Specifies the class of the card class           */
-
-  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
-  
-  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
-
-  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
-  
-  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
-
-  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
-
-}HAL_SD_CardInfoTypeDef;
-
-/** 
-  * @brief  SD handle Structure definition
-  */ 
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-typedef struct __SD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-{
-  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
-  
-  SD_InitTypeDef               Init;             /*!< SD required parameters              */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
-  
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
-
-  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
-
-  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
-
-  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
-  
-  __IO uint32_t                Context;          /*!< SD transfer context                 */
- 
-  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
-  
-  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
- 
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
-
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
-  
-  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
-  
-  uint32_t                     CSD[4];           /*!< SD card specific data table         */
-  
-  uint32_t                     CID[4];           /*!< SD card identification number table */
-  
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
-  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
-  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
-  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
-
-  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
-  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-}SD_HandleTypeDef;
-
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-}HAL_SD_CardCSDTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CardCIDTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
-  * @{
-  */
-typedef struct
-{
-  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t CardType;               /*!< Carries information about card type                        */
-  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypeDef;
-/** 
-  * @}
-  */
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition 
-  * @{
-  */
-typedef enum
-{
-  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
-  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
-  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
-  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
-
-  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
-  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
-}HAL_SD_CallbackIDTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition 
-  * @{
-  */
-typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
-/** 
-  * @}
-  */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-/** 
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
-  * @{
-  */
-
-#define BLOCKSIZE   512U /*!< Block size is 512 bytes */
-
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
-  * @{
-  */  
-#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
-#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
-#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
-#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
-#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
-#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
-#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
-#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
-                                                                                       number of transferred bytes does not match the block length   */
-#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
-#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
-#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
-                                                                                       command or if there was an attempt to access a locked card    */
-#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
-#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
-#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
-#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
-#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
-#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
-#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
-#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
-#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
-#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
-#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
-                                                                                       of erase sequence command was received                        */
-#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
-#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
-#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
-#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
-#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
-#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
-                                                
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-/** 
-  * @}
-  */
- 
-/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
-  * @{
-  */ 
-#define SD_CONTEXT_NONE                            0x00000000U   /*!< None                             */
-#define SD_CONTEXT_READ_SINGLE_BLOCK               0x00000001U   /*!< Read single block operation      */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK             0x00000002U   /*!< Read multiple blocks operation   */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK              0x00000010U   /*!< Write single block operation     */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK            0x00000020U   /*!< Write multiple blocks operation  */
-#define SD_CONTEXT_IT                              0x00000008U   /*!< Process in Interrupt mode        */
-#define SD_CONTEXT_DMA                             0x00000080U   /*!< Process in DMA mode              */
-
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
-  * @{
-  */
-#define CARD_SDSC                  0x00000000U  /*!< SD Standard Capacity <2Go                          */
-#define CARD_SDHC_SDXC             0x00000001U  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
-#define CARD_SECURED               0x00000003U
-    
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
-  * @{
-  */
-#define CARD_V1_X                  0x00000000U
-#define CARD_V2_X                  0x00000001U
-/**
-  * @}
-  */
-      
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset SD handle state.
-  * @param  __HANDLE__ : SD handle.
-  * @retval None
-  */
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
-                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
- 
-/**
-  * @brief  Enable the SD device.
-  * @retval None
-  */ 
-#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Enable the SDMMC DMA transfer.
-  * @retval None
-  */ 
-#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
-  * @brief  Disable the SDMMC DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
- 
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
-  * @retval None
-  */
-#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not. 
-  * @param  __HANDLE__: SD Handle   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
-  * @retval None
-  */
-#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
-  * @retval None
-  */
-#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
-  * @{
-  */
-  
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/* SD callback registering/unregistering */
-HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group4 SD card related functions
-  * @{
-  */
-HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
-  * @{
-  */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
-  * @{
-  */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-    
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* SDIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_HAL_SD_H */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h
deleted file mode 100644
index 3aeb6f8585d..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_smartcard.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_smartcard.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMARTCARD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SMARTCARD_H
-#define __STM32L1xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
-  * @{
-  */
-
-/**
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref SMARTCARD_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref SMARTCARD_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits).*/
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
-  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
-                                           to provide the smartcard clock. The value given in the register (5 significant bits)
-                                           is multiplied by 2 to give the division factor of the source clock frequency.
-                                           This parameter can be a value of @ref SMARTCARD_Prescaler */
-
-  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-
-  uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state.
-                                           This parameter can be a value of @ref SMARTCARD_NACK_State */
-}SMARTCARD_InitTypeDef;
-
-/**
-  * @brief HAL SMARTCARD State structures definition
-  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains SMARTCARD state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initialization status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized. HAL SMARTCARD Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initialization status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef enum
-{
-  HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                        Value is allowed for gState and RxState */
-  HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                        Value is allowed for gState and RxState */
-  HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                        Value is allowed for RxState only */
-  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                        Not to be used for neither gState nor RxState.
-                                                        Value is result of combination (Or) between gState and RxState values */
-  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error
-                                                        Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
-
-/**
-  * @brief  SMARTCARD handle Structure definition
-  */
-typedef struct __SMARTCARD_HandleTypeDef
-{
-  USART_TypeDef                    *Instance;        /*!< USART registers base address */
-
-  SMARTCARD_InitTypeDef            Init;             /*!< SmartCard communication parameters */
-
-  uint8_t                          *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer */
-
-  uint16_t                         TxXferSize;       /*!< SmartCard Tx Transfer size */
-
-  __IO uint16_t                    TxXferCount;      /*!< SmartCard Tx Transfer Counter */
-
-  uint8_t                          *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer */
-
-  uint16_t                         RxXferSize;       /*!< SmartCard Rx Transfer size */
-
-  __IO uint16_t                    RxXferCount;      /*!< SmartCard Rx Transfer Counter */
-
-  DMA_HandleTypeDef                *hdmatx;          /*!< SmartCard Tx DMA Handle parameters */
-
-  DMA_HandleTypeDef                *hdmarx;          /*!< SmartCard Rx DMA Handle parameters */
-
-  HAL_LockTypeDef                  Lock;             /*!< Locking object */
-
-  __IO HAL_SMARTCARD_StateTypeDef  gState;           /*!< SmartCard state information related to global Handle management
-                                                        and also related to Tx operations.
-                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
-  __IO HAL_SMARTCARD_StateTypeDef  RxState;          /*!< SmartCard state information related to Rx operations.
-                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
-  __IO uint32_t                    ErrorCode;        /*!< SmartCard Error code */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Tx Complete Callback             */
-
-  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc);             /*!< SMARTCARD Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);  /*!< SMARTCARD Abort Receive Complete Callback  */
-
-  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);           /*!< SMARTCARD Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Msp DeInit callback              */
-#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-} SMARTCARD_HandleTypeDef;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMARTCARD Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
-  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
-  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
-  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
-  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
-  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
-
-  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
-  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
-
-} HAL_SMARTCARD_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMARTCARD Callback pointer definition
-  */
-typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!< pointer to an SMARTCARD callback function */
-
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
-  * @{
-  */
-#define HAL_SMARTCARD_ERROR_NONE             0x00000000U   /*!< No error            */
-#define HAL_SMARTCARD_ERROR_PE               0x00000001U   /*!< Parity error        */
-#define HAL_SMARTCARD_ERROR_NE               0x00000002U   /*!< Noise error         */
-#define HAL_SMARTCARD_ERROR_FE               0x00000004U   /*!< Frame error         */
-#define HAL_SMARTCARD_ERROR_ORE              0x00000008U   /*!< Overrun error       */
-#define HAL_SMARTCARD_ERROR_DMA              0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
-  * @{
-  */
-#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
-  * @{
-  */
-#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
-  * @{
-  */
-#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
-  * @{
-  */
-#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
-  * @{
-  */
-#define SMARTCARD_POLARITY_LOW              0x00000000U
-#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
-  * @{
-  */
-#define SMARTCARD_PHASE_1EDGE               0x00000000U
-#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
-  * @{
-  */
-#define SMARTCARD_LASTBIT_DISABLE           0x00000000U
-#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE              0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests
-  * @{
-  */
-#define SMARTCARD_DMAREQ_TX                 ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX                 ((uint32_t)USART_CR3_DMAR)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
-  * @{
-  */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2     0x00000001U          /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4     0x00000002U          /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6     0x00000003U          /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8     0x00000004U          /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10    0x00000005U          /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12    0x00000006U          /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14    0x00000007U          /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16    0x00000008U          /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18    0x00000009U          /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20    0x0000000AU          /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22    0x0000000BU          /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24    0x0000000CU          /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26    0x0000000DU          /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28    0x0000000EU          /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30    0x0000000FU          /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32    0x00000010U          /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34    0x00000011U          /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36    0x00000012U          /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38    0x00000013U          /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40    0x00000014U          /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42    0x00000015U          /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44    0x00000016U          /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46    0x00000017U          /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48    0x00000018U          /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50    0x00000019U          /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52    0x0000001AU          /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54    0x0000001BU          /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56    0x0000001CU          /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58    0x0000001DU          /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60    0x0000001EU          /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62    0x0000001FU          /*!< SYSCLK divided by 62 */
-/**
-  * @}
-  */
-
-/** @defgroup SmartCard_Flags SMARTCARD Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define SMARTCARD_FLAG_TXE                  ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC                   ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE                 ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE                 ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE                  ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE                   ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE                   ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE                   ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the Y register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 11: CR3 register
-  * @{
-  */
-#define SMARTCARD_IT_PE                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE                    ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR                    ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
-  * @{
-  */
-
-/** @brief Reset SMARTCARD handle gstate & RxState
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                           (__HANDLE__)->MspInitCallback = NULL;                  \
-                                                           (__HANDLE__)->MspDeInitCallback = NULL;                \
-                                                          } while(0U)
-#else
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                          } while(0U)
-#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the Smartcard DR register
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
-  *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
-  *            @arg SMARTCARD_FLAG_ORE:  Overrun Error flag
-  *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
-  *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
-  *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified Smartcard pending flags.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
-  *          error) flags are cleared by software sequence: a read operation to
-  *          USART_SR register followed by a read operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)  \
-    do{                                           \
-      __IO uint32_t tmpreg = 0x00U;               \
-      tmpreg = (__HANDLE__)->Instance->SR;        \
-      tmpreg = (__HANDLE__)->Instance->DR;        \
-      UNUSED(tmpreg);                             \
-    } while(0U)
-
-/** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                                 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Disable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                                 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __IT__ specifies the SMARTCARD interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_ERR: Error interrupt
-  *            @arg SMARTCARD_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-
-/** @brief  Macro to enable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Macro to disable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/** @brief  Macros to enable the SmartCard DMA request.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __REQUEST__ specifies the SmartCard DMA request.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
-
-/** @brief  Macros to disable the SmartCard DMA request.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __REQUEST__ specifies the SmartCard DMA request.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
-  * @{
-  */
-
-/** @brief SMARTCARD interruptions flag mask
-  *
-  */
-#define SMARTCARD_IT_MASK                   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                                        USART_CR1_IDLEIE | USART_CR3_EIE )
-
-#define SMARTCARD_CR1_REG_INDEX             1U
-#define SMARTCARD_CR3_REG_INDEX             3U
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
-  * @{
-  */
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH)    ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS)     (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
-                                             ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY)         (((PARITY) == SMARTCARD_PARITY_EVEN) || \
-                                             ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
-#define IS_SMARTCARD_POLARITY(CPOL)         (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA)            (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT)       (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
-                                             ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK)       (((NACK) == SMARTCARD_NACK_ENABLE) || \
-                                             ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE)     ((BAUDRATE) < 2000001U)
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25U)/(4U*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__)            (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__)            ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
-/* SMARTCARD BRR = mantissa + overflow + fraction
-            = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
-#define SMARTCARD_BRR(__PCLK__, __BAUD__)       (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
-                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
-                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h
deleted file mode 100644
index 6ec4766f555..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_SPI_H
-#define STM32L1xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-  uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
-                                     This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-} SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
-  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
-} HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
-
-  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
-
-  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
-
-  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
-
-  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
-
-  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
-
-  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
-
-  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
-
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
-
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
-
-  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
-
-  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
-
-  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
-  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
-  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
-  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
-  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
-  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
-  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
-  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
-
-#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL SPI Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
-  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
-  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
-  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
-  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
-  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
-  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
-  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SPI Callback pointer definition
-  */
-typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
-#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
-#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
-#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
-#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
-#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY Flag             */
-#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  (0x00000000U)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_8BIT               (0x00000000U)
-#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                (0x00000000U)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 (0x00000000U)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                (0x00000000U)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
-  * @brief  SPI TI Mode not supported for Category 1 and 2
-  * @{
-  */
-#define SPI_TIMODE_DISABLE              (0x00000000U)
-#if defined(SPI_CR2_FRF)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
-#if defined(SPI_CR2_FRF)
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
-                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
-#else
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\
-                                         | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR)
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Disable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI handle.
-  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
-  do{                                                    \
-    __IO uint32_t tmpreg_modf = 0x00U;                   \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
-    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                                 \
-  } while(0U)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0U)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_fre = 0x00U;              \
-    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_fre);                            \
-  }while(0U)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of SPI SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
-                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of SPI CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
-                                                     (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if SPI Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Mode.
-  *         This parameter can be a value of @ref SPI_Mode
-  * @retval None
-  */
-#define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \
-                                    ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  *         This parameter can be a value of @ref SPI_Direction
-  * @retval None
-  */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
-                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Data Size parameter is in allowed range.
-  * @param  __DATASIZE__ specifies the SPI Data Size.
-  *         This parameter can be a value of @ref SPI_Data_Size
-  * @retval None
-  */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the SPI serial clock steady state.
-  *         This parameter can be a value of @ref SPI_Clock_Polarity
-  * @retval None
-  */
-#define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \
-                                    ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
-  * @param  __CPHA__ specifies the SPI Clock Phase.
-  *         This parameter can be a value of @ref SPI_Clock_Phase
-  * @retval None
-  */
-#define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \
-                                    ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief  Checks if SPI Slave Select parameter is in allowed range.
-  * @param  __NSS__ specifies the SPI Slave Select management parameter.
-  *         This parameter can be a value of @ref SPI_Slave_Select_management
-  * @retval None
-  */
-#define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \
-                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \
-                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-  * @retval None
-  */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
-  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
-  * @retval None
-  */
-#define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \
-                                    ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-#if defined(SPI_I2SCFGR_I2SMOD)
-/** @brief  Checks if SPI TI mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI TI mode.
-  *         This parameter can be a value of @ref SPI_TI_mode
-  * @retval None
-  */
-#define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \
-                                    ((__MODE__) == SPI_TIMODE_ENABLE))
-#else
-/** @defgroup SPI_TI_mode SPI TI mode disable
-  * @brief  SPI TI Mode not supported for Category 1 and 2
-  * @{
-  */
-#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
-
-#endif
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
-  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
-  *         This parameter can be a value of @ref SPI_CRC_Calculation
-  * @retval None
-  */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
-  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
-  * @retval None
-  */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \
-                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \
-                                              (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief  Checks if DMA handle is valid.
-  * @param  __HANDLE__ specifies a DMA Handle.
-  * @retval None
-  */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h
deleted file mode 100644
index fa1c6a396d8..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_sram.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sram.h
-  * @author  MCD Application Team
-  * @brief   Header file of SRAM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_SRAM_H
-#define STM32L1xx_HAL_SRAM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(FSMC_BANK1)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_fsmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-/** @addtogroup SRAM
-  * @{
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
-  * @{
-  */
-/**
-  * @brief  HAL SRAM State structures definition
-  */
-typedef enum
-{
-  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
-  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
-  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
-  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
-  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
-
-} HAL_SRAM_StateTypeDef;
-
-/**
-  * @brief  SRAM handle Structure definition
-  */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-typedef struct __SRAM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
-{
-  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
-
-  FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
-
-  FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
-
-  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
-
-  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
-
-  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
-  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
-  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
-} SRAM_HandleTypeDef;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SRAM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
-  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
-  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
-  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
-} HAL_SRAM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SRAM Callback pointer definition
-  */
-typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
-typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
-  * @{
-  */
-
-/** @brief Reset SRAM handle state
-  * @param  __HANDLE__ SRAM handle
-  * @retval None
-  */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
-                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
-  * @{
-  */
-
-/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
-                                FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
-  * @{
-  */
-
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
-                                   uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
-                                    uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
-                                    uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
-                                     uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
-                                    uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
-                                     uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
-                                    uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
-                                     uint32_t BufferSize);
-
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
-                                            pSRAM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
-                                               pSRAM_DmaCallbackTypeDef pCallback);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
-  * @{
-  */
-
-/* SRAM Control functions  ****************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
-  * @{
-  */
-
-/* SRAM  State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* FSMC_BANK1 */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h
deleted file mode 100644
index 12b32e2e908..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h
+++ /dev/null
@@ -1,1826 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_TIM_H
-#define STM32L1xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
-                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
-                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
-  * @brief  Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;     /*!< TIM clock filter
-                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  TIM Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
-                                      ETR prescaler must be off */
-  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Master configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
-                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
-                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
-                                        @note When the Master/slave mode is enabled, the effect of
-                                        an event on the trigger input (TRGI) is delayed to allow a
-                                        perfect synchronization between the current timer and its
-                                        slaves (through TRGO). It is not mandatory in case of timer
-                                        synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  SlaveMode;         /*!< Slave mode selection
-                                    This parameter can be a value of @ref TIM_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                    This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
-} HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  TIM Channel States definition
-  */
-typedef enum
-{
-  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
-  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
-  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
-  * @brief  DMA Burst States definition
-  */
-typedef enum
-{
-  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
-  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
-  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
-  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
-  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
-  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
-  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
-                                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
-  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
-  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */
-  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
-  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
-  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
-  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
-  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
-  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
-  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
-  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
-  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
-  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
-  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
-  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
-  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
-  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
-  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
-  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
-  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
-  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
-  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
-  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
-  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
-  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL TIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
-  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
-  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
-  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
-  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
-  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
-  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
-  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
-  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
-  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
-  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
-  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
-  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
-  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
-  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
-  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
-
-  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
-  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
-  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
-  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
-  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
-  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL TIM Callback pointer definition
-  */
-typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       0x00000002U   /*!< OCREF_CLR is connected to OCREF_CLR_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
-  * @{
-  */
-#define TIM_DMABASE_CR1                    0x00000000U
-#define TIM_DMABASE_CR2                    0x00000001U
-#define TIM_DMABASE_SMCR                   0x00000002U
-#define TIM_DMABASE_DIER                   0x00000003U
-#define TIM_DMABASE_SR                     0x00000004U
-#define TIM_DMABASE_EGR                    0x00000005U
-#define TIM_DMABASE_CCMR1                  0x00000006U
-#define TIM_DMABASE_CCMR2                  0x00000007U
-#define TIM_DMABASE_CCER                   0x00000008U
-#define TIM_DMABASE_CNT                    0x00000009U
-#define TIM_DMABASE_PSC                    0x0000000AU
-#define TIM_DMABASE_ARR                    0x0000000BU
-#define TIM_DMABASE_CCR1                   0x0000000DU
-#define TIM_DMABASE_CCR2                   0x0000000EU
-#define TIM_DMABASE_CCR3                   0x0000000FU
-#define TIM_DMABASE_CCR4                   0x00000010U
-#define TIM_DMABASE_DCR                    0x00000012U
-#define TIM_DMABASE_DMAR                   0x00000013U
-#define TIM_DMABASE_OR                     0x00000014U
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source TIM Event Source
-  * @{
-  */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
-#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
-  * @{
-  */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
-  * @{
-  */
-#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
-#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
-#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
-  * @{
-  */
-#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
-#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
-#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
-#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
-#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
-  * @{
-  */
-#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
-#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
-#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
-#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
-#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
-#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
-#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
-#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
-#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
-#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
-#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel TIM Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
-#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
-#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
-#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
-#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
-  * @{
-  */
-#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
-#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
-#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
-#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
-#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
-#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
-#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
-#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
-#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
-#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
-  * @{
-  */
-#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
-#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
-#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
-#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
-#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
-#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
-#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
-#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
-#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
-#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
-#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
-#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
-#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
-#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
-  * @{
-  */
-#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
-#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
-#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
-#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
-#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
-#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
-#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
-#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
-#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
-  * @{
-  */
-#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
-#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
-#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @brief  Reset TIM handle state.
-  * @param  __HANDLE__ TIM handle.
-  * @retval None
-  */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
-                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
-                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
-                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
-                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
-                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
-                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
-                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
-                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
-                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
-                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
-                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
-                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
-                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
-                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
-                                                     } while(0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
-                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
-                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
-                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
-                                                     } while(0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__ TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__ TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-  do { \
-    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
-    { \
-      (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-    } \
-  } while(0)
-
-/** @brief  Enable the specified TIM interrupt.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief  Disable the specified TIM interrupt.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief  Enable the specified DMA request.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __DMA__ specifies the TIM DMA request to enable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief  Disable the specified DMA request.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __DMA__ specifies the TIM DMA request to disable.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: Update DMA request
-  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
-  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
-  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
-  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
-  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief  Check whether the specified TIM interrupt flag is set or not.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __FLAG__ specifies the TIM interrupt flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified TIM interrupt flag.
-  * @param  __HANDLE__ specifies the TIM Handle.
-  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
-  *        This parameter can be one of the following values:
-  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
-  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
-  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
-  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
-  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
-  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
-  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
-  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
-  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
-  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
-  * @brief  Check whether the specified TIM interrupt source is enabled or not.
-  * @param  __HANDLE__ TIM handle
-  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval The state of TIM_IT (SET or RESET).
-  */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
-                                                             == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
-  * @param  __HANDLE__ TIM handle
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_IT_UPDATE: Update interrupt
-  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
-  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
-  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
-  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
-  *            @arg TIM_IT_TRIGGER: Trigger interrupt
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
-  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
-  * @param  __HANDLE__ TIM handle.
-  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
-  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
-  *       or Encoder mode.
-  */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
-  * @brief  Set the TIM Prescaler on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __PRESC__ specifies the Prescaler new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
-  * @brief  Set the TIM Counter Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __COUNTER__ specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Get the TIM Counter Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
-  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __AUTORELOAD__ specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
-  do{                                                    \
-    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Autoreload Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
-  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CKD__ specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
-  * @retval None
-  */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-  do{                                                   \
-    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
-    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
-    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Clock Division value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @retval The clock division can be one of the following values:
-  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
-  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
-  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
-  *         function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-  do{                                                    \
-    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-  } while(0)
-
-/**
-  * @brief  Get the TIM Input Capture prescaler on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval The input capture prescaler can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
-  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__ specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
-   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
-
-/**
-  * @brief  Get the TIM Capture Compare Register value on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
-  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
-   ((__HANDLE__)->Instance->CCR4))
-
-/**
-  * @brief  Set the TIM Output compare preload.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
-   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
-  * @brief  Reset the TIM Output compare preload.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
-
-/**
-  * @brief  Enable fast mode for a given channel.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @note  When fast mode is enabled an active edge on the trigger input acts
-  *        like a compare match on CCx output. Delay to sample the trigger
-  *        input and to activate CCx output is reduced to 3 clock cycles.
-  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
-   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
-
-/**
-  * @brief  Disable fast mode for a given channel.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @note  When fast mode is disabled CCx output behaves normally depending
-  *        on counter and CCRx values even when the trigger is ON. The minimum
-  *        delay to activate CCx output when an active edge occurs on the
-  *        trigger input is 5 clock cycles.
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
-
-/**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__ TIM handle.
-  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
-  *        overflow/underflow generates an update interrupt or DMA request (if
-  *        enabled)
-  * @retval None
-  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
-
-/**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
-  * @param  __HANDLE__ TIM handle.
-  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
-  *        following events generate an update interrupt or DMA request (if
-  *        enabled):
-  *           _ Counter overflow underflow
-  *           _ Setting the UG bit
-  *           _ Update generation through the slave mode controller
-  * @retval None
-  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
-
-/**
-  * @brief  Set the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__ TIM handle.
-  * @param  __CHANNEL__ TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__ Polarity for TIx source
-  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
-  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @retval None
-  */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
-  do{                                                                     \
-    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-  }while(0)
-
-/**
-  * @}
-  */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
-  * @{
-  */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-/**
-  * @}
-  */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)       || \
-                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
-                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
-                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
-                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
-                                   ((__BASE__) == TIM_DMABASE_SR)    || \
-                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
-                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
-                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
-                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
-                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
-                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
-                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
-                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
-                                   ((__BASE__) == TIM_DMABASE_OR))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
-                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
-                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
-                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
-                                            ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
-                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
-                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
-                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
-                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
-                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
-                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
-                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
-                                            ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
-                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
-                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
-                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
-                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
-                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
-                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
-                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
-                                   ((__MODE__) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
-                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
-                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
-                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
-                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
-                                                 ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                               ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
-                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
-   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
-   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
-   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
-   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
-   (__HANDLE__)->ChannelState[3])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
-   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
-  (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \
- } while(0)
-
-/**
-  * @}
-  */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32l1xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
-  *  @brief   Time Base functions
-  * @{
-  */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
-  *  @brief   TIM Output Compare functions
-  * @{
-  */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
-  *  @brief   TIM PWM functions
-  * @{
-  */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
-  *  @brief   TIM Input Capture functions
-  * @{
-  */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
-  *  @brief   TIM One Pulse functions
-  * @{
-  */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
-  *  @brief   TIM Encoder functions
-  * @{
-  */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
-                                            uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
-  *  @brief   IRQ handler management
-  * @{
-  */
-/* Interrupt Handler functions  ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
-  *  @brief   Peripheral Control functions
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
-                                                 uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
-                                                   uint32_t BurstLength,  uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
-                                                  uint32_t  BurstLength, uint32_t  DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
-  *  @brief   TIM Callbacks functions
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
-                                           pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
-  *  @brief  Peripheral State functions
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions  ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-/* End of private functions --------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h
deleted file mode 100644
index c6c8e2f0abe..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_TIM_EX_H
-#define STM32L1xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
-  * @{
-  */
-/* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6.
-         Remap capabilities depend on the device category. As the DMA2 controller is available only in
-         Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s.
-         Cat.3, Cat.4, Cat.5 and Cat.6 devices. */
-#if defined(DMA2)
-#define TIM_TIM2_ITR1_TIM10_OC        (0x00000000)       /*!< TIM2 ITR1 input is connected to TIM10 OC */
-#define TIM_TIM2_ITR1_TIM5_TGO        TIM2_OR_ITR1_RMP   /*!< TIM2 ITR1 input is connected to TIM5 TGO */
-#endif /* DMA2 */
-
-#if defined(DMA2)
-#define TIM_TIM3_ITR2_TIM11_OC        (0x00000000)       /*!< TIM3 ITR2 input is connected to TIM11 OC */
-#define TIM_TIM3_ITR2_TIM5_TGO        TIM2_OR_ITR1_RMP   /*!< TIM3 ITR2 input is connected to TIM5 TGO */
-#endif /* DMA2 */
-
-#if defined(DMA2)
-#define TIM_TIM9_ITR1_TIM3_TGO        (0x00000000)       /*!< TIM9 ITR1 input is connected to TIM3 TGO */
-#define TIM_TIM9_ITR1_TS              TIM9_OR_ITR1_RMP   /*!< TIM9 ITR1 input is connected to touch sensing I/O */
-#endif /* DMA2 */
-#define TIM_TIM9_GPIO                 (0x00000000)       /*!< TIM9 Channel1 is connected to GPIO */
-#define TIM_TIM9_LSE                  TIM_OR_TI1RMP_0    /*!< TIM9 Channel1 is connected to LSE internal clock */
-#define TIM_TIM9_GPIO1                TIM_OR_TI1RMP_1    /*!< TIM9 Channel1 is connected to GPIO */
-#define TIM_TIM9_GPIO2                TIM_OR_TI1RMP      /*!< TIM9 Channel1 is connected to GPIO */
-
-#if defined(DMA2)
-#define TIM_TIM10_TI1RMP              (0x00000000)       /*!< TIM10 Channel 1 depends on TI1_RMP */
-#define TIM_TIM10_RI                  TIM_OR_TI1_RMP_RI  /*!< TIM10 Channel 1 is connected to RI */
-#define TIM_TIM10_ETR_LSE             (0x00000000)       /*!< TIM10 ETR input is connected to LSE clock */
-#define TIM_TIM10_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /*!< TIM10 ETR input is connected to TIM9 TGO */
-#endif /* DMA2 */
-#define TIM_TIM10_GPIO                (0x00000000)       /*!< TIM10 Channel1 is connected to GPIO */
-#define TIM_TIM10_LSI                 TIM_OR_TI1RMP_0    /*!< TIM10 Channel1 is connected to LSI internal clock */
-#define TIM_TIM10_LSE                 TIM_OR_TI1RMP_1    /*!< TIM10 Channel1 is connected to LSE internal clock */
-#define TIM_TIM10_RTC                 TIM_OR_TI1RMP      /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */
-
-#if defined(DMA2)
-#define TIM_TIM11_TI1RMP              (0x00000000)       /*!< TIM11 Channel 1 depends on TI1_RMP */
-#define TIM_TIM11_RI                  TIM_OR_TI1_RMP_RI  /*!< TIM11 Channel 1 is connected to RI */
-#define TIM_TIM11_ETR_LSE             (0x00000000)       /*!< TIM11 ETR input is connected to LSE clock */
-#define TIM_TIM11_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /*!< TIM11 ETR input is connected to TIM9 TGO */
-#endif /* DMA2 */
-#define TIM_TIM11_GPIO                (0x00000000)       /*!< TIM11 Channel1 is connected to GPIO */
-#define TIM_TIM11_MSI                 TIM_OR_TI1RMP_0    /*!< TIM11 Channel1 is connected to MSI internal clock */
-#define TIM_TIM11_HSE_RTC             TIM_OR_TI1RMP_1    /*!< TIM11 Channel1 is connected to HSE_RTC clock */
-#define TIM_TIM11_GPIO1               TIM_OR_TI1RMP      /*!< TIM11 Channel1 is connected to GPIO */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
-  * @{
-  */
-#if defined(DMA2)
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
-  ( (((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO)))  || \
-    (((INSTANCE) == TIM3)  && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO)))  || \
-    (((INSTANCE) == TIM9)  && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2)))                                  || \
-    (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC)))              || \
-    (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1)))               \
-  )
-#else
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
-  ( (((INSTANCE) == TIM9)  && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2)))       || \
-    (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC)))       || \
-    (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1)))    \
-  )
-#endif /* DMA2 */
-
-/**
-  * @}
-  */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  *  @brief    Peripheral Control functions
-  * @{
-  */
-/* Extended Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* End of exported functions -------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h
deleted file mode 100644
index 96dd147a43b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h
+++ /dev/null
@@ -1,881 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_uart.h
-  * @author  MCD Application Team
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_UART_H
-#define __STM32L1xx_HAL_UART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/**
-  * @brief UART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
-                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */
-} UART_InitTypeDef;
-
-/**
-  * @brief HAL UART State structures definition
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains UART state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
-                                                   Value is allowed for gState only */
-} HAL_UART_StateTypeDef;
-
-/**
-  * @brief HAL UART Reception type definition
-  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
-  *        It is expected to admit following values :
-  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
-  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
-  */
-typedef uint32_t HAL_UART_RxTypeTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct __UART_HandleTypeDef
-{
-  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-
-  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
-
-  __IO HAL_UART_RxTypeTypeDef ReceptionType;      /*!< Type of ongoing reception          */
-
-  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
-                                                       and also related to Tx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
-  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
-  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
-  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
-  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
-  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
-  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
-
-  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
-#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL UART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
-  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
-  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
-  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
-  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
-  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
-  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
-  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
-  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
-
-  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
-  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL UART Callback pointer definition
-  */
-typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
-typedef  void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos);   /*!< pointer to a UART Rx Event specific callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
-  * @{
-  */
-
-/** @defgroup UART_Error_Code UART Error Code
-  * @{
-  */
-#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
-#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
-#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
-#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
-#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Word_Length UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_8B                  0x00000000U
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     0x00000000U
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity UART Parity
-  * @{
-  */
-#define UART_PARITY_NONE                    0x00000000U
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */
-#define UART_HWCONTROL_NONE                  0x00000000U
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_State UART State
-  * @{
-  */
-#define UART_STATE_DISABLE                  0x00000000U
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                    0x00000000U
-#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
-  * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_functions  UART Wakeup Functions
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags   UART FLags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (2bits)
-  *                   - 0001: CR1 register
-  *                   - 0010: CR2 register
-  *                   - 0011: CR3 register
-  * @{
-  */
-
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
-  * @{
-  */
-#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
-#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief Reset UART handle gstate & RxState
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief  Flushes the UART DR register
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag
-  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg UART_FLAG_TC:   Transmission Complete flag
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE: Idle Line detection flag
-  *            @arg UART_FLAG_ORE:  Overrun Error flag
-  *            @arg UART_FLAG_NE:   Noise Error flag
-  *            @arg UART_FLAG_FE:   Framing Error flag
-  *            @arg UART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
-  *            @arg UART_FLAG_TC:   Transmission Complete flag.
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clears the UART PE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    UNUSED(tmpreg);                             \
-  } while(0U)
-
-/** @brief  Clears the UART FE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART NE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART ORE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART IDLE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief  Checks whether the specified UART interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__ specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ERR: Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief  Enable CTS flow control
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0U)
-
-/** @brief  Disable CTS flow control
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0U)
-
-/** @brief  Enable RTS flow control
-  *         This macro allows to enable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0U)
-
-/** @brief  Disable RTS flow control
-  *         This macro allows to disable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0U)
-
-/** @brief  Macro to enable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Macro to disable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-/** @brief UART interruptions flag mask
-  *
-  */
-#define UART_IT_MASK                     0x0000FFFFU
-
-#define UART_CR1_REG_INDEX               1U
-#define UART_CR2_REG_INDEX               2U
-#define UART_CR3_REG_INDEX               3U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
-  * @{
-  */
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
-                                     ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
-                                    ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
-                                ((PARITY) == UART_PARITY_EVEN) || \
-                                ((PARITY) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == UART_HWCONTROL_NONE) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS) || \
-                               ((CONTROL) == UART_HWCONTROL_CTS) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
-                              ((STATE) == UART_STATE_ENABLE))
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
-                                        ((SAMPLING) == UART_OVERSAMPLING_8))
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4000000U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h
deleted file mode 100644
index b9d286362c9..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_usart.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_USART_H
-#define __STM32L1xx_HAL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
-  * @{
-  */
-
-/**
-  * @brief USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_Last_Bit */
-} USART_InitTypeDef;
-
-/**
-  * @brief HAL State structures definition
-  */
-typedef enum
-{
-  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized   */
-  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
-  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
-  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */
-  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
-  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */
-} HAL_USART_StateTypeDef;
-
-/**
-  * @brief  USART handle Structure definition
-  */
-typedef struct __USART_HandleTypeDef
-{
-  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
-
-  USART_InitTypeDef             Init;             /*!< Usart communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to Usart Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /*!< Usart Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;      /*!< Usart Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to Usart Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /*!< Usart Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;      /*!< Usart Rx Transfer Counter           */
-
-  DMA_HandleTypeDef             *hdmatx;          /*!< Usart Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /*!< Usart Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef                Lock;            /*!< Locking object                      */
-
-  __IO HAL_USART_StateTypeDef    State;           /*!< Usart communication state           */
-
-  __IO uint32_t                  ErrorCode;       /*!< USART Error code                    */
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
-  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
-  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
-  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
-
-  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
-#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-} USART_HandleTypeDef;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL USART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
-  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
-  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
-  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
-  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
-  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
-  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
-
-  HAL_USART_MSPINIT_CB_ID                 = 0x07U,    /*!< USART MspInit callback ID                 */
-  HAL_USART_MSPDEINIT_CB_ID               = 0x08U     /*!< USART MspDeInit callback ID               */
-
-} HAL_USART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL USART Callback pointer definition
-  */
-typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
-
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_Error_Code USART Error Code
-  * @brief    USART Error Code
-  * @{
-  */
-#define HAL_USART_ERROR_NONE             0x00000000U   /*!< No error                */
-#define HAL_USART_ERROR_PE               0x00000001U   /*!< Parity error            */
-#define HAL_USART_ERROR_NE               0x00000002U   /*!< Noise error             */
-#define HAL_USART_ERROR_FE               0x00000004U   /*!< Frame error             */
-#define HAL_USART_ERROR_ORE              0x00000008U   /*!< Overrun error           */
-#define HAL_USART_ERROR_DMA              0x00000010U   /*!< DMA transfer error      */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U    /*!< Invalid Callback error */
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup USART_Word_Length USART Word Length
-  * @{
-  */
-#define USART_WORDLENGTH_8B          0x00000000U
-#define USART_WORDLENGTH_9B          ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
-  * @{
-  */
-#define USART_STOPBITS_1             0x00000000U
-#define USART_STOPBITS_0_5           ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2             ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5           ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Parity USART Parity
-  * @{
-  */
-#define USART_PARITY_NONE            0x00000000U
-#define USART_PARITY_EVEN            ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD             ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Mode USART Mode
-  * @{
-  */
-#define USART_MODE_RX                ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX                ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX             ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock USART Clock
-  * @{
-  */
-#define USART_CLOCK_DISABLE          0x00000000U
-#define USART_CLOCK_ENABLE           ((uint32_t)USART_CR2_CLKEN)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
-  * @{
-  */
-#define USART_POLARITY_LOW           0x00000000U
-#define USART_POLARITY_HIGH          ((uint32_t)USART_CR2_CPOL)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
-  * @{
-  */
-#define USART_PHASE_1EDGE            0x00000000U
-#define USART_PHASE_2EDGE            ((uint32_t)USART_CR2_CPHA)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit USART Last Bit
-  * @{
-  */
-#define USART_LASTBIT_DISABLE        0x00000000U
-#define USART_LASTBIT_ENABLE         ((uint32_t)USART_CR2_LBCL)
-/**
-  * @}
-  */
-
-/** @defgroup USART_NACK_State USART NACK State
-  * @{
-  */
-#define USART_NACK_ENABLE            ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE           0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup USART_Flags USART Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define USART_FLAG_TXE               ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC                ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE              ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE              ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE               ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE                ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE                ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE                ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  * @{
-  */
-#define USART_IT_PE                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define USART_IT_TXE                 ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define USART_IT_TC                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define USART_IT_RXNE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define USART_IT_IDLE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define USART_IT_ERR                 ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @brief Reset USART handle state
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
-                                                      (__HANDLE__)->State = HAL_USART_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback = NULL;        \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
-                                                    } while(0U)
-#else
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/** @brief  Check whether the specified USART flag is set or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg USART_FLAG_TC:   Transmission Complete flag
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg USART_FLAG_IDLE: Idle Line detection flag
-  *            @arg USART_FLAG_ORE:  Overrun Error flag
-  *            @arg USART_FLAG_NE:   Noise Error flag
-  *            @arg USART_FLAG_FE:   Framing Error flag
-  *            @arg USART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the specified USART pending flags.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg USART_FLAG_TC:   Transmission Complete flag.
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)    \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    UNUSED(tmpreg);                             \
-  } while(0U)
-
-/** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enables or disables the specified USART interrupts.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:   Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_PE:   Parity Error interrupt
-  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                             ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                             ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-/** @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __IT__ specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:  Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  *            @arg USART_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-
-/** @brief  Macro to enable the USART's one bit sample method
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
-
-/** @brief  Macro to disable the USART's one bit sample method
-  * @param  __HANDLE__ specifies the USART Handle.
-  * @retval None
-  */
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable USART
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief  Disable USART
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_USART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup USART_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
-  * @{
-  */
-/** @brief USART interruptions flag mask
-  *
-  */
-#define USART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-#define USART_CR1_REG_INDEX          1U
-#define USART_CR2_REG_INDEX          2U
-#define USART_CR3_REG_INDEX          3U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
-  * @{
-  */
-#define IS_USART_NACK_STATE(NACK)    (((NACK) == USART_NACK_ENABLE) || \
-                                      ((NACK) == USART_NACK_DISABLE))
-
-#define IS_USART_LASTBIT(LASTBIT)    (((LASTBIT) == USART_LASTBIT_DISABLE) || \
-                                      ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_PHASE(CPHA)         (((CPHA) == USART_PHASE_1EDGE) || \
-                                      ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_POLARITY(CPOL)      (((CPOL) == USART_POLARITY_LOW) || \
-                                      ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_CLOCK(CLOCK)        (((CLOCK) == USART_CLOCK_DISABLE) || \
-                                      ((CLOCK) == USART_CLOCK_ENABLE))
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
-                                      ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS)  (((STOPBITS) == USART_STOPBITS_1) || \
-                                      ((STOPBITS) == USART_STOPBITS_0_5) || \
-                                      ((STOPBITS) == USART_STOPBITS_1_5) || \
-                                      ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY)      (((PARITY) == USART_PARITY_NONE) || \
-                                      ((PARITY) == USART_PARITY_EVEN) || \
-                                      ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE)          ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
-
-#define IS_USART_BAUDRATE(BAUDRATE)  ((BAUDRATE) <= 4000000U)
-
-#define USART_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(2U*(_BAUD_)))
-
-#define USART_DIVMANT(_PCLK_, _BAUD_)  (USART_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define USART_DIVFRAQ(_PCLK_, _BAUD_)  ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
-
-  /* UART BRR = mantissa + overflow + fraction
-              = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-              
-#define USART_BRR(_PCLK_, _BAUD_)      (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
-                                        ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
-                                         (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h
deleted file mode 100644
index 6714088d126..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_wwdg.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_wwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of WWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_HAL_WWDG_H
-#define STM32L1xx_HAL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup WWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  WWDG Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
-                               This parameter can be a value of @ref WWDG_Prescaler */
-
-  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
-                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
-                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
-                               This parameter can be a value of @ref WWDG_EWI_Mode */
-
-} WWDG_InitTypeDef;
-
-/**
-  * @brief  WWDG handle Structure definition
-  */
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-typedef struct __WWDG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-{
-  WWDG_TypeDef      *Instance;  /*!< Register base address */
-
-  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-  void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);                  /*!< WWDG Early WakeUp Interrupt callback */
-
-  void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg);              /*!< WWDG Msp Init callback */
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-} WWDG_HandleTypeDef;
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL WWDG common Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_WWDG_EWI_CB_ID          = 0x00U,    /*!< WWDG EWI callback ID */
-  HAL_WWDG_MSPINIT_CB_ID      = 0x01U,    /*!< WWDG MspInit callback ID */
-} HAL_WWDG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL WWDG Callback pointer definition
-  */
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
-
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
-  * @{
-  */
-#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
-  * @brief WWDG Flag definition
-  * @{
-  */
-#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
-  * @{
-  */
-#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
-  * @{
-  */
-#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
-#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
-  * @{
-  */
-#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
-                                             ((__MODE__) == WWDG_EWI_DISABLE))
-/**
-  * @}
-  */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the WWDG peripheral.
-  * @param  __HANDLE__  WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
-  * @brief  Enable the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the selected WWDG interrupt has occurred or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the it to check.
-  *        This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief  Clear the WWDG interrupt pending bits.
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified WWDG flag is set or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the WWDG's pending flags.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval None
-  */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
-  * @param  __HANDLE__  WWDG Handle.
-  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
-  * @retval state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
-                                                pWWDG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h
deleted file mode 100644
index f42d49ce20e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h
+++ /dev/null
@@ -1,5166 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_adc.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_ADC_H
-#define __STM32L1xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (ADC1)
-
-/** @defgroup ADC_LL ADC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/* Internal mask for ADC group regular sequencer:                             */
-/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
-/* - sequencer register offset                                                */
-/* - sequencer rank bits position into the selected register                  */
-
-/* Internal register offset for ADC group regular sequencer configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET                 0x00000000U
-#define ADC_SQR2_REGOFFSET                 0x00000100U
-#define ADC_SQR3_REGOFFSET                 0x00000200U
-#define ADC_SQR4_REGOFFSET                 0x00000300U
-#define ADC_SQR5_REGOFFSET                 0x00000400U
-
-#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET | ADC_SQR5_REGOFFSET)
-#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group regular sequencer bits information to be inserted  */
-/* into ADC group regular sequencer ranks literals definition.                */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */
-#define ADC_REG_RANK_17_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */
-#define ADC_REG_RANK_18_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */
-#define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */
-#define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */
-#define ADC_REG_RANK_21_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */
-#define ADC_REG_RANK_22_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */
-#define ADC_REG_RANK_23_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */
-#define ADC_REG_RANK_24_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */
-#define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */
-#define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */
-#define ADC_REG_RANK_27_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */
-#if defined(ADC_SQR1_SQ28)
-#define ADC_REG_RANK_28_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */
-#endif
-
-
-
-/* Internal mask for ADC group injected sequencer:                            */
-/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
-/* - data register offset                                                     */
-/* - offset register offset                                                   */
-/* - sequencer rank bits position into the selected register                  */
-
-/* Internal register offset for ADC group injected data register */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET                 0x00000000U
-#define ADC_JDR2_REGOFFSET                 0x00000100U
-#define ADC_JDR3_REGOFFSET                 0x00000200U
-#define ADC_JDR4_REGOFFSET                 0x00000300U
-
-/* Internal register offset for ADC group injected offset configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JOFR1_REGOFFSET                0x00000000U
-#define ADC_JOFR2_REGOFFSET                0x00001000U
-#define ADC_JOFR3_REGOFFSET                0x00002000U
-#define ADC_JOFR4_REGOFFSET                0x00003000U
-
-#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
-#define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
-#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group injected sequencer bits information to be inserted */
-/* into ADC group injected sequencer ranks literals definition.               */
-#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
-#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
-#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
-#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
-
-
-
-/* Internal mask for ADC group regular trigger:                               */
-/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
-/* - regular trigger source                                                   */
-/* - regular trigger edge                                                     */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible                  */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
-                                             ((ADC_CR2_EXTSEL)                            >> (4U * 1U)) | \
-                                             ((ADC_CR2_EXTSEL)                            >> (4U * 2U)) | \
-                                             ((ADC_CR2_EXTSEL)                            >> (4U * 3U)))
-
-/* Mask containing trigger edge masks for each of possible                    */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 1U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 2U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U)))
-
-/* Definition of ADC group regular trigger bits information.                  */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
-
-
-
-/* Internal mask for ADC group injected trigger:                              */
-/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
-/* - injected trigger source                                                  */
-/* - injected trigger edge                                                    */
-#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible                  */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
-                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 1U)) | \
-                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 2U)) | \
-                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 3U)))
-
-/* Mask containing trigger edge masks for each of possible                    */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
-#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
-                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 1U)) | \
-                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 2U)) | \
-                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U)))
-
-/* Definition of ADC group injected trigger bits information.                 */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
-
-
-
-
-
-
-/* Internal mask for ADC channel:                                             */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
-/* - channel identifier defined by number                                     */
-/* - channel differentiation between external channels (connected to          */
-/*   GPIO pins) and internal channels (connected to internal paths)           */
-/* - channel sampling time defined by SMPRx register offset                   */
-/*   and SMPx bits positions into SMPRx register                              */
-#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
-#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
-
-/* Internal register offset for ADC channel sampling time configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET                0x00000000U
-#define ADC_SMPR2_REGOFFSET                0x02000000U
-#define ADC_SMPR3_REGOFFSET                0x04000000U
-#if defined(ADC_SMPR0_SMP31)
-#define ADC_SMPR0_REGOFFSET                0x28000000U   /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET)
-#else
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET)
-#endif /* ADC_SMPR0_SMP31 */
-
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
-
-/* Definition of channels ID number information to be inserted into           */
-/* channels literals definition.                                              */
-#define ADC_CHANNEL_0_NUMBER               0x00000000U
-#define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )
-#define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )
-#define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
-#define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )
-#define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_18_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_19_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_20_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2                                    )
-#define ADC_CHANNEL_21_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_22_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_23_NUMBER              (ADC_CR1_AWDCH_4                   | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_24_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                                                      )
-#define ADC_CHANNEL_25_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_26_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
-#if defined(ADC_SMPR0_SMP31)
-#define ADC_CHANNEL_27_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_28_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
-#define ADC_CHANNEL_29_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_30_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
-#define ADC_CHANNEL_31_NUMBER              (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#endif /* ADC_SMPR0_SMP31 */
-
-/* Definition of channels sampling time information to be inserted into       */
-/* channels literals definition.                                              */
-#define ADC_CHANNEL_0_SMP                  (ADC_SMPR3_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */
-#define ADC_CHANNEL_1_SMP                  (ADC_SMPR3_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */
-#define ADC_CHANNEL_2_SMP                  (ADC_SMPR3_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */
-#define ADC_CHANNEL_3_SMP                  (ADC_SMPR3_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */
-#define ADC_CHANNEL_4_SMP                  (ADC_SMPR3_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */
-#define ADC_CHANNEL_5_SMP                  (ADC_SMPR3_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */
-#define ADC_CHANNEL_6_SMP                  (ADC_SMPR3_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */
-#define ADC_CHANNEL_7_SMP                  (ADC_SMPR3_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */
-#define ADC_CHANNEL_8_SMP                  (ADC_SMPR3_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */
-#define ADC_CHANNEL_9_SMP                  (ADC_SMPR3_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */
-#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
-#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
-#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
-#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
-#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
-#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
-#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
-#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
-#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
-#define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */
-#define ADC_CHANNEL_20_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */
-#define ADC_CHANNEL_21_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */
-#define ADC_CHANNEL_22_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */
-#define ADC_CHANNEL_23_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */
-#define ADC_CHANNEL_24_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */
-#define ADC_CHANNEL_25_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */
-#define ADC_CHANNEL_26_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */
-#if defined(ADC_SMPR0_SMP31)
-#define ADC_CHANNEL_27_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */
-#define ADC_CHANNEL_28_SMP                 (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */
-#define ADC_CHANNEL_29_SMP                 (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */
-#define ADC_CHANNEL_30_SMP                 (ADC_SMPR0_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */
-#define ADC_CHANNEL_31_SMP                 (ADC_SMPR0_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */
-#endif /* ADC_SMPR0_SMP31 */
-
-
-/* Internal mask for ADC analog watchdog:                                     */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
-/* (concatenation of multiple bits used in different analog watchdogs,        */
-/* (feature of several watchdogs not available on all STM32 families)).       */
-/* - analog watchdog 1: monitored channel defined by number,                  */
-/*   selection of ADC group (ADC groups regular and-or injected).             */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET              0x00000000U
-
-#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U
-#define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U
-#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
-
-
-/* ADC registers bits positions */
-#define ADC_CR1_RES_BITOFFSET_POS          (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
-#define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
-
-
-/* ADC internal channels related definitions */
-/* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR                   ((uint16_t*) VREFINT_CAL_ADDR_CMSIS)     /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF                   ( 3000U)                                 /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
-/* Temperature sensor */
-#if defined (TEMPSENSOR_CAL1_ADDR_CMSIS)
-#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) TEMPSENSOR_CAL1_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) TEMPSENSOR_CAL2_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#endif /* TEMPSENSOR_CAL1_ADDR_CMSIS */
-#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG          ( 3000U)                                 /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Driver macro reserved for internal use: isolate bits with the
-  *         selected mask and shift them to the register LSB
-  *         (shift mask on register position bit 0).
-  * @param  __BITS__ Bits in register 32 bits
-  * @param  __MASK__ Mask in register 32 bits
-  * @retval Bits in register 32 bits
-  */
-#define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
-  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
-  * @brief  Driver macro reserved for internal use: set a pointer to
-  *         a register from a register basis from which an offset
-  *         is applied.
-  * @param  __REG__ Register basis from which the offset is applied.
-  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
-  * @retval Pointer to register address
-  */
-#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of ADC common parameters
-  *         and multimode
-  *         (all ADC instances belonging to the same ADC common instance).
-  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
-  *         is conditioned to ADC instances state (all ADC instances
-  *         sharing the same ADC common instance):
-  *         All ADC instances sharing the same ADC common instance must be
-  *         disabled.
-  */
-typedef struct
-{
-  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
-                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
-                                             @note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
-                                                   Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
-                                             @note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
-                                                   must be respected:
-                                                    - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
-                                                    - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
-                                                   Refer to reference manual.
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
-
-} LL_ADC_CommonInitTypeDef;
-
-/**
-  * @brief  Structure definition of some features of ADC instance.
-  * @note   These parameters have an impact on ADC scope: ADC instance.
-  *         Affects both group regular and group injected (availability
-  *         of ADC group injected depends on STM32 families).
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  */
-typedef struct
-{
-  uint32_t Resolution;                  /*!< Set ADC resolution.
-                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
-
-  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
-                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
-
-  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
-                                             This parameter can be a concatenation of a value of @ref ADC_LL_EC_LP_MODE_AUTOWAIT and a value of @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerModeAutoWait() and @ref LL_ADC_SetLowPowerModeAutoPowerOff(). */
-
-  uint32_t SequencersScanMode;          /*!< Set ADC scan selection.
-                                             This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
-  * @brief  Structure definition of some features of ADC group regular.
-  * @note   These parameters have an impact on ADC scope: ADC group regular.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "REG").
-  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  */
-typedef struct
-{
-  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
-                                             @note On this STM32 serie, setting of external trigger edge is performed
-                                                   using function @ref LL_ADC_REG_StartConversionExtTrig().
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
-
-  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
-                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
-  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
-                                             @note This parameter has an effect only if group regular sequencer is enabled
-                                                   (scan length of 2 ranks or more).
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
-  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
-                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
-  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
-                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
-  * @brief  Structure definition of some features of ADC group injected.
-  * @note   These parameters have an impact on ADC scope: ADC group injected.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "INJ").
-  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  */
-typedef struct
-{
-  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
-                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
-                                             @note On this STM32 serie, setting of external trigger edge is performed
-                                                   using function @ref LL_ADC_INJ_StartConversionExtTrig().
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
-
-  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
-                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
-                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
-
-  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
-                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
-                                             @note This parameter has an effect only if group injected sequencer is enabled
-                                                   (scan length of 2 ranks or more).
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
-
-  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
-                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
-                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
-
-} LL_ADC_INJ_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
-  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
-  * @{
-  */
-#define LL_ADC_FLAG_ADRDY                  ADC_SR_ADONS       /*!< ADC flag ADC instance ready */
-#define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */
-#define LL_ADC_FLAG_EOCS                   ADC_SR_EOC         /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_FLAG_OVR                    ADC_SR_OVR         /*!< ADC flag ADC group regular overrun */
-#define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */
-#define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
-  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
-  * @{
-  */
-#define LL_ADC_IT_EOCS                     ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_IT_OVR                      ADC_CR1_OVRIE      /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
-  * @{
-  */
-/* List of ADC registers intended to be used (most commonly) with             */
-/* DMA transfer.                                                              */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
-#define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
-  * @{
-  */
-#define LL_ADC_CLOCK_ASYNC_DIV1            0x00000000U                                           /*!< ADC asynchronous clock without prescaler */
-#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_ADCPRE_0)                                    /*!< ADC asynchronous clock with prescaler division by 2   */
-#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_ADCPRE_1)                                    /*!< ADC asynchronous clock with prescaler division by 4   */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
-  * @{
-  */
-/* Note: Other measurement paths to internal channels may be available        */
-/*       (connections to other peripherals).                                  */
-/*       If they are not listed below, they do not require any specific       */
-/*       path enable. In this case, Access to measurement path is done        */
-/*       only by selecting the corresponding ADC internal channel.            */
-#define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement pathes all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
-  * @{
-  */
-#define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */
-#define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */
-#define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
-  * @{
-  */
-#define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT  ADC instance - Low power mode auto wait (auto delay)
-  * @{
-  */
-#define LL_ADC_LP_AUTOWAIT_NONE               0x00000000U                                        /*!< ADC low power mode auto wait not activated */
-#define LL_ADC_LP_AUTOWAIT                    (                                  ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). */
-#define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES   (                 ADC_CR2_DELS_1                 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles */
-#define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES  (                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles */
-#define LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES  (ADC_CR2_DELS_2                                  ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 31 APB clock cycles */
-#define LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES  (ADC_CR2_DELS_2                  | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 63 APB clock cycles */
-#define LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1                 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 127 APB clock cycles */
-#define LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 255 APB clock cycles */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF  ADC instance - Low power mode auto power-off
-  * @{
-  */
-#define LL_ADC_LP_AUTOPOWEROFF_NONE                 0x00000000U                                  /*!< ADC low power mode auto power-off not activated */
-#define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE           (ADC_CR1_PDI)                                /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) */
-#define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE       (ADC_CR1_PDD)                                /*!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
-#define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI | ADC_CR1_PDD)                  /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
-  * @{
-  */
-#define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
-#define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
-/**
-  * @}
-  */
-
-#if defined(ADC_CR2_CFG)
-/** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank
-  * @{
-  */
-#define LL_ADC_CHANNELS_BANK_A             0x00000000U   /*!< ADC channels bank A */
-#define LL_ADC_CHANNELS_BANK_B             (ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
-  * @{
-  */
-#define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
-  * @{
-  */
-#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 . Direct (fast) channel. */
-#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 . Direct (fast) channel. */
-#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 . Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10. Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11. Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12. Channel different in bank A and bank B. */
-#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_20                  (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_21                  (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_22                  (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22. Direct (fast) channel. */
-#define LL_ADC_CHANNEL_23                  (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23. Direct (fast) channel. */
-#define LL_ADC_CHANNEL_24                  (ADC_CHANNEL_24_NUMBER | ADC_CHANNEL_24_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN24. Direct (fast) channel. */
-#define LL_ADC_CHANNEL_25                  (ADC_CHANNEL_25_NUMBER | ADC_CHANNEL_25_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN25. Direct (fast) channel. */
-#define LL_ADC_CHANNEL_26                  (ADC_CHANNEL_26_NUMBER | ADC_CHANNEL_26_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN26. Direct (fast) channel. */
-#if defined(ADC_SMPR0_SMP31)
-#define LL_ADC_CHANNEL_27                  (ADC_CHANNEL_27_NUMBER | ADC_CHANNEL_27_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN27. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#define LL_ADC_CHANNEL_28                  (ADC_CHANNEL_28_NUMBER | ADC_CHANNEL_28_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN28. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#define LL_ADC_CHANNEL_29                  (ADC_CHANNEL_29_NUMBER | ADC_CHANNEL_29_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN29. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#define LL_ADC_CHANNEL_30                  (ADC_CHANNEL_30_NUMBER | ADC_CHANNEL_30_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN30. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#define LL_ADC_CHANNEL_31                  (ADC_CHANNEL_31_NUMBER | ADC_CHANNEL_31_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN31. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
-#endif /* ADC_SMPR0_SMP31 */
-#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_VCOMP               (LL_ADC_CHANNEL_26 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
-#if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)
-#define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_8 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#if defined(OPAMP_CSR_OPA3PD)
-#define LL_ADC_CHANNEL_VOPAMP3             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#endif /* OPAMP_CSR_OPA3PD */
-#endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
-  * @{
-  */
-#define LL_ADC_REG_TRIG_SOFTWARE           0x00000000U                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH3       (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM9_CH2       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                             /*!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM9_TRGO      (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
-  * @{
-  */
-#define LL_ADC_REG_TRIG_EXT_RISING         (                  ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CR2_EXTEN_1                  )     /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
-* @{
-*/
-#define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
-  * @{
-  */
-#define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
-  * @{
-  */
-#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000U    /*!< ADC flag EOC (end of unitary conversion) selected */
-#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
-  * @{
-  */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
-  * @{
-  */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
-#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
-  * @{
-  */
-#define LL_ADC_REG_RANK_1                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
-#define LL_ADC_REG_RANK_2                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
-#define LL_ADC_REG_RANK_3                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
-#define LL_ADC_REG_RANK_4                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
-#define LL_ADC_REG_RANK_5                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
-#define LL_ADC_REG_RANK_6                  (ADC_SQR5_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
-#define LL_ADC_REG_RANK_7                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
-#define LL_ADC_REG_RANK_8                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
-#define LL_ADC_REG_RANK_9                  (ADC_SQR4_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
-#define LL_ADC_REG_RANK_10                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
-#define LL_ADC_REG_RANK_11                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
-#define LL_ADC_REG_RANK_12                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
-#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
-#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
-#define LL_ADC_REG_RANK_15                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
-#define LL_ADC_REG_RANK_16                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
-#define LL_ADC_REG_RANK_17                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_17_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 17 */
-#define LL_ADC_REG_RANK_18                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_18_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 18 */
-#define LL_ADC_REG_RANK_19                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_19_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 19 */
-#define LL_ADC_REG_RANK_20                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_20_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 20 */
-#define LL_ADC_REG_RANK_21                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_21_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 21 */
-#define LL_ADC_REG_RANK_22                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_22_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 22 */
-#define LL_ADC_REG_RANK_23                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_23_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 23 */
-#define LL_ADC_REG_RANK_24                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_24_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 24 */
-#define LL_ADC_REG_RANK_25                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_25_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 25 */
-#define LL_ADC_REG_RANK_26                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_26_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 26 */
-#define LL_ADC_REG_RANK_27                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_27_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 27 */
-#if defined(ADC_SQR1_SQ28)
-#define LL_ADC_REG_RANK_28                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_28_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 28 */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
-  * @{
-  */
-#define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000U                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */
-#define LL_ADC_INJ_TRIG_EXT_TIM9_CH1       (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO      (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM10_CH1      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
-  * @{
-  */
-#define LL_ADC_INJ_TRIG_EXT_RISING         (                   ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to rising edge */
-#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_CR2_JEXTEN_1                   )   /*!< ADC group injected conversion trigger polarity set to falling edge */
-#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
-* @{
-*/
-#define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
-#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
-  * @{
-  */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
-  * @{
-  */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */
-#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
-  * @{
-  */
-#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
-#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
-#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
-#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
-  * @{
-  */
-#define LL_ADC_SAMPLINGTIME_4CYCLES        0x00000000U                                              /*!< Sampling time 4 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_9CYCLES        (ADC_SMPR3_SMP0_0)                                       /*!< Sampling time 9 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_16CYCLES       (ADC_SMPR3_SMP0_1)                                       /*!< Sampling time 16 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_24CYCLES       (ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)                    /*!< Sampling time 24 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_48CYCLES       (ADC_SMPR3_SMP0_2)                                       /*!< Sampling time 48 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_96CYCLES       (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)                    /*!< Sampling time 96 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_192CYCLES      (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)                    /*!< Sampling time 192 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_384CYCLES      (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 384 ADC clock cycles */
-/**
-  * @}
-  */
-
-#if defined(COMP_CSR_FCH3)
-/** @defgroup ADC_LL_EC_CHANNEL_ROUTING_LIST  Channel - Routing channels list
-  * @{
-  */
-#define LL_ADC_CHANNEL_3_ROUTING           (COMP_CSR_FCH3)  /*!< ADC channel 3 routing. Used as ADC direct channel (fast channel) if OPAMP1 is in power down mode. */
-#define LL_ADC_CHANNEL_8_ROUTING           (COMP_CSR_FCH8)  /*!< ADC channel 8 routing. Used as ADC direct channel (fast channel) if OPAMP2 is in power down mode. */
-#define LL_ADC_CHANNEL_13_ROUTING          (COMP_CSR_RCH13) /*!< ADC channel 13 routing. Used as ADC re-routed channel if OPAMP3 is in power down mode. Otherwise, channel 13 is connected to OPAMP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is available on STM32L1 Cat.4 only). */
-/**
-  * @}
-  */
-  
-/** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION  Channel - Routing selection
-  * @{
-  */
-#define LL_ADC_CHANNEL_ROUTING_DEFAULT     0x00000000U  /*!< ADC channel routing default: slow channel */
-#define LL_ADC_CHANNEL_ROUTING_DIRECT      0x00000001U  /*!< ADC channel routing direct: fast channel. */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
-  * @{
-  */
-#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
-  * @{
-  */
-#define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
-#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_20_REG          ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_20_INJ          ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_20_REG_INJ      ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_21_REG          ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_21_INJ          ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_21_REG_INJ      ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_22_REG          ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_22_INJ          ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_22_REG_INJ      ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_23_REG          ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_23_INJ          ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_23_REG_INJ      ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_24_REG          ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_24_INJ          ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_24_REG_INJ      ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_25_REG          ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_25_INJ          ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_25_REG_INJ      ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_26_REG          ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_26_INJ          ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_26_REG_INJ      ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by either group regular or injected */
-#if defined(ADC_SMPR0_SMP31)
-#define LL_ADC_AWD_CHANNEL_27_REG          ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_27_INJ          ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_27_REG_INJ      ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_28_REG          ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_28_INJ          ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_28_REG_INJ      ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_29_REG          ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_29_INJ          ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_29_REG_INJ      ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_30_REG          ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_30_INJ          ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_30_REG_INJ      ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_31_REG          ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_31_INJ          ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#define LL_ADC_AWD_CHANNEL_31_REG_INJ      ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.  */
-#endif /* ADC_SMPR0_SMP31 */
-#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VCOMP_REG            ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VCOMP_INJ            ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VCOMP_REG_INJ        ((LL_ADC_CHANNEL_VCOMP      & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
-#if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)
-#define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#if defined(OPAMP_CSR_OPA3PD)
-#define LL_ADC_AWD_CH_VOPAMP3_REG          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP3_INJ          ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#define LL_ADC_AWD_CH_VOPAMP3_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP3    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
-#endif /* OPAMP_CSR_OPA3PD */
-#endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
-  * @{
-  */
-#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
-  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-  
-/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
-/*       not timeout values.                                                  */
-/*       Timeout values for ADC operations are dependent to device clock      */
-/*       configuration (system clock versus ADC clock),                       */
-/*       and therefore must be defined in user application.                   */
-/*       Indications for estimation of ADC timeout delays, for this           */
-/*       STM32 serie:                                                         */
-/*       - ADC enable time: maximum delay is 3.5us                            */
-/*         (refer to device datasheet, parameter "tSTAB")                     */
-/*       - ADC conversion time: duration depending on ADC clock and ADC       */
-/*         configuration.                                                     */
-/*         (refer to device reference manual, section "Timing")               */
-
-/* Delay for internal voltage reference stabilization time.                   */
-/* Delay set to maximum value (refer to device datasheet,                     */
-/* parameter "TADC_BUF").                                                     */
-/* Unit: us                                                                   */
-#define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay for temperature sensor stabilization time.                           */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSTART").                                                       */
-/* Unit: us                                                                   */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for internal voltage reference stabilization time */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
-  * @{
-  */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in ADC register
-  * @param  __INSTANCE__ ADC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in ADC register
-  * @param  __INSTANCE__ ADC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to get ADC channel number in decimal format
-  *         from literals LL_ADC_CHANNEL_x.
-  * @note   Example:
-  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
-  *           will return decimal number "4".
-  * @note   The input can be a value from functions where a channel
-  *         number is returned, either defined with number
-  *         or with bitfield (only one bit must be set).
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval Value between Min_Data=0 and Max_Data=18
-  */
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
-  (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
-
-/**
-  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
-  *         from number in decimal format.
-  * @note   Example:
-  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
-  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
-  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
-  *         (6) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  */
-#if defined(ADC_SMPR0_SMP31)
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                                  \
-  (((__DECIMAL_NB__) <= 9U)                                                                                             \
-    ? (                                                                                                                 \
-       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |                \
-       (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))                 \
-      )                                                                                                                 \
-      :                                                                                                                 \
-      (((__DECIMAL_NB__) <= 19U)                                                                                        \
-        ? (                                                                                                             \
-           ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \
-           (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \
-          )                                                                                                             \
-          :                                                                                                             \
-          (((__DECIMAL_NB__) <= 28U)                                                                                    \
-            ? (                                                                                                         \
-               ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
-               (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
-              )                                                                                                         \
-              :                                                                                                         \
-              (                                                                                                         \
-               ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
-               (ADC_SMPR0_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
-              )                                                                                                         \
-          )                                                                                                             \
-      )                                                                                                                 \
-  )
-#else
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                                  \
-  (((__DECIMAL_NB__) <= 9U)                                                                                             \
-    ? (                                                                                                                 \
-       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |                \
-       (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))                 \
-      )                                                                                                                 \
-      :                                                                                                                 \
-      (((__DECIMAL_NB__) <= 19U)                                                                                        \
-        ? (                                                                                                             \
-           ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \
-           (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \
-          )                                                                                                             \
-          :                                                                                                             \
-          (                                                                                                             \
-           ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |            \
-           (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))      \
-          )                                                                                                             \
-      )                                                                                                                 \
-  )
-#endif /* ADC_SMPR0_SMP31 */
-
-/**
-  * @brief  Helper macro to determine whether the selected channel
-  *         corresponds to literal definitions of driver.
-  * @note   The different literal definitions of ADC channels are:
-  *         - ADC internal channel:
-  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
-  *         - ADC external channel (channel connected to a GPIO pin):
-  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
-  * @note   The channel parameter must be a value defined from literal
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
-  *         must not be a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
-  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
-  */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
-  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
-
-/**
-  * @brief  Helper macro to convert a channel defined from parameter
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         to its equivalent parameter definition of a ADC external channel
-  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
-  * @note   The channel parameter can be, additionally to a value
-  *         defined from parameter definition of a ADC internal channel
-  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         a value defined from parameter definition of
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is returned
-  *         from ADC registers.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0
-  *         @arg @ref LL_ADC_CHANNEL_1
-  *         @arg @ref LL_ADC_CHANNEL_2
-  *         @arg @ref LL_ADC_CHANNEL_3
-  *         @arg @ref LL_ADC_CHANNEL_4
-  *         @arg @ref LL_ADC_CHANNEL_5
-  *         @arg @ref LL_ADC_CHANNEL_6
-  *         @arg @ref LL_ADC_CHANNEL_7
-  *         @arg @ref LL_ADC_CHANNEL_8
-  *         @arg @ref LL_ADC_CHANNEL_9
-  *         @arg @ref LL_ADC_CHANNEL_10
-  *         @arg @ref LL_ADC_CHANNEL_11
-  *         @arg @ref LL_ADC_CHANNEL_12
-  *         @arg @ref LL_ADC_CHANNEL_13
-  *         @arg @ref LL_ADC_CHANNEL_14
-  *         @arg @ref LL_ADC_CHANNEL_15
-  *         @arg @ref LL_ADC_CHANNEL_16
-  *         @arg @ref LL_ADC_CHANNEL_17
-  *         @arg @ref LL_ADC_CHANNEL_18
-  */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
-  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
-  * @brief  Helper macro to determine whether the internal channel
-  *         selected is available on the ADC instance selected.
-  * @note   The channel parameter must be a value defined from parameter
-  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
-  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
-  *         must not be a value defined from parameter definition of
-  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __ADC_INSTANCE__ ADC instance
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
-  *         Value "1" if the internal channel selected is available on the ADC instance selected.
-  */
-#if defined (OPAMP_CSR_OPA3PD)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  (                                                                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)      ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3)                                  \
-  )
-#elif defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD)
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  (                                                                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)      ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)                                  \
-  )
-#else
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  (                                                                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
-    ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP)                                    \
-  )
-#endif
-
-/**
-  * @brief  Helper macro to define ADC analog watchdog parameter:
-  *         define a single channel to monitor with analog watchdog
-  *         from sequencer channel and groups definition.
-  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
-  *         Example:
-  *           LL_ADC_SetAnalogWDMonitChannels(
-  *             ADC1, LL_ADC_AWD1,
-  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
-  *         (6) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  * @param  __GROUP__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_GROUP_REGULAR
-  *         @arg @ref LL_ADC_GROUP_INJECTED
-  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG            (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_INJ            (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ        (3)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ      (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ      (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ      (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
-  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
-    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
-      :                                                                                                   \
-      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
-       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
-         :                                                                                                \
-         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
-  )
-
-/**
-  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
-  *         or low in function of ADC resolution, when ADC resolution is
-  *         different of 12 bits.
-  * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
-  *         Example, with a ADC resolution of 8 bits, to set the value of
-  *         analog watchdog threshold high (on 8 bits):
-  *           LL_ADC_SetAnalogWDThresholds
-  *            (< ADCx param >,
-  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
-  *            );
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
-  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
-
-/**
-  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
-  *         or low in function of ADC resolution, when ADC resolution is 
-  *         different of 12 bits.
-  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
-  *         Example, with a ADC resolution of 8 bits, to get the value of
-  *         analog watchdog threshold high (on 8 bits):
-  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
-  *            (LL_ADC_RESOLUTION_8B,
-  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
-  *            );
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
-  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
-
-/**
-  * @brief  Helper macro to select the ADC common instance
-  *         to which is belonging the selected ADC instance.
-  * @note   ADC common register instance can be used for:
-  *         - Set parameters common to several ADC instances
-  *         - Multimode (for devices with several ADC instances)
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @param  __ADCx__ ADC instance
-  * @retval ADC common register instance
-  */
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
-  (ADC1_COMMON)
-  
-/**
-  * @brief  Helper macro to check if all ADC instances sharing the same
-  *         ADC common instance are disabled.
-  * @note   This check is required by functions with setting conditioned to
-  *         ADC state:
-  *         All ADC instances of the ADC common group must be disabled.
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @note   On devices with only 1 ADC common instance, parameter of this macro
-  *         is useless and can be ignored (parameter kept for compatibility
-  *         with devices featuring several ADC common instances).
-  * @param  __ADCXY_COMMON__ ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Value "0" if all ADC instances sharing the same ADC common instance
-  *         are disabled.
-  *         Value "1" if at least one ADC instance sharing the same ADC common instance
-  *         is enabled.
-  */
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
-  LL_ADC_IsEnabled(ADC1)
-
-/**
-  * @brief  Helper macro to define the ADC conversion data full-scale digital
-  *         value corresponding to the selected ADC resolution.
-  * @note   ADC conversion data full-scale corresponds to voltage range
-  *         determined by analog voltage references Vref+ and Vref-
-  *         (refer to reference manual).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
-
-/**
-  * @brief  Helper macro to convert the ADC conversion data from
-  *         a resolution to another resolution.
-  * @param  __DATA__ ADC conversion data to be converted 
-  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data to the requested resolution
-  */
-#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
-  (((__DATA__)                                                                 \
-    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))     \
-   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))        \
-  )
-
-/**
-  * @brief  Helper macro to calculate the voltage (unit: mVolt)
-  *         corresponding to a ADC conversion data (unit: digital value).
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
-  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *                       (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
-                                      __ADC_DATA__,\
-                                      __ADC_RESOLUTION__)                      \
-  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
-   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
-  )
-
-/**
-  * @brief  Helper macro to calculate analog reference voltage (Vref+)
-  *         (unit: mVolt) from ADC conversion data of internal voltage
-  *         reference VrefInt.
-  * @note   Computation is using VrefInt calibration value
-  *         stored in system memory for each device during production.
-  * @note   This voltage depends on user board environment: voltage level
-  *         connected to pin Vref+.
-  *         On devices with small package, the pin Vref+ is not present
-  *         and internally bonded to pin Vdda.
-  * @note   On this STM32 serie, calibration data of internal voltage reference
-  *         VrefInt corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         internal voltage reference VrefInt.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *         of internal voltage reference VrefInt (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Analog reference voltage (unit: mV)
-  */
-#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
-                                         __ADC_RESOLUTION__)                   \
-  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
-    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
-                                       (__ADC_RESOLUTION__),                   \
-                                       LL_ADC_RESOLUTION_12B)                  \
-  )
-
-/* Note: On device STM32L100, calibration parameters TS_CAL1 and TS_CAL2 are not available. */
-/*       Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
-/*       Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().        */
-#if defined(TEMPSENSOR_CAL1_ADDR_CMSIS)
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor calibration values
-  *         stored in system memory for each device during production.
-  * @note   Calculation formula:
-  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
-  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
-  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
-  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
-  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
-  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
-  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL1 (calibrated in factory)
-  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL2 (calibrated in factory)
-  *         Caution: Calculation relevancy under reserve that calibration
-  *                  parameters are correct (address and data).
-  *                  To calculate temperature using temperature sensor
-  *                  datasheet typical values (generic values less, therefore
-  *                  less accurate than calibrated values),
-  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   On this STM32 serie, calibration data of temperature sensor
-  *         corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         temperature sensor.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
-  *                                 temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
-  *                                 sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
-                                  __TEMPSENSOR_ADC_DATA__,\
-                                  __ADC_RESOLUTION__)                              \
-  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
-                                                    (__ADC_RESOLUTION__),          \
-                                                    LL_ADC_RESOLUTION_12B)         \
-                   * (__VREFANALOG_VOLTAGE__))                                     \
-                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
-        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
-     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
-    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
-   ) + TEMPSENSOR_CAL1_TEMP                                                        \
-  )
-#endif /* TEMPSENSOR_CAL1_ADDR_CMSIS */
-
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor typical values
-  *         (refer to device datasheet).
-  * @note   Calculation formula:
-  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
-  *                         / Avg_Slope + CALx_TEMP
-  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
-  *                                   (unit: digital value)
-  *                Avg_Slope        = temperature sensor slope
-  *                                   (unit: uV/Degree Celsius)
-  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
-  *                                   temperature CALx_TEMP (unit: mV)
-  *         Caution: Calculation relevancy under reserve the temperature sensor
-  *                  of the current device has characteristics in line with
-  *                  datasheet typical values.
-  *                  If temperature sensor calibration values are available on
-  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
-  *                  temperature calculation will be more accurate using
-  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   ADC measurement data must correspond to a resolution of 12bits
-  *         (full scale digital value 4095). If not the case, the data must be
-  *         preliminarily rescaled to an equivalent resolution of 12 bits.
-  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
-  *                                       On STM32L1, refer to device datasheet parameter "Avg_Slope".
-  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
-  *                                       On STM32L1, refer to device datasheet parameter "V110" (corresponding to TS_CAL2).
-  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
-  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
-                                             __TEMPSENSOR_TYP_CALX_V__,\
-                                             __TEMPSENSOR_CALX_TEMP__,\
-                                             __VREFANALOG_VOLTAGE__,\
-                                             __TEMPSENSOR_ADC_DATA__,\
-                                             __ADC_RESOLUTION__)               \
-  ((( (                                                                        \
-       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
-                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
-                 * 1000)                                                       \
-       -                                                                       \
-       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
-                 * 1000)                                                       \
-      )                                                                        \
-    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
-   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
-  )
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
-  * @{
-  */
-/* Note: LL ADC functions to set DMA transfer are located into sections of    */
-/*       configuration of ADC instance, groups and multimode (if available):  */
-/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
-
-/**
-  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
-  *         ADC register address from ADC instance and a list of ADC registers
-  *         intended to be used (most commonly) with DMA transfer.
-  * @note   These ADC registers are data registers:
-  *         when ADC conversion data is available in ADC data registers,
-  *         ADC generates a DMA transfer request.
-  * @note   This macro is intended to be used with LL DMA driver, refer to
-  *         function "LL_DMA_ConfigAddresses()".
-  *         Example:
-  *           LL_DMA_ConfigAddresses(DMA1,
-  *                                  LL_DMA_CHANNEL_1,
-  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
-  *                                  (uint32_t)&< array or variable >,
-  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
-  * @note   For devices with several ADC: in multimode, some devices
-  *         use a different data register outside of ADC instance scope
-  *         (common data register). This macro manages this register difference,
-  *         only ADC instance has to be set as parameter.
-  * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
-  * @param  ADCx ADC instance
-  * @param  Register This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
-  * @retval ADC register address
-  */
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
-{
-  /* Retrieve address of register DR */
-  return (uint32_t)&(ADCx->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
-  * @{
-  */
-
-/**
-  * @brief  Set parameter common to several ADC: Clock source and prescaler.
-  * @note   On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
-  *         Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
-  * @note   On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
-  *         must be respected:
-  *         - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
-  *         - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
-  *         Refer to reference manual.
-  * @rmtoll CCR      ADCPRE         LL_ADC_SetCommonClock
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  CommonClock This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
-{
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
-}
-
-/**
-  * @brief  Get parameter common to several ADC: Clock source and prescaler.
-  * @rmtoll CCR      ADCPRE         LL_ADC_GetCommonClock
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
-  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
-}
-
-/**
-  * @brief  Set parameter common to several ADC: measurement path to internal
-  *         channels (VrefInt, temperature sensor, ...).
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
-  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
-  * @note   Stabilization time of measurement path to internal channel:
-  *         After enabling internal paths, before starting ADC conversion,
-  *         a delay is required for internal voltage reference and
-  *         temperature sensor stabilization time.
-  *         Refer to device datasheet.
-  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
-  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
-  * @note   ADC internal channel sampling time constraint:
-  *         For ADC conversion of internal channels,
-  *         a sampling time minimum value is required.
-  *         Refer to device datasheet.
-  * @rmtoll CCR      TSVREFE        LL_ADC_SetCommonPathInternalCh
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  PathInternal This parameter can be a combination of the following values:
-  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
-  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
-{
-  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE, PathInternal);
-}
-
-/**
-  * @brief  Get parameter common to several ADC: measurement path to internal
-  *         channels (VrefInt, temperature sensor, ...).
-  * @note   One or several values can be selected.
-  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
-  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
-  * @rmtoll CCR      TSVREFE        LL_ADC_GetCommonPathInternalCh
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Returned value can be a combination of the following values:
-  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
-  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
-  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
-  * @{
-  */
-
-/**
-  * @brief  Set ADC resolution.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CR1      RES            LL_ADC_SetResolution
-  * @param  ADCx ADC instance
-  * @param  Resolution This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
-{
-  MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
-}
-
-/**
-  * @brief  Get ADC resolution.
-  *         Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CR1      RES            LL_ADC_GetResolution
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_12B
-  *         @arg @ref LL_ADC_RESOLUTION_10B
-  *         @arg @ref LL_ADC_RESOLUTION_8B
-  *         @arg @ref LL_ADC_RESOLUTION_6B
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
-}
-
-/**
-  * @brief  Set ADC conversion data alignment.
-  * @note   Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
-  * @param  ADCx ADC instance
-  * @param  DataAlignment This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
-  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
-}
-
-/**
-  * @brief  Get ADC conversion data alignment.
-  * @note   Refer to reference manual for alignments formats
-  *         dependencies to ADC resolutions.
-  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
-  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
-}
-
-/**
-  * @brief  Set ADC low power mode auto wait.
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait": Dynamic low power mode,
-  *           ADC conversions occurrences are limited to the minimum necessary
-  *           in order to reduce power consumption.
-  *           New ADC conversion starts only when the previous
-  *           unitary conversion data (for ADC group regular)
-  *           or previous sequence conversions data (for ADC group injected)
-  *           has been retrieved by user software.
-  *           In the meantime, ADC remains idle: does not performs any
-  *           other conversion.
-  *           This mode allows to automatically adapt the ADC conversions
-  *           triggers to the speed of the software that reads the data.
-  *           Moreover, this avoids risk of overrun for low frequency
-  *           applications.
-  *           How to use this low power mode:
-  *           - Do not use with interruption or DMA since these modes
-  *             have to clear immediately the EOC flag to free the
-  *             IRQ vector sequencer.
-  *           - Do use with polling: 1. Start conversion,
-  *             2. Later on, when conversion data is needed: poll for end of
-  *             conversion  to ensure that conversion is completed and
-  *             retrieve ADC conversion data. This will trig another
-  *             ADC conversion start.
-  *         - ADC low power mode "auto power-off":
-  *           refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
-  * @note   With ADC low power mode "auto wait", the ADC conversion data read
-  *         is corresponding to previous ADC conversion start, independently
-  *         of delay during which ADC was idle.
-  *         Therefore, the ADC conversion data may be outdated: does not
-  *         correspond to the current voltage level on the selected
-  *         ADC channel.
-  * @rmtoll CR2      DELS           LL_ADC_SetLowPowerModeAutoWait
-  * @param  ADCx ADC instance
-  * @param  LowPowerModeAutoWait This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_NONE
-  *         @arg @ref LL_ADC_LP_AUTOWAIT
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetLowPowerModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoWait)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_DELS, LowPowerModeAutoWait);
-}
-
-/**
-  * @brief  Get ADC low power mode auto wait.
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait": Dynamic low power mode,
-  *           ADC conversions occurrences are limited to the minimum necessary
-  *           in order to reduce power consumption.
-  *           New ADC conversion starts only when the previous
-  *           unitary conversion data (for ADC group regular)
-  *           or previous sequence conversions data (for ADC group injected)
-  *           has been retrieved by user software.
-  *           In the meantime, ADC remains idle: does not performs any
-  *           other conversion.
-  *           This mode allows to automatically adapt the ADC conversions
-  *           triggers to the speed of the software that reads the data.
-  *           Moreover, this avoids risk of overrun for low frequency
-  *           applications.
-  *           How to use this low power mode:
-  *           - Do not use with interruption or DMA since these modes
-  *             have to clear immediately the EOC flag to free the
-  *             IRQ vector sequencer.
-  *           - Do use with polling: 1. Start conversion,
-  *             2. Later on, when conversion data is needed: poll for end of
-  *             conversion  to ensure that conversion is completed and
-  *             retrieve ADC conversion data. This will trig another
-  *             ADC conversion start.
-  *         - ADC low power mode "auto power-off":
-  *           refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
-  * @note   With ADC low power mode "auto wait", the ADC conversion data read
-  *         is corresponding to previous ADC conversion start, independently
-  *         of delay during which ADC was idle.
-  *         Therefore, the ADC conversion data may be outdated: does not
-  *         correspond to the current voltage level on the selected
-  *         ADC channel.
-  * @rmtoll CR2      DELS           LL_ADC_GetLowPowerModeAutoWait
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_NONE
-  *         @arg @ref LL_ADC_LP_AUTOWAIT
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
-  *         @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoWait(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DELS));
-}
-
-/**
-  * @brief  Set ADC low power mode auto power-off.
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait":
-  *           refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
-  *         - ADC low power mode "auto power-off":
-  *           the ADC automatically powers-off after a conversion and
-  *           automatically wakes up when a new conversion is triggered
-  *           (with startup time between trigger and start of sampling).
-  *           This feature can be combined with low power mode "auto wait".
-  * @rmtoll CR1      PDI            LL_ADC_GetLowPowerModeAutoPowerOff\n
-  *         CR1      PDD            LL_ADC_GetLowPowerModeAutoPowerOff
-  * @param  ADCx ADC instance
-  * @param  LowPowerModeAutoPowerOff This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoPowerOff)
-{
-  MODIFY_REG(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD), LowPowerModeAutoPowerOff);
-}
-
-/**
-  * @brief  Get ADC low power mode auto power-off.
-  * @note   Description of ADC low power modes:
-  *         - ADC low power mode "auto wait":
-  *           refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
-  *         - ADC low power mode "auto power-off":
-  *           the ADC automatically powers-off after a conversion and
-  *           automatically wakes up when a new conversion is triggered
-  *           (with startup time between trigger and start of sampling).
-  *           This feature can be combined with low power mode "auto wait".
-  * @rmtoll CR1      PDI            LL_ADC_GetLowPowerModeAutoPowerOff\n
-  *         CR1      PDD            LL_ADC_GetLowPowerModeAutoPowerOff
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
-  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD)));
-}
-
-/**
-  * @brief  Set ADC sequencers scan mode, for all ADC groups
-  *         (group regular, group injected).
-  * @note  According to sequencers scan mode :
-  *         - If disabled: ADC conversion is performed in unitary conversion
-  *           mode (one channel converted, that defined in rank 1).
-  *           Configuration of sequencers of all ADC groups
-  *           (sequencer scan length, ...) is discarded: equivalent to
-  *           scan length of 1 rank.
-  *         - If enabled: ADC conversions are performed in sequence conversions
-  *           mode, according to configuration of sequencers of
-  *           each ADC group (sequencer scan length, ...).
-  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
-  *           and to function @ref LL_ADC_INJ_SetSequencerLength().
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on either groups regular or injected.
-  * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode
-  * @param  ADCx ADC instance
-  * @param  ScanMode This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
-{
-  MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
-}
-
-/**
-  * @brief  Get ADC sequencers scan mode, for all ADC groups
-  *         (group regular, group injected).
-  * @note  According to sequencers scan mode :
-  *         - If disabled: ADC conversion is performed in unitary conversion
-  *           mode (one channel converted, that defined in rank 1).
-  *           Configuration of sequencers of all ADC groups
-  *           (sequencer scan length, ...) is discarded: equivalent to
-  *           scan length of 1 rank.
-  *         - If enabled: ADC conversions are performed in sequence conversions
-  *           mode, according to configuration of sequencers of
-  *           each ADC group (sequencer scan length, ...).
-  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
-  *           and to function @ref LL_ADC_INJ_SetSequencerLength().
-  * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
-}
-
-#if defined(ADC_CR2_CFG)
-/**
-  * @brief  Set ADC channels bank.
-  * @note   Bank selected applies to ADC scope, on all channels
-  *         (independently of channel mapped on ADC group regular
-  *         or group injected).
-  * @note   Banks availability depends on devices categories.
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         ADC state:
-  *         ADC must be disabled or enabled without conversion on going
-  *         on either groups regular or injected.
-  * @rmtoll CR2      ADC_CFG        LL_ADC_SetChannelsBank
-  * @param  ADCx ADC instance
-  * @param  ChannelsBank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNELS_BANK_A
-  *         @arg @ref LL_ADC_CHANNELS_BANK_B
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetChannelsBank(ADC_TypeDef *ADCx, uint32_t ChannelsBank)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_CFG, ChannelsBank);
-}
-
-/**
-  * @brief  Get ADC channels bank.
-  * @note   Bank selected applies to ADC scope, on all channels 
-  *         (independently of channel mapped on ADC group regular
-  *         or group injected).
-  * @note   Banks availability depends on devices categories.
-  * @rmtoll CR2      ADC_CFG        LL_ADC_GetChannelsBank
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNELS_BANK_A
-  *         @arg @ref LL_ADC_CHANNELS_BANK_B
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelsBank(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CFG));
-}
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
-  * @{
-  */
-
-/**
-  * @brief  Set ADC group regular conversion trigger source:
-  *         internal (SW start) or from external IP (timer event,
-  *         external interrupt line).
-  * @note   On this STM32 serie, setting of external trigger edge is performed
-  *         using function @ref LL_ADC_REG_StartConversionExtTrig().
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource\n
-  *         CR2      EXTEN          LL_ADC_REG_SetTriggerSource
-  * @param  ADCx ADC instance
-  * @param  TriggerSource This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
-{
-/* Note: On this STM32 serie, ADC group regular external trigger edge        */
-/*       is used to perform a ADC conversion start.                           */
-/*       This function does not set external trigger edge.                    */
-/*       This feature is set using function                                   */
-/*       @ref LL_ADC_REG_StartConversionExtTrig().                            */
-  MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger source:
-  *         internal (SW start) or from external IP (timer event,
-  *         external interrupt line).
-  * @note   To determine whether group regular trigger source is
-  *         internal (SW start) or external, without detail
-  *         of which peripheral is selected as external trigger,
-  *         (equivalent to 
-  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
-  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource\n
-  *         CR2      EXTEN          LL_ADC_REG_GetTriggerSource
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
-{
-  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
-  
-  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
-  /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}.                             */
-  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
-  
-  /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL           */
-  /* to match with triggers literals definition.                              */
-  return ((TriggerSource
-           & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
-          | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
-         );
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger source internal (SW start)
-            or external.
-  * @note   In case of group regular trigger source set to external trigger,
-  *         to determine which peripheral is selected as external trigger,
-  *         use function @ref LL_ADC_REG_GetTriggerSource().
-  * @rmtoll CR2      EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
-  * @param  ADCx ADC instance
-  * @retval Value "0" if trigger source external trigger
-  *         Value "1" if trigger source SW start.
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
-}
-
-/**
-  * @brief  Get ADC group regular conversion trigger polarity.
-  * @note   Applicable only for trigger source set to external trigger.
-  * @note   On this STM32 serie, setting of external trigger edge is performed
-  *         using function @ref LL_ADC_REG_StartConversionExtTrig().
-  * @rmtoll CR2      EXTEN          LL_ADC_REG_GetTriggerEdge
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
-}
-
-
-/**
-  * @brief  Set ADC group regular sequencer length and scan direction.
-  * @note   Description of ADC group regular sequencer features:
-  *         - For devices with sequencer fully configurable
-  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
-  *           sequencer length and each rank affectation to a channel
-  *           are configurable.
-  *           This function performs configuration of:
-  *           - Sequence length: Number of ranks in the scan sequence.
-  *           - Sequence direction: Unless specified in parameters, sequencer
-  *             scan direction is forward (from rank 1 to rank n).
-  *           Sequencer ranks are selected using
-  *           function "LL_ADC_REG_SetSequencerRanks()".
-  *         - For devices with sequencer not fully configurable
-  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
-  *           sequencer length and each rank affectation to a channel
-  *           are defined by channel number.
-  *           This function performs configuration of:
-  *           - Sequence length: Number of ranks in the scan sequence is
-  *             defined by number of channels set in the sequence,
-  *             rank of each channel is fixed by channel HW number.
-  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  *           - Sequence direction: Unless specified in parameters, sequencer
-  *             scan direction is forward (from lowest channel number to
-  *             highest channel number).
-  *           Sequencer ranks are selected using
-  *           function "LL_ADC_REG_SetSequencerChannels()".
-  * @note   On this STM32 serie, group regular sequencer configuration
-  *         is conditioned to ADC instance sequencer mode.
-  *         If ADC instance sequencer mode is disabled, sequencers of
-  *         all groups (group regular, group injected) can be configured
-  *         but their execution is disabled (limited to rank 1).
-  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
-  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
-  *         ADC conversion on only 1 channel.
-  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
-  * @param  ADCx ADC instance
-  * @param  SequencerNbRanks This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
-{
-  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
-}
-
-/**
-  * @brief  Get ADC group regular sequencer length and scan direction.
-  * @note   Description of ADC group regular sequencer features:
-  *         - For devices with sequencer fully configurable
-  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
-  *           sequencer length and each rank affectation to a channel
-  *           are configurable.
-  *           This function retrieves:
-  *           - Sequence length: Number of ranks in the scan sequence.
-  *           - Sequence direction: Unless specified in parameters, sequencer
-  *             scan direction is forward (from rank 1 to rank n).
-  *           Sequencer ranks are selected using
-  *           function "LL_ADC_REG_SetSequencerRanks()".
-  *         - For devices with sequencer not fully configurable
-  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
-  *           sequencer length and each rank affectation to a channel
-  *           are defined by channel number.
-  *           This function retrieves:
-  *           - Sequence length: Number of ranks in the scan sequence is
-  *             defined by number of channels set in the sequence,
-  *             rank of each channel is fixed by channel HW number.
-  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-  *           - Sequence direction: Unless specified in parameters, sequencer
-  *             scan direction is forward (from lowest channel number to
-  *             highest channel number).
-  *           Sequencer ranks are selected using
-  *           function "LL_ADC_REG_SetSequencerChannels()".
-  * @note   On this STM32 serie, group regular sequencer configuration
-  *         is conditioned to ADC instance sequencer mode.
-  *         If ADC instance sequencer mode is disabled, sequencers of
-  *         all groups (group regular, group injected) can be configured
-  *         but their execution is disabled (limited to rank 1).
-  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
-  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
-  *         ADC conversion on only 1 channel.
-  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
-}
-
-/**
-  * @brief  Set ADC group regular sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @note   It is not possible to enable both ADC group regular 
-  *         continuous mode and sequencer discontinuous mode.
-  * @note   It is not possible to enable both ADC auto-injected mode
-  *         and ADC group regular sequencer discontinuous mode.
-  * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n
-  *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont
-  * @param  ADCx ADC instance
-  * @param  SeqDiscont This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
-{
-  MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
-}
-
-/**
-  * @brief  Get ADC group regular sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n
-  *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
-  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
-}
-
-/**
-  * @brief  Set ADC group regular sequence: channel on the selected
-  *         scan sequence rank.
-  * @note   This function performs configuration of:
-  *         - Channels ordering into each rank of scan sequence:
-  *           whatever channel can be placed into whatever rank.
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         fully configurable: sequencer length and each rank
-  *         affectation to a channel are configurable.
-  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @rmtoll SQR5     SQ1            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR5     SQ2            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR5     SQ3            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR5     SQ4            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR5     SQ5            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR5     SQ6            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ7            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ8            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ9            LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ10           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ11           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR4     SQ12           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ15           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ16           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ17           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR3     SQ18           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ19           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ20           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ21           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ22           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ23           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR2     SQ24           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR1     SQ25           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR1     SQ26           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR1     SQ27           LL_ADC_REG_SetSequencerRanks\n
-  *         SQR1     SQ28           LL_ADC_REG_SetSequencerRanks
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_RANK_1
-  *         @arg @ref LL_ADC_REG_RANK_2
-  *         @arg @ref LL_ADC_REG_RANK_3
-  *         @arg @ref LL_ADC_REG_RANK_4
-  *         @arg @ref LL_ADC_REG_RANK_5
-  *         @arg @ref LL_ADC_REG_RANK_6
-  *         @arg @ref LL_ADC_REG_RANK_7
-  *         @arg @ref LL_ADC_REG_RANK_8
-  *         @arg @ref LL_ADC_REG_RANK_9
-  *         @arg @ref LL_ADC_REG_RANK_10
-  *         @arg @ref LL_ADC_REG_RANK_11
-  *         @arg @ref LL_ADC_REG_RANK_12
-  *         @arg @ref LL_ADC_REG_RANK_13
-  *         @arg @ref LL_ADC_REG_RANK_14
-  *         @arg @ref LL_ADC_REG_RANK_15
-  *         @arg @ref LL_ADC_REG_RANK_16
-  *         @arg @ref LL_ADC_REG_RANK_17
-  *         @arg @ref LL_ADC_REG_RANK_18
-  *         @arg @ref LL_ADC_REG_RANK_19
-  *         @arg @ref LL_ADC_REG_RANK_20
-  *         @arg @ref LL_ADC_REG_RANK_21
-  *         @arg @ref LL_ADC_REG_RANK_22
-  *         @arg @ref LL_ADC_REG_RANK_23
-  *         @arg @ref LL_ADC_REG_RANK_24
-  *         @arg @ref LL_ADC_REG_RANK_25
-  *         @arg @ref LL_ADC_REG_RANK_26
-  *         @arg @ref LL_ADC_REG_RANK_27
-  *         @arg @ref LL_ADC_REG_RANK_28 (1)
-  *         
-  *         (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
-{
-  /* Set bits with content of parameter "Channel" with bits position          */
-  /* in register and register position depending on parameter "Rank".         */
-  /* Parameters "Rank" and "Channel" are used with masks because containing   */
-  /* other bits reserved for other purpose.                                   */
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
-  
-  MODIFY_REG(*preg,
-             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
-             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
-}
-
-/**
-  * @brief  Get ADC group regular sequence: channel on the selected
-  *         scan sequence rank.
-  * @note   On this STM32 serie, ADC group regular sequencer is
-  *         fully configurable: sequencer length and each rank
-  *         affectation to a channel are configurable.
-  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   Usage of the returned channel number:
-  *         - To reinject this channel into another function LL_ADC_xxx:
-  *           the returned channel number is only partly formatted on definition
-  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
-  *           with parts of literals LL_ADC_CHANNEL_x or using
-  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Then the selected literal LL_ADC_CHANNEL_x can be used
-  *           as parameter for another function.
-  *         - To get the channel number in decimal format:
-  *           process the returned value with the helper macro
-  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  * @rmtoll SQR5     SQ1            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR5     SQ2            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR5     SQ3            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR5     SQ4            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR5     SQ5            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR5     SQ6            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ7            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ8            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ9            LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ10           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ11           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR4     SQ12           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ15           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ16           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ17           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR3     SQ18           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ19           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ20           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ21           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ22           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ23           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR2     SQ24           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR1     SQ25           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR1     SQ26           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR1     SQ27           LL_ADC_REG_GetSequencerRanks\n
-  *         SQR1     SQ28           LL_ADC_REG_GetSequencerRanks
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_RANK_1
-  *         @arg @ref LL_ADC_REG_RANK_2
-  *         @arg @ref LL_ADC_REG_RANK_3
-  *         @arg @ref LL_ADC_REG_RANK_4
-  *         @arg @ref LL_ADC_REG_RANK_5
-  *         @arg @ref LL_ADC_REG_RANK_6
-  *         @arg @ref LL_ADC_REG_RANK_7
-  *         @arg @ref LL_ADC_REG_RANK_8
-  *         @arg @ref LL_ADC_REG_RANK_9
-  *         @arg @ref LL_ADC_REG_RANK_10
-  *         @arg @ref LL_ADC_REG_RANK_11
-  *         @arg @ref LL_ADC_REG_RANK_12
-  *         @arg @ref LL_ADC_REG_RANK_13
-  *         @arg @ref LL_ADC_REG_RANK_14
-  *         @arg @ref LL_ADC_REG_RANK_15
-  *         @arg @ref LL_ADC_REG_RANK_16
-  *         @arg @ref LL_ADC_REG_RANK_17
-  *         @arg @ref LL_ADC_REG_RANK_18
-  *         @arg @ref LL_ADC_REG_RANK_19
-  *         @arg @ref LL_ADC_REG_RANK_20
-  *         @arg @ref LL_ADC_REG_RANK_21
-  *         @arg @ref LL_ADC_REG_RANK_22
-  *         @arg @ref LL_ADC_REG_RANK_23
-  *         @arg @ref LL_ADC_REG_RANK_24
-  *         @arg @ref LL_ADC_REG_RANK_25
-  *         @arg @ref LL_ADC_REG_RANK_26
-  *         @arg @ref LL_ADC_REG_RANK_27
-  *         @arg @ref LL_ADC_REG_RANK_28 (1)
-  *         
-  *         (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
-  *         (6) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
-  
-  return (uint32_t) (READ_BIT(*preg,
-                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
-                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
-                    );
-}
-
-/**
-  * @brief  Set ADC continuous conversion mode on ADC group regular.
-  * @note   Description of ADC continuous conversion mode:
-  *         - single mode: one conversion per trigger
-  *         - continuous mode: after the first trigger, following
-  *           conversions launched successively automatically.
-  * @note   It is not possible to enable both ADC group regular 
-  *         continuous mode and sequencer discontinuous mode.
-  * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode
-  * @param  ADCx ADC instance
-  * @param  Continuous This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_CONV_SINGLE
-  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
-}
-
-/**
-  * @brief  Get ADC continuous conversion mode on ADC group regular.
-  * @note   Description of ADC continuous conversion mode:
-  *         - single mode: one conversion per trigger
-  *         - continuous mode: after the first trigger, following
-  *           conversions launched successively automatically.
-  * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_CONV_SINGLE
-  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
-}
-
-/**
-  * @brief  Set ADC group regular conversion data transfer: no transfer or
-  *         transfer by DMA, and DMA requests mode.
-  * @note   If transfer by DMA selected, specifies the DMA requests
-  *         mode:
-  *         - Limited mode (One shot mode): DMA transfer requests are stopped
-  *           when number of DMA data transfers (number of
-  *           ADC conversions) is reached.
-  *           This ADC mode is intended to be used with DMA mode non-circular.
-  *         - Unlimited mode: DMA transfer requests are unlimited,
-  *           whatever number of DMA data transfers (number of
-  *           ADC conversions).
-  *           This ADC mode is intended to be used with DMA mode circular.
-  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
-  *         mode non-circular:
-  *         when DMA transfers size will be reached, DMA will stop transfers of
-  *         ADC conversions data ADC will raise an overrun error
-  *        (overrun flag and interruption if enabled).
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_ADC_DMA_GetRegAddr().
-  * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer\n
-  *         CR2      DDS            LL_ADC_REG_SetDMATransfer
-  * @param  ADCx ADC instance
-  * @param  DMATransfer This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
-}
-
-/**
-  * @brief  Get ADC group regular conversion data transfer: no transfer or
-  *         transfer by DMA, and DMA requests mode.
-  * @note   If transfer by DMA selected, specifies the DMA requests
-  *         mode:
-  *         - Limited mode (One shot mode): DMA transfer requests are stopped
-  *           when number of DMA data transfers (number of
-  *           ADC conversions) is reached.
-  *           This ADC mode is intended to be used with DMA mode non-circular.
-  *         - Unlimited mode: DMA transfer requests are unlimited,
-  *           whatever number of DMA data transfers (number of
-  *           ADC conversions).
-  *           This ADC mode is intended to be used with DMA mode circular.
-  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
-  *         mode non-circular:
-  *         when DMA transfers size will be reached, DMA will stop transfers of
-  *         ADC conversions data ADC will raise an overrun error
-  *         (overrun flag and interruption if enabled).
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_ADC_DMA_GetRegAddr().
-  * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer\n
-  *         CR2      DDS            LL_ADC_REG_GetDMATransfer
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
-  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
-}
-
-/**
-  * @brief  Specify which ADC flag between EOC (end of unitary conversion)
-  *         or EOS (end of sequence conversions) is used to indicate
-  *         the end of conversion.
-  * @note   This feature is aimed to be set when using ADC with
-  *         programming model by polling or interruption
-  *         (programming model by DMA usually uses DMA interruptions
-  *         to indicate end of conversion and data transfer).
-  * @note   For ADC group injected, end of conversion (flag&IT) is raised
-  *         only at the end of the sequence.
-  * @rmtoll CR2      EOCS           LL_ADC_REG_SetFlagEndOfConversion
-  * @param  ADCx ADC instance
-  * @param  EocSelection This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
-  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
-{
-  MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
-}
-
-/**
-  * @brief  Get which ADC flag between EOC (end of unitary conversion)
-  *         or EOS (end of sequence conversions) is used to indicate
-  *         the end of conversion.
-  * @rmtoll CR2      EOCS           LL_ADC_REG_GetFlagEndOfConversion
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
-  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
-  * @{
-  */
-
-/**
-  * @brief  Set ADC group injected conversion trigger source:
-  *         internal (SW start) or from external IP (timer event,
-  *         external interrupt line).
-  * @note   On this STM32 serie, setting of external trigger edge is performed
-  *         using function @ref LL_ADC_INJ_StartConversionExtTrig().
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
-  *         CR2      JEXTEN         LL_ADC_INJ_SetTriggerSource
-  * @param  ADCx ADC instance
-  * @param  TriggerSource This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
-{
-/* Note: On this STM32 serie, ADC group injected external trigger edge       */
-/*       is used to perform a ADC conversion start.                           */
-/*       This function does not set external trigger edge.                    */
-/*       This feature is set using function                                   */
-/*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */
-  MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
-}
-
-/**
-  * @brief  Get ADC group injected conversion trigger source:
-  *         internal (SW start) or from external IP (timer event,
-  *         external interrupt line).
-  * @note   To determine whether group injected trigger source is
-  *         internal (SW start) or external, without detail
-  *         of which peripheral is selected as external trigger,
-  *         (equivalent to 
-  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
-  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
-  * @note   Availability of parameters of trigger sources from timer 
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
-  *         CR2      JEXTEN         LL_ADC_INJ_GetTriggerSource
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
-{
-  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
-  
-  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
-  /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}.                            */
-  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
-  
-  /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL         */
-  /* to match with triggers literals definition.                              */
-  return ((TriggerSource
-           & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
-          | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
-         );
-}
-
-/**
-  * @brief  Get ADC group injected conversion trigger source internal (SW start)
-            or external
-  * @note   In case of group injected trigger source set to external trigger,
-  *         to determine which peripheral is selected as external trigger,
-  *         use function @ref LL_ADC_INJ_GetTriggerSource.
-  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
-  * @param  ADCx ADC instance
-  * @retval Value "0" if trigger source external trigger
-  *         Value "1" if trigger source SW start.
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
-}
-
-/**
-  * @brief  Get ADC group injected conversion trigger polarity.
-  *         Applicable only for trigger source set to external trigger.
-  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_GetTriggerEdge
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
-}
-
-/**
-  * @brief  Set ADC group injected sequencer length and scan direction.
-  * @note   This function performs configuration of:
-  *         - Sequence length: Number of ranks in the scan sequence.
-  *         - Sequence direction: Unless specified in parameters, sequencer
-  *           scan direction is forward (from rank 1 to rank n).
-  * @note   On this STM32 serie, group injected sequencer configuration
-  *         is conditioned to ADC instance sequencer mode.
-  *         If ADC instance sequencer mode is disabled, sequencers of
-  *         all groups (group regular, group injected) can be configured
-  *         but their execution is disabled (limited to rank 1).
-  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
-  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
-  *         ADC conversion on only 1 channel.
-  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
-  * @param  ADCx ADC instance
-  * @param  SequencerNbRanks This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
-{
-  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
-}
-
-/**
-  * @brief  Get ADC group injected sequencer length and scan direction.
-  * @note   This function retrieves:
-  *         - Sequence length: Number of ranks in the scan sequence.
-  *         - Sequence direction: Unless specified in parameters, sequencer
-  *           scan direction is forward (from rank 1 to rank n).
-  * @note   On this STM32 serie, group injected sequencer configuration
-  *         is conditioned to ADC instance sequencer mode.
-  *         If ADC instance sequencer mode is disabled, sequencers of
-  *         all groups (group regular, group injected) can be configured
-  *         but their execution is disabled (limited to rank 1).
-  *         Refer to function @ref LL_ADC_SetSequencersScanMode().
-  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
-  *         ADC conversion on only 1 channel.
-  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
-  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
-}
-
-/**
-  * @brief  Set ADC group injected sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @note   It is not possible to enable both ADC group injected
-  *         auto-injected mode and sequencer discontinuous mode.
-  * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont
-  * @param  ADCx ADC instance
-  * @param  SeqDiscont This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
-{
-  MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
-}
-
-/**
-  * @brief  Get ADC group injected sequencer discontinuous mode:
-  *         sequence subdivided and scan conversions interrupted every selected
-  *         number of ranks.
-  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
-  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
-}
-
-/**
-  * @brief  Set ADC group injected sequence: channel on the selected
-  *         sequence rank.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   On this STM32 serie, to measure internal channels (VrefInt,
-  *         TempSensor, ...), measurement paths to internal channels must be
-  *         enabled separately.
-  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
-  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
-{
-  /* Set bits with content of parameter "Channel" with bits position          */
-  /* in register depending on parameter "Rank".                               */
-  /* Parameters "Rank" and "Channel" are used with masks because containing   */
-  /* other bits reserved for other purpose.                                   */
-  MODIFY_REG(ADCx->JSQR,
-             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
-             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
-}
-
-/**
-  * @brief  Get ADC group injected sequence: channel on the selected
-  *         sequence rank.
-  * @note   Depending on devices and packages, some channels may not be available.
-  *         Refer to device datasheet for channels availability.
-  * @note   Usage of the returned channel number:
-  *         - To reinject this channel into another function LL_ADC_xxx:
-  *           the returned channel number is only partly formatted on definition
-  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
-  *           with parts of literals LL_ADC_CHANNEL_x or using
-  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Then the selected literal LL_ADC_CHANNEL_x can be used
-  *           as parameter for another function.
-  *         - To get the channel number in decimal format:
-  *           process the returned value with the helper macro
-  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
-  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)(6)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
-  *         (6) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  return (uint32_t)(READ_BIT(ADCx->JSQR,
-                             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
-                    >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
-                   );
-}
-
-/**
-  * @brief  Set ADC group injected conversion trigger:
-  *         independent or from ADC group regular.
-  * @note   This mode can be used to extend number of data registers
-  *         updated after one ADC conversion trigger and with data 
-  *         permanently kept (not erased by successive conversions of scan of
-  *         ADC sequencer ranks), up to 5 data registers:
-  *         1 data register on ADC group regular, 4 data registers
-  *         on ADC group injected.            
-  * @note   If ADC group injected injected trigger source is set to an
-  *         external trigger, this feature must be must be set to
-  *         independent trigger.
-  *         ADC group injected automatic trigger is compliant only with 
-  *         group injected trigger source set to SW start, without any 
-  *         further action on  ADC group injected conversion start or stop: 
-  *         in this case, ADC group injected is controlled only 
-  *         from ADC group regular.
-  * @note   It is not possible to enable both ADC group injected
-  *         auto-injected mode and sequencer discontinuous mode.
-  * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto
-  * @param  ADCx ADC instance
-  * @param  TrigAuto This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
-  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
-{
-  MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
-}
-
-/**
-  * @brief  Get ADC group injected conversion trigger:
-  *         independent or from ADC group regular.
-  * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
-  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
-}
-
-/**
-  * @brief  Set ADC group injected offset.
-  * @note   It sets:
-  *         - ADC group injected rank to which the offset programmed
-  *           will be applied
-  *         - Offset level (offset to be subtracted from the raw
-  *           converted data).
-  *         Caution: Offset format is dependent to ADC resolution:
-  *         offset has to be left-aligned on bit 11, the LSB (right bits)
-  *         are set to 0.
-  * @note   Offset cannot be enabled or disabled.
-  *         To emulate offset disabled, set an offset value equal to 0.
-  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n
-  *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n
-  *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n
-  *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
-  
-  MODIFY_REG(*preg,
-             ADC_JOFR1_JOFFSET1,
-             OffsetLevel);
-}
-
-/**
-  * @brief  Get ADC group injected offset.
-  * @note   It gives offset level (offset to be subtracted from the raw converted data).
-  *         Caution: Offset format is dependent to ADC resolution:
-  *         offset has to be left-aligned on bit 11, the LSB (right bits)
-  *         are set to 0.
-  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n
-  *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n
-  *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n
-  *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
-  
-  return (uint32_t)(READ_BIT(*preg,
-                             ADC_JOFR1_JOFFSET1)
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
-  * @{
-  */
-
-/**
-  * @brief  Set sampling time of the selected ADC channel
-  *         Unit: ADC clock cycles.
-  * @note   On this device, sampling time is on channel scope: independently
-  *         of channel mapped on ADC group regular or injected.
-  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
-  *         converted:
-  *         sampling time constraints must be respected (sampling time can be
-  *         adjusted in function of ADC clock frequency and sampling time
-  *         setting).
-  *         Refer to device datasheet for timings values (parameters TS_vrefint,
-  *         TS_temp, ...).
-  * @note   Conversion time is the addition of sampling time and processing time.
-  *         Refer to reference manual for ADC processing time of
-  *         this STM32 serie.
-  * @note   In case of ADC conversion of internal channel (VrefInt,
-  *         temperature sensor, ...), a sampling time minimum value
-  *         is required.
-  *         Refer to device datasheet.
-  * @rmtoll SMPR0    SMP31          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR0    SMP30          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP29          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP28          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP27          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP26          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP25          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP24          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP23          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP22          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP21          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR1    SMP20          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP19          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP9           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP8           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP7           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP6           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP5           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP4           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP3           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP2           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP1           LL_ADC_SetChannelSamplingTime\n
-  *         SMPR3    SMP0           LL_ADC_SetChannelSamplingTime
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @param  SamplingTime This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
-{
-  /* Set bits with content of parameter "SamplingTime" with bits position     */
-  /* in register and register position depending on parameter "Channel".      */
-  /* Parameter "Channel" is used with masks because containing                */
-  /* other bits reserved for other purpose.                                   */
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
-  
-  MODIFY_REG(*preg,
-             ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
-             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get sampling time of the selected ADC channel
-  *         Unit: ADC clock cycles.
-  * @note   On this device, sampling time is on channel scope: independently
-  *         of channel mapped on ADC group regular or injected.
-  * @note   Conversion time is the addition of sampling time and processing time.
-  *         Refer to reference manual for ADC processing time of
-  *         this STM32 serie.
-  * @rmtoll SMPR0    SMP31          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR0    SMP30          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP29          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP28          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP27          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP26          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP25          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP24          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP23          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP22          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP21          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR1    SMP20          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP19          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP9           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP8           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP7           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP6           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP5           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP4           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP3           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP2           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP1           LL_ADC_GetChannelSamplingTime\n
-  *         SMPR3    SMP0           LL_ADC_GetChannelSamplingTime
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0          (2)
-  *         @arg @ref LL_ADC_CHANNEL_1          (2)
-  *         @arg @ref LL_ADC_CHANNEL_2          (2)
-  *         @arg @ref LL_ADC_CHANNEL_3          (2)
-  *         @arg @ref LL_ADC_CHANNEL_4          (1)
-  *         @arg @ref LL_ADC_CHANNEL_5          (1)
-  *         @arg @ref LL_ADC_CHANNEL_6          (2)
-  *         @arg @ref LL_ADC_CHANNEL_7          (2)
-  *         @arg @ref LL_ADC_CHANNEL_8          (2)
-  *         @arg @ref LL_ADC_CHANNEL_9          (2)
-  *         @arg @ref LL_ADC_CHANNEL_10         (2)
-  *         @arg @ref LL_ADC_CHANNEL_11         (2)
-  *         @arg @ref LL_ADC_CHANNEL_12         (2)
-  *         @arg @ref LL_ADC_CHANNEL_13         (3)
-  *         @arg @ref LL_ADC_CHANNEL_14         (3)
-  *         @arg @ref LL_ADC_CHANNEL_15         (3)
-  *         @arg @ref LL_ADC_CHANNEL_16         (3)
-  *         @arg @ref LL_ADC_CHANNEL_17         (3)
-  *         @arg @ref LL_ADC_CHANNEL_18         (3)
-  *         @arg @ref LL_ADC_CHANNEL_19         (3)
-  *         @arg @ref LL_ADC_CHANNEL_20         (3)
-  *         @arg @ref LL_ADC_CHANNEL_21         (3)
-  *         @arg @ref LL_ADC_CHANNEL_22         (1)
-  *         @arg @ref LL_ADC_CHANNEL_23         (1)
-  *         @arg @ref LL_ADC_CHANNEL_24         (1)
-  *         @arg @ref LL_ADC_CHANNEL_25         (1)
-  *         @arg @ref LL_ADC_CHANNEL_26         (3)
-  *         @arg @ref LL_ADC_CHANNEL_27         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_28         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_29         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_30         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_31         (3)(4)
-  *         @arg @ref LL_ADC_CHANNEL_VREFINT    (3)
-  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
-  *         @arg @ref LL_ADC_CHANNEL_VCOMP      (3)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2    (3)(5)
-  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3    (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
-  *         @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
-  
-  return (uint32_t)(READ_BIT(*preg,
-                             ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
-                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
-                   );
-}
-
-#if defined(COMP_CSR_FCH3)
-/**
-  * @brief  Set ADC channels routing.
-  * @note   Channel routing set configuration between ADC IP and GPIO pads,
-  *         it is used to increase ADC channels speed (setting of
-  *         direct channel).
-  * @note   This feature is specific to STM32L1, on devices
-  *         category Cat.3, Cat.4, Cat.5.
-  *         To use this function, COMP RCC clock domain must be enabled.
-  *         Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
-  * @rmtoll CSR      FCH3           LL_ADC_SetChannelRouting
-  * @rmtoll CSR      FCH8           LL_ADC_SetChannelRouting
-  * @rmtoll CSR      RCH13          LL_ADC_SetChannelRouting
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_3_ROUTING  (1)
-  *         @arg @ref LL_ADC_CHANNEL_8_ROUTING  (2)
-  *         @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
-  *
-  *         (1) Used as ADC direct channel (fast channel) if OPAMP1 is
-  *             in power down mode.\n
-  *         (2) Used as ADC direct channel (fast channel) if OPAMP2 is
-  *             in power down mode.\n
-  *         (3) Used as ADC re-routed channel if OPAMP3 is
-  *             in power down mode.
-  *             Otherwise, channel 13 is connected to OPAMP3 output and routed
-  *             through switches COMP1_SW1 and VCOMP to ADC switch matrix.
-  *             (Note: OPAMP3 is available on STM32L1 Cat.4 only).
-  * @param  Routing This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
-  *         @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
-  */
-__STATIC_INLINE void LL_ADC_SetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Routing)
-{
-  /* Note: Bit is located in comparator IP, but dedicated to ADC */
-  MODIFY_REG(COMP->CSR, Channel, (Routing << POSITION_VAL(Channel)));
-}
-
-/**
-  * @brief  Get ADC channels speed.
-  * @note   Channel routing set configuration between ADC IP and GPIO pads,
-  *         it is used to increase ADC channels speed (setting of
-  *         direct channel).
-  * @note   This feature is specific to STM32L1, on devices
-  *         category Cat.3, Cat.4, Cat.5.
-  *         To use this function, COMP RCC clock domain must be enabled.
-  *         Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
-  * @rmtoll CSR      FCH3           LL_ADC_GetChannelRouting
-  * @rmtoll CSR      FCH8           LL_ADC_GetChannelRouting
-  * @rmtoll CSR      RCH13          LL_ADC_GetChannelRouting
-  * @param  ADCx ADC instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_3_ROUTING  (1)
-  *         @arg @ref LL_ADC_CHANNEL_8_ROUTING  (2)
-  *         @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
-  *
-  *         (1) Used as ADC direct channel (fast channel) if OPAMP1 is
-  *             in power down mode.\n
-  *         (2) Used as ADC direct channel (fast channel) if OPAMP2 is
-  *             in power down mode.\n
-  *         (3) Used as ADC re-routed channel if OPAMP3 is
-  *             in power down mode.
-  *             Otherwise, channel 13 is connected to OPAMP3 output and routed
-  *             through switches COMP1_SW1 and VCOMP to ADC switch matrix.
-  *             (Note: OPAMP3 is available on STM32L1 Cat.4 only).
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
-  *         @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel)
-{
-  /* Note: Bit is located in comparator IP, but dedicated to ADC */
-  return (uint32_t)(READ_BIT(COMP->CSR, Channel) >> POSITION_VAL(Channel));
-}
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
-  * @{
-  */
-
-/**
-  * @brief  Set ADC analog watchdog monitored channels:
-  *         a single channel or all channels,
-  *         on ADC groups regular and-or injected.
-  * @note   Once monitored channels are selected, analog watchdog
-  *         is enabled.
-  * @note   In case of need to define a single channel to monitor
-  *         with analog watchdog from sequencer channel definition,
-  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC groups regular and-or injected.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
-  *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
-  *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels
-  * @param  ADCx ADC instance
-  * @param  AWDChannelGroup This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (3)
-  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG            (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_INJ            (3)
-  *         @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ        (3)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ      (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ      (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ          (3)(5)
-  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ      (3)(5)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
-  *         (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
-{
-  MODIFY_REG(ADCx->CR1,
-             (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
-             AWDChannelGroup);
-}
-
-/**
-  * @brief  Get ADC analog watchdog monitored channel.
-  * @note   Usage of the returned channel number:
-  *         - To reinject this channel into another function LL_ADC_xxx:
-  *           the returned channel number is only partly formatted on definition
-  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
-  *           with parts of literals LL_ADC_CHANNEL_x or using
-  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Then the selected literal LL_ADC_CHANNEL_x can be used
-  *           as parameter for another function.
-  *         - To get the channel number in decimal format:
-  *           process the returned value with the helper macro
-  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
-  *           Applicable only when the analog watchdog is set to monitor
-  *           one channel.
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC groups regular and-or injected.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
-  *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
-  *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels
-  * @param  ADCx ADC instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_DISABLE
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
-  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ       (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ       (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ      (2)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_INJ          (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ      (1)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_INJ          (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ      (3)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ      (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_INJ          (3)(4)
-  *         @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ      (3)(4)
-  *         
-  *         (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
-  *         (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
-  *         (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
-  *         (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.
-  */
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
-{
-  return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
-}
-
-/**
-  * @brief  Set ADC analog watchdog threshold value of threshold
-  *         high or low.
-  * @note   In case of ADC resolution different of 12 bits,
-  *         analog watchdog thresholds data require a specific shift.
-  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
-  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
-  *         instance:
-  *         - AWD standard (instance AWD1):
-  *           - channels monitored: can monitor 1 channel or all channels.
-  *           - groups monitored: ADC groups regular and-or injected.
-  *           - resolution: resolution is not limited (corresponds to
-  *             ADC resolution configured).
-  * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n
-  *         LTR      LT             LL_ADC_SetAnalogWDThresholds
-  * @param  ADCx ADC instance
-  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
-  
-  MODIFY_REG(*preg,
-             ADC_HTR_HT,
-             AWDThresholdValue);
-}
-
-/**
-  * @brief  Get ADC analog watchdog threshold value of threshold high or
-  *         threshold low.
-  * @note   In case of ADC resolution different of 12 bits,
-  *         analog watchdog thresholds data require a specific shift.
-  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
-  * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n
-  *         LTR      LT             LL_ADC_GetAnalogWDThresholds
-  * @param  ADCx ADC instance
-  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
-  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-*/
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
-  
-  return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
-  * @{
-  */
-
-/**
-  * @brief  Enable the selected ADC instance.
-  * @note   On this STM32 serie, after ADC enable, a delay for 
-  *         ADC internal analog stabilization is required before performing a
-  *         ADC conversion start.
-  *         Refer to device datasheet, parameter tSTAB.
-  * @note   Due to the latency introduced by the synchronization between
-  *         two clock domains (ADC clock source asynchronous),
-  *         some hardware constraints must be respected:
-  *         - ADC must be enabled (@ref LL_ADC_Enable() ) only
-  *           when ADC is not ready to convert.
-  *         - ADC must be disabled (@ref LL_ADC_Disable() ) only
-  *           when ADC is ready to convert.
-  *         Status of ADC ready to convert can be checked using function
-  *         @ref LL_ADC_IsActiveFlag_ADRDY().
-  * @rmtoll CR2      ADON           LL_ADC_Enable
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR2, ADC_CR2_ADON);
-}
-
-/**
-  * @brief  Disable the selected ADC instance.
-  * @note   Due to the latency introduced by the synchronization between
-  *         two clock domains (ADC clock source asynchronous),
-  *         some hardware constraints must be respected:
-  *         - ADC must be enabled (@ref LL_ADC_Enable() ) only
-  *           when ADC is not ready to convert.
-  *         - ADC must be disabled (@ref LL_ADC_Disable() ) only
-  *           when ADC is ready to convert.
-  *         Status of ADC ready to convert can be checked using function
-  *         @ref LL_ADC_IsActiveFlag_ADRDY().
-  * @rmtoll CR2      ADON           LL_ADC_Disable
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
-}
-
-/**
-  * @brief  Get the selected ADC instance enable state.
-  * @rmtoll CR2      ADON           LL_ADC_IsEnabled
-  * @param  ADCx ADC instance
-  * @retval 0: ADC is disabled, 1: ADC is enabled.
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
-  * @{
-  */
-
-/**
-  * @brief  Start ADC group regular conversion.
-  * @note   On this STM32 serie, this function is relevant only for
-  *         internal trigger (SW start), not for external trigger:
-  *         - If ADC trigger has been set to software start, ADC conversion
-  *           starts immediately.
-  *         - If ADC trigger has been set to external trigger, ADC conversion
-  *           start must be performed using function 
-  *           @ref LL_ADC_REG_StartConversionExtTrig().
-  *           (if external trigger edge would have been set during ADC other 
-  *           settings, ADC conversion would start at trigger event
-  *           as soon as ADC is enabled).
-  * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
-}
-
-/**
-  * @brief  Start ADC group regular conversion from external trigger.
-  * @note   ADC conversion will start at next trigger event (on the selected
-  *         trigger edge) following the ADC start conversion command.
-  * @note   On this STM32 serie, this function is relevant for 
-  *         ADC conversion start from external trigger.
-  *         If internal trigger (SW start) is needed, perform ADC conversion
-  *         start using function @ref LL_ADC_REG_StartConversionSWStart().
-  * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig
-  * @param  ExternalTriggerEdge This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
-{
-  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
-}
-
-/**
-  * @brief  Stop ADC group regular conversion from external trigger.
-  * @note   No more ADC conversion will start at next trigger event
-  *         following the ADC stop conversion command.
-  *         If a conversion is on-going, it will be completed.
-  * @note   On this STM32 serie, there is no specific command
-  *         to stop a conversion on-going or to stop ADC converting
-  *         in continuous mode. These actions can be performed
-  *         using function @ref LL_ADC_Disable().
-  * @rmtoll CR2      EXTEN          LL_ADC_REG_StopConversionExtTrig
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         all ADC configurations: all ADC resolutions and
-  *         all oversampling increased data width (for devices
-  *         with feature oversampling).
-  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 12 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 10 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
-  */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 8 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         ADC resolution 6 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
-  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
-  * @param  ADCx ADC instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
-{
-  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
-  * @{
-  */
-
-/**
-  * @brief  Start ADC group injected conversion.
-  * @note   On this STM32 serie, this function is relevant only for
-  *         internal trigger (SW start), not for external trigger:
-  *         - If ADC trigger has been set to software start, ADC conversion
-  *           starts immediately.
-  *         - If ADC trigger has been set to external trigger, ADC conversion
-  *           start must be performed using function 
-  *           @ref LL_ADC_INJ_StartConversionExtTrig().
-  *           (if external trigger edge would have been set during ADC other 
-  *           settings, ADC conversion would start at trigger event
-  *           as soon as ADC is enabled).
-  * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
-}
-
-/**
-  * @brief  Start ADC group injected conversion from external trigger.
-  * @note   ADC conversion will start at next trigger event (on the selected
-  *         trigger edge) following the ADC start conversion command.
-  * @note   On this STM32 serie, this function is relevant for 
-  *         ADC conversion start from external trigger.
-  *         If internal trigger (SW start) is needed, perform ADC conversion
-  *         start using function @ref LL_ADC_INJ_StartConversionSWStart().
-  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig
-  * @param  ExternalTriggerEdge This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
-  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
-{
-  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
-}
-
-/**
-  * @brief  Stop ADC group injected conversion from external trigger.
-  * @note   No more ADC conversion will start at next trigger event
-  *         following the ADC stop conversion command.
-  *         If a conversion is on-going, it will be completed.
-  * @note   On this STM32 serie, there is no specific command
-  *         to stop a conversion on-going or to stop ADC converting
-  *         in continuous mode. These actions can be performed
-  *         using function @ref LL_ADC_Disable().
-  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StopConversionExtTrig
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
-}
-
-/**
-  * @brief  Get ADC group regular conversion data, range fit for
-  *         all ADC configurations: all ADC resolutions and
-  *         all oversampling increased data width (for devices
-  *         with feature oversampling).
-  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
-  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
-  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
-  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-  
-  return (uint32_t)(READ_BIT(*preg,
-                             ADC_JDR1_JDATA)
-                   );
-}
-
-/**
-  * @brief  Get ADC group injected conversion data, range fit for
-  *         ADC resolution 12 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
-  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
-  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
-  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
-  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-  
-  return (uint16_t)(READ_BIT(*preg,
-                             ADC_JDR1_JDATA)
-                   );
-}
-
-/**
-  * @brief  Get ADC group injected conversion data, range fit for
-  *         ADC resolution 10 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
-  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
-  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
-  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
-  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
-  */
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-  
-  return (uint16_t)(READ_BIT(*preg,
-                             ADC_JDR1_JDATA)
-                   );
-}
-
-/**
-  * @brief  Get ADC group injected conversion data, range fit for
-  *         ADC resolution 8 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
-  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
-  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
-  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
-  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-  
-  return (uint8_t)(READ_BIT(*preg,
-                            ADC_JDR1_JDATA)
-                  );
-}
-
-/**
-  * @brief  Get ADC group injected conversion data, range fit for
-  *         ADC resolution 6 bits.
-  * @note   For devices with feature oversampling: Oversampling
-  *         can increase data width, function for extended range
-  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
-  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
-  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
-  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
-  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
-  * @param  ADCx ADC instance
-  * @param  Rank This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_INJ_RANK_1
-  *         @arg @ref LL_ADC_INJ_RANK_2
-  *         @arg @ref LL_ADC_INJ_RANK_3
-  *         @arg @ref LL_ADC_INJ_RANK_4
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
-{
-  uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-  
-  return (uint8_t)(READ_BIT(*preg,
-                            ADC_JDR1_JDATA)
-                  );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
-  * @{
-  */
-
-/**
-  * @brief  Get flag ADC ready.
-  * @rmtoll SR       ADONS          LL_ADC_IsActiveFlag_ADRDY
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
-}
-
-/**
-  * @brief  Get flag ADC group regular end of unitary conversion
-  *         or end of sequence conversions, depending on
-  *         ADC configuration.
-  * @note   To configure flag of end of conversion,
-  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
-  * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOCS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
-}
-
-/**
-  * @brief  Get flag ADC group regular overrun.
-  * @rmtoll SR       OVR            LL_ADC_IsActiveFlag_OVR
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
-}
-
-
-/**
-  * @brief  Get flag ADC group injected end of sequence conversions.
-  * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
-{
-  /* Note: on this STM32 serie, there is no flag ADC group injected          */
-  /*       end of unitary conversion.                                         */
-  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
-  /*       in other STM32 families).                                          */
-  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
-}
-
-/**
-  * @brief  Get flag ADC analog watchdog 1 flag
-  * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
-}
-
-/**
-  * @brief  Clear flag ADC group regular end of unitary conversion
-  *         or end of sequence conversions, depending on
-  *         ADC configuration.
-  * @note   To configure flag of end of conversion,
-  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
-  * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOCS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
-}
-
-/**
-  * @brief  Clear flag ADC group regular overrun.
-  * @rmtoll SR       OVR            LL_ADC_ClearFlag_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
-}
-
-
-/**
-  * @brief  Clear flag ADC group injected end of sequence conversions.
-  * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
-{
-  /* Note: on this STM32 serie, there is no flag ADC group injected          */
-  /*       end of unitary conversion.                                         */
-  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
-  /*       in other STM32 families).                                          */
-  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
-}
-
-/**
-  * @brief  Clear flag ADC analog watchdog 1.
-  * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
-{
-  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LL_EF_IT_Management ADC IT management
-  * @{
-  */
-
-/**
-  * @brief  Enable interruption ADC group regular end of unitary conversion
-  *         or end of sequence conversions, depending on
-  *         ADC configuration.
-  * @note   To configure flag of end of conversion,
-  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
-  * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOCS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
-}
-
-/**
-  * @brief  Enable ADC group regular interruption overrun.
-  * @rmtoll CR1      OVRIE          LL_ADC_EnableIT_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
-}
-
-
-/**
-  * @brief  Enable interruption ADC group injected end of sequence conversions.
-  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
-{
-  /* Note: on this STM32 serie, there is no flag ADC group injected          */
-  /*       end of unitary conversion.                                         */
-  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
-  /*       in other STM32 families).                                          */
-  SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
-}
-
-/**
-  * @brief  Enable interruption ADC analog watchdog 1.
-  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
-{
-  SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular end of unitary conversion
-  *         or end of sequence conversions, depending on
-  *         ADC configuration.
-  * @note   To configure flag of end of conversion,
-  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
-  * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOCS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
-}
-
-/**
-  * @brief  Disable interruption ADC group regular overrun.
-  * @rmtoll CR1      OVRIE          LL_ADC_DisableIT_OVR
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
-}
-
-
-/**
-  * @brief  Disable interruption ADC group injected end of sequence conversions.
-  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
-{
-  /* Note: on this STM32 serie, there is no flag ADC group injected          */
-  /*       end of unitary conversion.                                         */
-  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
-  /*       in other STM32 families).                                          */
-  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
-}
-
-/**
-  * @brief  Disable interruption ADC analog watchdog 1.
-  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
-{
-  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular end of unitary conversion
-  *         or end of sequence conversions, depending on
-  *         ADC configuration.
-  * @note   To configure flag of end of conversion,
-  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().
-  *         (0: interrupt disabled, 1: interrupt enabled)
-  * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOCS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
-}
-
-/**
-  * @brief  Get state of interruption ADC group regular overrun
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll CR1      OVRIE          LL_ADC_IsEnabledIT_OVR
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
-}
-
-
-/**
-  * @brief  Get state of interruption ADC group injected end of sequence conversions
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
-{
-  /* Note: on this STM32 serie, there is no flag ADC group injected          */
-  /*       end of unitary conversion.                                         */
-  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
-  /*       in other STM32 families).                                          */
-  return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
-}
-
-/**
-  * @brief  Get state of interruption ADC analog watchdog 1
-  *         (0: interrupt disabled, 1: interrupt enabled).
-  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
-  * @param  ADCx ADC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
-{
-  return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization of some features of ADC common parameters and multimode */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-
-/* De-initialization of ADC instance, ADC group regular and ADC group injected */
-/* (availability of ADC group injected depends on STM32 families) */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
-
-/* Initialization of some features of ADC instance */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
-void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group regular */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group injected */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ADC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h
deleted file mode 100644
index c4c1e0a6a6b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h
+++ /dev/null
@@ -1,1103 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_bus.h
-  * @author  MCD Application Team
-  * @brief   Header file of BUS LL module.
-
-  @verbatim
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_BUS_H
-#define __STM32L1xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
-  * @{
-  */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_GPIOA          RCC_AHBENR_GPIOAEN
-#define LL_AHB1_GRP1_PERIPH_GPIOB          RCC_AHBENR_GPIOBEN
-#define LL_AHB1_GRP1_PERIPH_GPIOC          RCC_AHBENR_GPIOCEN
-#define LL_AHB1_GRP1_PERIPH_GPIOD          RCC_AHBENR_GPIODEN
-#if defined(GPIOE)
-#define LL_AHB1_GRP1_PERIPH_GPIOE          RCC_AHBENR_GPIOEEN
-#endif/*GPIOE*/
-#define LL_AHB1_GRP1_PERIPH_GPIOH          RCC_AHBENR_GPIOHEN
-#if defined(GPIOF)
-#define LL_AHB1_GRP1_PERIPH_GPIOF          RCC_AHBENR_GPIOFEN
-#endif/*GPIOF*/
-#if defined(GPIOG)
-#define LL_AHB1_GRP1_PERIPH_GPIOG          RCC_AHBENR_GPIOGEN
-#endif/*GPIOG*/
-#define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBLPENR_SRAMLPEN
-#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN
-#define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHBENR_FLITFEN
-#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN
-#if defined(DMA2)
-#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHBENR_DMA2EN
-#endif/*DMA2*/
-#if defined(AES)
-#define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_AESEN
-#endif/*AES*/
-#if defined(FSMC_Bank1)
-#define LL_AHB1_GRP1_PERIPH_FSMC           RCC_AHBENR_FSMCEN
-#endif/*FSMC_Bank1*/
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
-#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
-#if defined(TIM5)
-#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
-#endif /*TIM5*/
-#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
-#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
-#if defined(LCD)
-#define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR_LCDEN
-#endif /*LCD*/
-#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
-#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
-#endif /*SPI3*/
-#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
-#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
-#endif /*UART4*/
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
-#endif /*UART5*/
-#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
-#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN
-#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
-#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
-#define LL_APB1_GRP1_PERIPH_COMP           RCC_APB1ENR_COMPEN
-#if defined(OPAMP)
-/* Note: Peripherals COMP and OPAMP share the same clock domain */
-#define LL_APB1_GRP1_PERIPH_OPAMP          LL_APB1_GRP1_PERIPH_COMP
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
-#define LL_APB2_GRP1_PERIPH_TIM9           RCC_APB2ENR_TIM9EN
-#define LL_APB2_GRP1_PERIPH_TIM10          RCC_APB2ENR_TIM10EN
-#define LL_APB2_GRP1_PERIPH_TIM11          RCC_APB2ENR_TIM11EN
-#define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN
-#if defined(SDIO)
-#define LL_APB2_GRP1_PERIPH_SDIO           RCC_APB2ENR_SDIOEN
-#endif /*SDIO*/
-#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
-#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
-  * @{
-  */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB1 peripherals clock.
-  * @rmtoll AHBENR       GPIOAEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOBEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOCEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIODEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOEEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOHEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOFEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       GPIOGEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       FLITFEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       DMA1EN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       DMA2EN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       FSMCEN        LL_AHB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB1 peripheral clock is enabled or not
-  * @rmtoll AHBENR       GPIOAEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOBEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOCEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIODEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOEEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOHEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOFEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       GPIOGEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       FLITFEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       FSMCEN        LL_AHB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock.
-  * @rmtoll AHBENR       GPIOAEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOBEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOCEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIODEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOEEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOHEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOFEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       GPIOGEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       FLITFEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       DMA1EN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       DMA2EN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       FSMCEN        LL_AHB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      GPIOARST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOBRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOCRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIODRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOERST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOHRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOFRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      GPIOGRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      FLITFRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      DMA1RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      DMA2RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      AESRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      FSMCRST       LL_AHB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      FLITFRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      AESRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      FSMCRST       LL_AHB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHBLPENR     GPIOALPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOBLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOCLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIODLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOELPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOHLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOFLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     GPIOGLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     FLITFLPEN     LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     SRAMLPEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     AESLPEN       LL_AHB1_GRP1_EnableClockSleep\n
-  *         AHBLPENR     FSMCLPEN      LL_AHB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBLPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll AHBLPENR     GPIOALPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOBLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOCLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIODLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOELPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOHLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOFLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     GPIOGLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     FLITFLPEN     LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     SRAMLPEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     AESLPEN       LL_AHB1_GRP1_DisableClockSleep\n
-  *         AHBLPENR     FSMCLPEN      LL_AHB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBLPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      TIM3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      TIM4EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      TIM5EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      TIM6EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      TIM7EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      LCDEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      WWDGEN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      SPI2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      SPI3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      USART2EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      USART3EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      UART4EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      UART5EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      I2C1EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      I2C2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      USBEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      PWREN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      DACEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR      COMPEN        LL_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      LCDEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      USART2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      USART3EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      UART4EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      UART5EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      USBEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      PWREN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      DACEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR      COMPEN        LL_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APB1ENR      TIM2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      TIM3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      TIM4EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      TIM5EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      TIM6EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      TIM7EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      LCDEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      WWDGEN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      SPI2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      SPI3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      USART2EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      USART3EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      UART4EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      UART5EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      I2C1EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      I2C2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      USBEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      PWREN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      DACEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR      COMPEN        LL_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     LCDRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART2RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART3RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART4RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART5RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USBRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     PWRRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     DACRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     COMPRST       LL_APB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     LCDRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART2RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART3RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART4RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART5RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USBRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     PWRRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     DACRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     COMPRST       LL_APB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LPENR    TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    LCDLPEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    WWDGLPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    USBLPEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    PWRLPEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    DACLPEN       LL_APB1_GRP1_EnableClockSleep\n
-  *         APB1LPENR    COMPLPEN      LL_APB1_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB1LPENR    TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    LCDLPEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    WWDGLPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    USBLPEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    PWRLPEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    DACLPEN       LL_APB1_GRP1_DisableClockSleep\n
-  *         APB1LPENR    COMPLPEN      LL_APB1_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_COMP
-  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable APB2 peripherals clock.
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM9EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM10EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      TIM11EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      ADC1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SDIOEN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SDIOEN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock.
-  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM9EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM10EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      TIM11EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      ADC1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SDIOEN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB2 peripherals reset.
-  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM9RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM10RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM11RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     ADC1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SDIORST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB2 peripherals reset.
-  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM9RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM10RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM11RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     ADC1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SDIORST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    SYSCFGLPEN    LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM9LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM10LPEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    TIM11LPEN     LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    ADC1LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SDIOLPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
-  * @rmtoll APB2LPENR    SYSCFGLPEN    LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM9LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM10LPEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    TIM11LPEN     LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    ADC1LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SDIOLPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
-  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_comp.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_comp.h
deleted file mode 100644
index 122f87404b7..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_comp.h
+++ /dev/null
@@ -1,847 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_comp.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_COMP_H
-#define __STM32L1xx_LL_COMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (COMP1) || defined (COMP2)
-
-/** @defgroup COMP_LL COMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_LL_Private_Constants COMP Private Constants
-  * @{
-  */
-
-/* COMP registers bits positions */
-#define LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1OUT) */
-#define LL_COMP_OUTPUT_LEVEL_COMP2_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP2OUT) */
-#define LL_COMP_ENABLE_COMP1_BITOFFSET_POS       ( 4U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1EN) */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMP_LL_Private_Macros COMP Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Driver macro reserved for internal use: if COMP instance selected
-  *         is odd (COMP1, COMP3, ...), return value '1', else return '0'.
-  * @param  __COMP_INSTANCE__ COMP instance
-  * @retval If COMP instance is odd, value '1'. Else, value '0'.
-*/
-#define __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__)                              \
-  ((~((uint32_t)(__COMP_INSTANCE__) - COMP_BASE)) & 0x00000001)
-
-/**
-  * @brief  Driver macro reserved for internal use: if COMP instance selected
-  *         is even (COMP2, COMP4, ...), return value '1', else return '0'.
-  * @param  __COMP_INSTANCE__ COMP instance
-  * @retval If COMP instance is even, value '1'. Else, value '0'.
-*/
-#define __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__)                             \
-  ((uint32_t)(__COMP_INSTANCE__) - COMP_BASE)
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of COMP instance.
-  */
-typedef struct
-{
-  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
-                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
-
-  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
-                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
-
-  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
-                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
-
-  uint32_t OutputSelection;             /*!< Set comparator output selection.
-                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
-
-} LL_COMP_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
-  * @{
-  */
-#define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000U)           /*!< Window mode disable: Comparators 1 and 2 are independent */
-#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WNDWE)        /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP2 input plus (COMP1 input plus is no more accessible, either from GPIO and from ADC channel VCOMP). */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
-  * @{
-  */
-#define LL_COMP_POWERMODE_ULTRALOWPOWER   (0x00000000U)               /*!< COMP power mode to low speed (specific to COMP instance: COMP2) */
-#define LL_COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_SPEED)            /*!< COMP power mode to fast speed (specific to COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
-  * @{
-  */
-#define LL_COMP_INPUT_PLUS_NONE         (0x00000000U)           /*!< Comparator input plus connected not connected */
-#define LL_COMP_INPUT_PLUS_IO1          (RI_ASCR2_GR6_1)        /*!< Comparator input plus connected to IO1 (pin PB4 for COMP2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_PLUS_IO2          (RI_ASCR2_GR6_2)        /*!< Comparator input plus connected to IO1 (pin PB5 for COMP2) (specific to COMP instance: COMP2) */
-#if defined(RI_ASCR1_CH_31)
-#define LL_COMP_INPUT_PLUS_IO3          (RI_ASCR2_GR6_3)        /*!< Comparator input plus connected to IO1 (pin PB6 for COMP2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_PLUS_IO4          (RI_ASCR2_GR6_4)        /*!< Comparator input plus connected to IO1 (pin PB7 for COMP2) (specific to COMP instance: COMP2) */
-#endif
-#define LL_COMP_INPUT_PLUS_IO5          (RI_ASCR1_CH_0)         /*!< Comparator input plus connected to IO5 (pin PA0 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO6          (RI_ASCR1_CH_1)         /*!< Comparator input plus connected to IO6 (pin PA1 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO7          (RI_ASCR1_CH_2)         /*!< Comparator input plus connected to IO7 (pin PA2 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO8          (RI_ASCR1_CH_3)         /*!< Comparator input plus connected to IO8 (pin PA3 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO9          (RI_ASCR1_CH_4)         /*!< Comparator input plus connected to IO9 (pin PA4 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO10         (RI_ASCR1_CH_5)         /*!< Comparator input plus connected to IO10 (pin PA5 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO11         (RI_ASCR1_CH_6)         /*!< Comparator input plus connected to IO11 (pin PA6 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO12         (RI_ASCR1_CH_7)         /*!< Comparator input plus connected to IO12 (pin PA7 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO13         (RI_ASCR1_CH_8)         /*!< Comparator input plus connected to IO13 (pin PB0 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO14         (RI_ASCR1_CH_9)         /*!< Comparator input plus connected to IO14 (pin PB1 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO15         (RI_ASCR1_CH_10)        /*!< Comparator input plus connected to IO15 (pin PC0 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO16         (RI_ASCR1_CH_11)        /*!< Comparator input plus connected to IO16 (pin PC1 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO17         (RI_ASCR1_CH_12)        /*!< Comparator input plus connected to IO17 (pin PC2 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO18         (RI_ASCR1_CH_13)        /*!< Comparator input plus connected to IO18 (pin PC3 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO19         (RI_ASCR1_CH_14)        /*!< Comparator input plus connected to IO19 (pin PC4 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO20         (RI_ASCR1_CH_15)        /*!< Comparator input plus connected to IO20 (pin PC5 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO21         (RI_ASCR1_CH_18)        /*!< Comparator input plus connected to IO21 (pin PB12 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO22         (RI_ASCR1_CH_19)        /*!< Comparator input plus connected to IO22 (pin PB13 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO23         (RI_ASCR1_CH_20)        /*!< Comparator input plus connected to IO23 (pin PB14 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO24         (RI_ASCR1_CH_21)        /*!< Comparator input plus connected to IO24 (pin PB15 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO25         (RI_ASCR1_CH_22)        /*!< Comparator input plus connected to IO25 (pin PE7 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO26         (RI_ASCR1_CH_23)        /*!< Comparator input plus connected to IO26 (pin PE8 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO27         (RI_ASCR1_CH_24)        /*!< Comparator input plus connected to IO27 (pin PE9 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO28         (RI_ASCR1_CH_25)        /*!< Comparator input plus connected to IO28 (pin PE10 for COMP1) (specific to COMP instance: COMP1) */
-#if defined(RI_ASCR1_CH_31)
-#define LL_COMP_INPUT_PLUS_IO29         (RI_ASCR1_CH_27)        /*!< Comparator input plus connected to IO29 (pin PF6 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO30         (RI_ASCR1_CH_28)        /*!< Comparator input plus connected to IO30 (pin PF7 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO31         (RI_ASCR1_CH_29)        /*!< Comparator input plus connected to IO31 (pin PF8 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO32         (RI_ASCR1_CH_30)        /*!< Comparator input plus connected to IO32 (pin PF9 for COMP1) (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_IO33         (RI_ASCR1_CH_31)        /*!< Comparator input plus connected to IO33 (pin PF10 for COMP1) (specific to COMP instance: COMP1) */
-#endif
-#if defined(OPAMP1)
-#define LL_COMP_INPUT_PLUS_OPAMP1       (RI_ASCR1_CH_3)         /*!< Comparator input plus connected to OPAMP1 output (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_PLUS_OPAMP2       (RI_ASCR1_CH_8)         /*!< Comparator input plus connected to OPAMP2 output (specific to COMP instance: COMP1) */
-#endif
-#if defined(OPAMP3)
-#define LL_COMP_INPUT_PLUS_OPAMP3       (RI_ASCR1_CH_13)        /*!< Comparator input plus connected to OPAMP3 output (specific to COMP instance: COMP1) */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
-  * @{
-  */
-#define LL_COMP_INPUT_MINUS_1_4VREFINT  (COMP_CSR_INSEL_2                    | COMP_CSR_INSEL_0) /*!< Comparator input minus connected to 1/4 VrefInt (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_1_2VREFINT  (COMP_CSR_INSEL_2                                      ) /*!< Comparator input minus connected to 1/2 VrefInt (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_3_4VREFINT  (                   COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< Comparator input minus connected to 3/4 VrefInt (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_VREFINT     (                   COMP_CSR_INSEL_1                   ) /*!< Comparator input minus connected to VrefInt */
-#define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1                   ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) (specific to COMP instance: COMP2) */
-#define LL_COMP_INPUT_MINUS_IO1         (                                      COMP_CSR_INSEL_0) /*!< Comparator input minus connected to IO1 (pin PB3 for COMP2) (specific to COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_INPUT_PULLING_RESISTOR Comparator input - Pulling resistor
-  * @{
-  */
-#define LL_COMP_INPUT_MINUS_PULL_NO        (0x00000000U)           /*!< Comparator input minus not connected to any pulling resistor */
-#define LL_COMP_INPUT_MINUS_PULL_UP_10K    (COMP_CSR_10KPU)        /*!< Comparator input minus connected to pull-up resistor of 10kOhm (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_MINUS_PULL_UP_400K   (COMP_CSR_400KPU)       /*!< Comparator input minus connected to pull-up resistor of 400kOhm (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_MINUS_PULL_DOWN_10K  (COMP_CSR_10KPD)        /*!< Comparator input minus connected to pull-down resistor of 10kOhm (specific to COMP instance: COMP1) */
-#define LL_COMP_INPUT_MINUS_PULL_DOWN_400K (COMP_CSR_400KPD)       /*!< Comparator input minus connected to pull-down resistor of 400kOhm (specific to COMP instance: COMP1) */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
-  * @{
-  */
-#define LL_COMP_OUTPUT_NONE             (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4         (0x00000000)                                                /*!< COMP output connected to TIM2 input capture 4  (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_OCREFCLR    (                                        COMP_CSR_OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear      (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM3_IC4         (                    COMP_CSR_OUTSEL_1                    ) /*!< COMP output connected to TIM3 input capture 4  (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM3_OCREFCLR    (                    COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear      (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM4_IC4         (COMP_CSR_OUTSEL_2                                        ) /*!< COMP output connected to TIM4 input capture 4  (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM4_OCREFCLR    (COMP_CSR_OUTSEL_2                     | COMP_CSR_OUTSEL_0) /*!< COMP output connected to TIM4 OCREF clear      (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM10_IC1        (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1                    ) /*!< COMP output connected to TIM10 input capture 1 (specific to COMP instance: COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
-  * @{
-  */
-#define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
-#define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
-  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-
-/* Delay for comparator startup time.                                         */
-/* Note: Delay required to reach propagation delay specification.             */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSTART").                                                       */
-/* Unit: us                                                                   */
-#define LL_COMP_DELAY_STARTUP_US          (25U)  /*!< Delay for COMP startup time */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
-  * @{
-  */
-/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
-  * @{
-  */
-
-/**
-  * @brief  Write a value in COMP register
-  * @param  __INSTANCE__ comparator instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in COMP register
-  * @param  __INSTANCE__ comparator instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to select the COMP common instance
-  *         to which is belonging the selected COMP instance.
-  * @note   COMP common register instance can be used to
-  *         set parameters common to several COMP instances.
-  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
-  * @param  __COMPx__ COMP instance
-  * @retval COMP common instance or value "0" if there is no COMP common instance.
-  */
-#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
-  (COMP12_COMMON)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
-  * @{
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
-  * @{
-  */
-
-/**
-  * @brief  Set window mode of a pair of comparators instances
-  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
-  * @rmtoll CSR      WNDWE          LL_COMP_SetCommonWindowMode
-  * @param  COMPxy_COMMON Comparator common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
-  * @param  WindowMode This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
-  *         @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
-{
-  MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWE, WindowMode);
-}
-
-/**
-  * @brief  Get window mode of a pair of comparators instances
-  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
-  * @rmtoll CSR      WNDWE          LL_COMP_GetCommonWindowMode
-  * @param  COMPxy_COMMON Comparator common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
-  *         @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
-  * @{
-  */
-
-/**
-  * @brief  Set comparator instance operating mode to adjust power and speed.
-  * @rmtoll COMP2_CSR   SPEED           LL_COMP_SetPowerMode
-  * @param  COMPx Comparator instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
-  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
-{
-  MODIFY_REG(COMP->CSR, COMP_CSR_SPEED, PowerMode);
-}
-
-/**
-  * @brief  Get comparator instance operating mode to adjust power and speed.
-  * @rmtoll COMP2_CSR   SPEED           LL_COMP_GetPowerMode
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
-  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMP->CSR, COMP_CSR_SPEED));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
-  * @{
-  */
-
-/**
-  * @brief  Set comparator input plus (non-inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @rmtoll RI       RI_ASCR1_CH    LL_COMP_SetInputPlus\n
-  *         RI       RI_ASCR2_GR6   LL_COMP_SetInputPlus
-  * @param  COMPx Comparator instance
-  * @param  InputPlus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_PLUS_NONE
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (2)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (2)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (2)(5)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (2)(5)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO7 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO8 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO9 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO10 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO11 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO12 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO13 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO14 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO15 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO16 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO17 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO18 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO19 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO20 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO21 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO22 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO23 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO24 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO25 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO26 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO27 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO28 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO29 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO30 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO31 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO32 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO33 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP1 (1)(3)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP2 (1)(3)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP3 (1)(4)
-  *         
-  *         (1) Available only on COMP instance: COMP1. \n
-  *         (2) Available only on COMP instance: COMP2. \n
-  *         (3) Available on devices: STM32L100xB, STM32L151xB, STM32L152xB, STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD \n
-  *         (4) Available on devices: STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD \n
-  *         (5) Available on devices: STM32L100xC, STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX, STM32L152xE, STM32L152xDX, STM32L162xE, STM32L162xDX
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
-{
-  /* Set switch in routing interface (RI) register ASCR1 or ASCR2 */
-  /* Note: If COMP instance COMP1 is selected, this function performs         */
-  /*       necessary actions on routing interface:                            */
-  /*        - close switch netween comparator 1 and switch matrix             */
-  /*          (RI_ASCR1_VCOMP)                                                */
-  /*        - enable IO switch control mode (RI_ASCR1_SCM)                    */
-  /*          If ADC needs to be used afterwards, disable IO switch control   */
-  /*          mode using function @ref LL_RI_DisableSwitchControlMode().      */
-  uint32_t *preg = ((uint32_t *)((uint32_t) ((uint32_t)(&(RI->ASCR1)) + ((__COMP_IS_INSTANCE_EVEN(COMPx)) << 2U))));
-  
-  MODIFY_REG(*preg,
-             (RI_ASCR1_CH * __COMP_IS_INSTANCE_ODD(COMPx)) | (RI_ASCR2_GR6 * __COMP_IS_INSTANCE_EVEN(COMPx)),
-             InputPlus | ((RI_ASCR1_VCOMP | RI_ASCR1_SCM) * __COMP_IS_INSTANCE_ODD(COMPx)));
-}
-
-/**
-  * @brief  Get comparator input plus (non-inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @rmtoll RI       RI_ASCR1_CH    LL_COMP_GetInputPlus\n
-  *         RI       RI_ASCR2_GR6   LL_COMP_GetInputPlus
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_PLUS_NONE
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (2)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (2)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (2)(5)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (2)(5)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO7 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO8 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO9 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO10 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO11 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO12 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO13 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO14 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO15 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO16 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO17 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO18 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO19 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO20 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO21 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO22 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO23 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO24 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO25 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO26 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO27 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO28 (1)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO29 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO30 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO31 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO32 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_IO33 (1)(4)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP1 (1)(3)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP2 (1)(3)
-  *         @arg @ref LL_COMP_INPUT_PLUS_OPAMP3 (1)(4)
-  *         
-  *         (1) Available only on COMP instance: COMP1. \n
-  *         (2) Available only on COMP instance: COMP2. \n
-  *         (3) Available on devices: STM32L100xB, STM32L151xB, STM32L152xB, STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD \n
-  *         (4) Available on devices: STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD \n
-  *         (5) Available on devices: STM32L100xC, STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, STM32L152xD, STM32L162xCA, STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX, STM32L152xE, STM32L152xDX, STM32L162xE, STM32L162xDX
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
-{
-  /* Get switch state in routing interface (RI) register ASCR1 or ASCR2 */
-  uint32_t *preg = ((uint32_t *)((uint32_t) ((uint32_t)(&(RI->ASCR1)) + ((__COMP_IS_INSTANCE_EVEN(COMPx)) << 2U))));
-  
-  return (uint32_t)(READ_BIT(*preg,
-                             (RI_ASCR1_CH * __COMP_IS_INSTANCE_ODD(COMPx)) | (RI_ASCR2_GR6 * __COMP_IS_INSTANCE_EVEN(COMPx))));
-}
-
-/**
-  * @brief  Set comparator input minus (inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @rmtoll CSR      COMP_CSR_INSEL LL_COMP_SetInputMinus
-  * @param  COMPx Comparator instance
-  * @param  InputMinus This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO1        (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
-{
-  /* On this STM32 serie, only COMP instance COMP1 input minus is fixed to   */
-  /* VrefInt. Check of comparator instance is implemented to modify register  */
-  /* only if COMP2 is selected.                                               */
-  MODIFY_REG(COMP->CSR,
-             COMP_CSR_INSEL * __COMP_IS_INSTANCE_EVEN(COMPx),
-             InputMinus     * __COMP_IS_INSTANCE_EVEN(COMPx));
-}
-
-/**
-  * @brief  Get comparator input minus (inverting).
-  * @note   In case of comparator input selected to be connected to IO:
-  *         GPIO pins are specific to each comparator instance.
-  *         Refer to description of parameters or to reference manual.
-  * @rmtoll CSR      COMP_CSR_INSEL LL_COMP_SetInputMinus
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_IO1        (1)
-  *         
-  *         (1) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
-{
-  /* On this STM32 serie, only COMP instance COMP1 input minus is fixed to   */
-  /* VrefInt. Check of comparator instance is implemented to return           */
-  /* the comparator input plus depending on COMP instance selected.           */
-  return (uint32_t)((READ_BIT(COMP->CSR, COMP_CSR_INSEL) * __COMP_IS_INSTANCE_EVEN(COMPx))
-                     | (LL_COMP_INPUT_MINUS_VREFINT * __COMP_IS_INSTANCE_ODD(COMPx)));
-}
-
-/**
-  * @brief  Set comparator input pulling resistor.
-  * @rmtoll CSR      10KPU          LL_COMP_SetInputPullingResistor\n
-  *         CSR      400KPU         LL_COMP_SetInputPullingResistor\n
-  *         CSR      10KPD          LL_COMP_SetInputPullingResistor\n
-  *         CSR      400KPD         LL_COMP_SetInputPullingResistor
-  * @param  COMPx Comparator instance
-  * @param  InputPullingResistor This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_NO
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_UP_10K    (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_UP_400K   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_DOWN_10K  (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_DOWN_400K (1)
-  *         
-  *         (1) Available only on COMP instance: COMP1.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetInputPullingResistor(COMP_TypeDef *COMPx, uint32_t InputPullingResistor)
-{
-  /* On this STM32 serie, only COMP instance COMP1 has input pulling         */
-  /* resistor. Check of comparator instance is implemented to modify register */
-  /* only if COMP1 is selected.                                               */
-  MODIFY_REG(COMP->CSR,
-             (COMP_CSR_10KPU | COMP_CSR_400KPU | COMP_CSR_10KPD | COMP_CSR_400KPD) * __COMP_IS_INSTANCE_ODD(COMPx),
-             InputPullingResistor * __COMP_IS_INSTANCE_ODD(COMPx));
-}
-
-/**
-  * @brief  Get comparator input pulling resistor.
-  * @rmtoll CSR      10KPU          LL_COMP_SetInputPullingResistor\n
-  *         CSR      400KPU         LL_COMP_SetInputPullingResistor\n
-  *         CSR      10KPD          LL_COMP_SetInputPullingResistor\n
-  *         CSR      400KPD         LL_COMP_SetInputPullingResistor
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_NO
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_UP_10K    (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_UP_400K   (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_DOWN_10K  (1)
-  *         @arg @ref LL_COMP_INPUT_MINUS_PULL_DOWN_400K (1)
-  *         
-  *         (1) Available only on COMP instance: COMP1.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetInputPullingResistor(COMP_TypeDef *COMPx)
-{
-  /* On this STM32 serie, only COMP instance COMP1 has input pulling         */
-  /* resistor. Check of comparator instance is implemented to return          */
-  /* the comparator input pulling resistor depending on COMP instance         */
-  /* selected.                                                                */
-  /* On this STM32 serie, only COMP instance COMP1 input minus is fixed to   */
-  /* VrefInt. Check of comparator instance is implemented to return           */
-  /* the comparator input plus depending on COMP instance selected.           */
-  return (uint32_t)((READ_BIT(COMP->CSR, (COMP_CSR_10KPU | COMP_CSR_400KPU | COMP_CSR_10KPD | COMP_CSR_400KPD)) * __COMP_IS_INSTANCE_ODD(COMPx))
-                     | (LL_COMP_INPUT_MINUS_PULL_NO * __COMP_IS_INSTANCE_EVEN(COMPx)));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
-  * @{
-  */
-
-/**
-  * @brief  Set comparator output selection.
-  * @note   Availability of parameters of output selection to timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CSR      OUTSEL         LL_COMP_SetOutputSelection
-  * @param  COMPx Comparator instance
-  * @param  OutputSelection This parameter can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_NONE
-  *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM2_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM3_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM3_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM4_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM4_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM10_IC1     (1)(2)
-  *         
-  *         (1) Parameter availability depending on timer availability
-  *             on the selected device.
-  *         (2) Available only on COMP instance: COMP2.
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
-{
-  /* On this STM32 serie, only COMP instance COMP2 has feature output        */
-  /* selection. Check of comparator instance is implemented to modify register*/
-  /* only if COMP2 is selected.                                               */
-  MODIFY_REG(COMP->CSR,
-             COMP_CSR_OUTSEL * __COMP_IS_INSTANCE_EVEN(COMPx),
-             OutputSelection * __COMP_IS_INSTANCE_EVEN(COMPx));
-}
-
-/**
-  * @brief  Get comparator output selection.
-  * @note   Availability of parameters of output selection to timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CSR      OUTSEL         LL_COMP_GetOutputSelection
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_NONE
-  *         @arg @ref LL_COMP_OUTPUT_TIM2_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM2_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM3_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM3_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM4_IC4      (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM4_OCREFCLR (1)(2)
-  *         @arg @ref LL_COMP_OUTPUT_TIM10_IC1     (1)(2)
-  *         
-  *         (1) Parameter availability depending on timer availability
-  *             on the selected device.
-  *         (2) Available only on COMP instance: COMP2.
-  */
-__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
-{
-  /* On this STM32 serie, only COMP instance COMP2 has feature output        */
-  /* selection. Check of comparator instance is implemented to return         */
-  /* the comparator output depending on COMP instance selected.               */
-  return (uint32_t)((READ_BIT(COMP->CSR, COMP_CSR_OUTSEL) * __COMP_IS_INSTANCE_EVEN(COMPx))
-                     | (LL_COMP_OUTPUT_NONE * __COMP_IS_INSTANCE_ODD(COMPx)));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
-  * @{
-  */
-
-/**
-  * @brief  Enable comparator instance.
-  * @note   After enable from off state, comparator requires a delay
-  *         to reach reach propagation delay specification.
-  *         Refer to device datasheet, parameter "tSTART".
-  * @rmtoll CSR      COMP1EN        LL_COMP_Enable\n
-  *         CSR      COMP_CSR_INSEL LL_COMP_Enable
-  * @param  COMPx Comparator instance (1)
-  *         
-  *         (1) On this STM32 serie, the only COMP instance that can be enabled
-  *             using this function is COMP1.
-  *             COMP2 is enabled by setting input minus.
-  *             Refer to function @ref LL_COMP_SetInputMinus().
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
-{
-  /* On this STM32 serie, only COMP instance COMP1 has a dedicated bit       */
-  /* for comparator enable. Check of comparator instance is implemented       */
-  /* to modify register only if COMP1 is selected.                            */
-  SET_BIT(COMP->CSR, __COMP_IS_INSTANCE_ODD(COMPx) << LL_COMP_ENABLE_COMP1_BITOFFSET_POS);
-}
-
-/**
-  * @brief  Disable comparator instance.
-  * @note   On this STM32 serie, COMP2 is disabled by clearing input minus
-  *         selection. If COMP2 must be enabled afterwards, input minus must
-  *         be set. Refer to function @ref LL_COMP_SetInputMinus().
-  * @rmtoll CSR      COMP1EN        LL_COMP_Disable\n
-  *         CSR      COMP_CSR_INSEL LL_COMP_Disable
-  * @param  COMPx Comparator instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
-{
-  /* Note: On this STM32 serie, COMP2 is enabled by setting input minus.     */
-  /*       Refer to function @ref LL_COMP_SetInputMinus().                    */
-  /*       To disable COMP2, bitfield of input minus selection is reset.      */
-  CLEAR_BIT(COMP->CSR, (COMP_CSR_CMP1EN * __COMP_IS_INSTANCE_ODD(COMPx)) | (COMP_CSR_INSEL * __COMP_IS_INSTANCE_EVEN(COMPx)));
-}
-
-/**
-  * @brief  Get comparator enable state
-  *         (0: COMP is disabled, 1: COMP is enabled)
-  * @rmtoll CSR      COMP1EN        LL_COMP_IsEnabled\n
-  *         CSR      COMP_CSR_INSEL LL_COMP_IsEnabled
-  * @param  COMPx Comparator instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
-{
-  return (READ_BIT(COMP->CSR, (COMP_CSR_CMP1EN * __COMP_IS_INSTANCE_ODD(COMPx)) | (COMP_CSR_INSEL * __COMP_IS_INSTANCE_EVEN(COMPx))) != (0U));
-}
-
-/**
-  * @brief  Read comparator instance output level.
-  * @note   On this STM32 serie, comparator polarity is not settable
-  *         and not inverted:
-  *          - Comparator output is low when the input plus
-  *            is at a lower voltage than the input minus
-  *          - Comparator output is high when the input plus
-  *            is at a higher voltage than the input minus
-  * @rmtoll CSR      CMP1OUT        LL_COMP_ReadOutputLevel\n
-  *         CSR      CMP2OUT        LL_COMP_ReadOutputLevel
-  * @param  COMPx Comparator instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
-  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
-  */
-__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
-{
-  return (uint32_t)(READ_BIT(COMP->CSR,
-                             ((__COMP_IS_INSTANCE_ODD(COMPx) << LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS) | (__COMP_IS_INSTANCE_EVEN(COMPx) << LL_COMP_OUTPUT_LEVEL_COMP2_BITOFFSET_POS)))
-                    >> (LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS + ((LL_COMP_OUTPUT_LEVEL_COMP2_BITOFFSET_POS - LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS) * __COMP_IS_INSTANCE_EVEN(COMPx)))
-                   );
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
-void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* COMP1 || COMP2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h
deleted file mode 100644
index c08339efb98..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h
+++ /dev/null
@@ -1,639 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL CORTEX driver contains a set of generic APIs that can be
-    used by user:
-      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
-          functions
-      (+) Low power mode configuration (SCB register of Cortex-MCU)
-      (+) MPU API to configure and enable regions
-      (+) API to access to MCU info (CPUID register)
-      (+) API to enable fault handler (SHCSR accesses)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_CORTEX_H
-#define __STM32L1xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX_LL CORTEX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @{
-  */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
-  * @{
-  */
-#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @{
-  */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @{
-  */
-#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @{
-  */
-#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @{
-  */
-#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @{
-  */
-#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @{
-  */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @{
-  */
-
-/**
-  * @brief  This function checks if the Systick counter flag is active or not.
-  * @note   It can be used in timeout function on application side.
-  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
-  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
-  * @brief  Configures the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
-  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
-  {
-    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-  else
-  {
-    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-}
-
-/**
-  * @brief  Get the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
-  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
-  * @brief  Enable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
-  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Disable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
-  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
-  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @{
-  */
-
-/**
-  * @brief  Processor uses sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Processor uses deep sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
-  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
-  *         empty main application.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Do not sleep when returning to Thread mode.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
-  *         processor.
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
-  /* Set SEVEONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
-  *         excluded
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
-  /* Clear SEVEONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
-  * @{
-  */
-
-/**
-  * @brief  Enable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
-  /* Enable the system handler fault */
-  SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @brief  Disable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
-  /* Disable the system handler fault */
-  CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @{
-  */
-
-/**
-  * @brief  Get Implementer code
-  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
-  * @retval Value should be equal to 0x41 for ARM
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
-  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
-  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
-  * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
-  * @brief  Get Constant number
-  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
-  * @retval Value should be equal to 0xF for Cortex-M3 devices
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
-  * @brief  Get Part number
-  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
-  * @retval Value should be equal to 0xC23 for Cortex-M3
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
-  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
-  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
-  * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
-  * @{
-  */
-
-/**
-  * @brief  Enable MPU with input options
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
-  * @param  Options This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
-  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
-  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
-  /* Enable the MPU*/
-  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
-  /* Ensure MPU settings take effects */
-  __DSB();
-  /* Sequence instruction fetches using update settings */
-  __ISB();
-}
-
-/**
-  * @brief  Disable MPU
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-  /* Disable MPU*/
-  WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
-  * @brief  Check if MPU is enabled or not
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
-  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
-  * @brief  Enable a MPU region
-  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Enable the MPU region */
-  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @brief  Configure and enable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
-  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @param  Address Value of region base address
-  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @param  Attributes This parameter can be a combination of the following values:
-  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
-  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
-  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
-  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
-  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
-  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
-  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
-  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
-  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
-  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
-  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
-  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Set base address */
-  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
-  /* Configure MPU */
-  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
-  * @brief  Disable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
-  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Disable the MPU region */
-  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @}
-  */
-
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crc.h
deleted file mode 100644
index f91f0105399..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crc.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_crc.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_CRC_H
-#define STM32L1xx_LL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(CRC)
-
-/** @defgroup CRC_LL CRC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in CRC register
-  * @param  __INSTANCE__ CRC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
-
-/**
-  * @brief  Read a value in CRC register
-  * @param  __INSTANCE__ CRC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Reset the CRC calculation unit.
-  * @note   If Programmable Initial CRC value feature
-  *         is available, also set the Data Register to the value stored in the
-  *         CRC_INIT register, otherwise, reset Data Register to its default value.
-  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
-  * @param  CRCx CRC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
-{
-  SET_BIT(CRCx->CR, CRC_CR_RESET);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Write given 32-bit data to the CRC calculator
-  * @rmtoll DR           DR            LL_CRC_FeedData32
-  * @param  CRCx CRC Instance
-  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
-{
-  WRITE_REG(CRCx->DR, InData);
-}
-
-/**
-  * @brief  Return current CRC calculation result. 32 bits value is returned.
-  * @rmtoll DR           DR            LL_CRC_ReadData32
-  * @param  CRCx CRC Instance
-  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
-  */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->DR));
-}
-
-/**
-  * @brief  Return data stored in the Independent Data(IDR) register.
-  * @note   This register can be used as a temporary storage location for one byte.
-  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
-  * @param  CRCx CRC Instance
-  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
-  */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
-{
-  return (uint32_t)(READ_REG(CRCx->IDR));
-}
-
-/**
-  * @brief  Store data in the Independent Data(IDR) register.
-  * @note   This register can be used as a temporary storage location for one byte.
-  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
-  * @param  CRCx CRC Instance
-  * @param  InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
-{
-  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
-}
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(CRC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dac.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dac.h
deleted file mode 100644
index 9d161fe13aa..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dac.h
+++ /dev/null
@@ -1,1336 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_dac.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_DAC_H
-#define STM32L1xx_LL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(DAC1)
-
-/** @defgroup DAC_LL DAC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Constants DAC Private Constants
-  * @{
-  */
-
-/* Internal masks for DAC channels definition */
-/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
-/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
-/* - channel bits position into register SWTRIG                               */
-/* - channel register offset of data holding register DHRx                    */
-/* - channel register offset of data output register DORx                     */
-#define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers
-                                                CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers
-                                                CR, MCR, CCR, SHHR, SHRR of channel 2 */
-#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
-
-#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
-#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
-#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
-
-#define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
-                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */
-#define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
-                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */
-
-#define DAC_REG_DHR12R2_REGOFFSET      0x00030000UL            /* Register offset of DHR12Rx channel 2 versus
-                                                                  DHR12Rx channel 1 (shifted left of 16 bits)   */
-#define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
-                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */
-#define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
-                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */
-
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
-#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
-#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK\
-                                        | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-
-#define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
-
-#define DAC_REG_DOR2_REGOFFSET         0x10000000UL            /* Register offset of DORx channel 1 versus
-                                                                  DORx channel 2 (shifted left of 28 bits)   */
-#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
-
-
-#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
-                                                                   DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
-#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted
-                                                                   to position 0                                    */
-#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted
-                                                                   to position 0                                    */
-
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           16UL  /* Position of bits register offset of DHR12Rx
-                                                                   channel 1 or 2 versus DHR12Rx channel 1
-                                                                   (shifted left of 16 bits)                   */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx
-                                                                   channel 1 or 2 versus DHR12Rx channel 1
-                                                                   (shifted left of 20 bits)                   */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx
-                                                                   channel 1 or 2 versus DHR12Rx channel 1
-                                                                   (shifted left of 24 bits)                   */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS              28UL  /* Position of bits register offset of DORx
-                                                                   channel 1 or 2 versus DORx channel 1
-                                                                   (shifted left of 28 bits)                   */
-
-/* DAC registers bits positions */
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
-
-/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS                  4095UL   /* Full-scale digital value with a resolution of 12
-                                                              bits (voltage range determined by analog voltage
-                                                              references Vref+ and Vref-, refer to reference manual) */
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Macros DAC Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Driver macro reserved for internal use: set a pointer to
-  *         a register from a register basis from which an offset
-  *         is applied.
-  * @param  __REG__ Register basis from which the offset is applied.
-  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
-  * @retval Pointer to register address
-  */
-#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
-  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of DAC instance.
-  */
-typedef struct
-{
-  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel:
-                                             internal (SW start) or from external peripheral
-                                             (timer event, external interrupt line).
-                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
-                                             This feature can be modified afterwards using unitary
-                                             function @ref LL_DAC_SetTriggerSource(). */
-
-  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
-                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
-                                             This feature can be modified afterwards using unitary
-                                             function @ref LL_DAC_SetWaveAutoGeneration(). */
-
-  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
-                                             If waveform automatic generation mode is set to noise, this parameter
-                                             can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
-                                             If waveform automatic generation mode is set to triangle,
-                                             this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
-                                             @note If waveform automatic generation mode is disabled,
-                                              this parameter is discarded.
-
-                                             This feature can be modified afterwards using unitary
-                                             function @ref LL_DAC_SetWaveNoiseLFSR(),
-                                             @ref LL_DAC_SetWaveTriangleAmplitude()
-                                             depending on the wave automatic generation selected. */
-
-  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
-                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
-                                             This feature can be modified afterwards using unitary
-                                             function @ref LL_DAC_SetOutputBuffer(). */
-} LL_DAC_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
-  * @brief    Flags defines which can be used with LL_DAC_ReadReg function
-  * @{
-  */
-/* DAC channel 1 flags */
-#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
-
-/* DAC channel 2 flags */
-#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_IT DAC interruptions
-  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
-  * @{
-  */
-#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
-
-#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_CHANNEL DAC channels
-  * @{
-  */
-#define LL_DAC_CHANNEL_1                   (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
-
-#define LL_DAC_CHANNEL_2                   (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
-  * @{
-  */
-#define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000UL                                       /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM9_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
-  * @{
-  */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
-  * @{
-  */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
-  * @{
-  */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
-  * @{
-  */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
-#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
-  * @{
-  */
-#define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
-  * @{
-  */
-/* List of DAC registers intended to be used (most commonly) with             */
-/* DMA transfer.                                                              */
-/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
-  * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-
-/* Delay for DAC channel voltage settling time from DAC channel startup       */
-/* (transition from disable to enable).                                       */
-/* Note: DAC channel startup time depends on board application environment:   */
-/*       impedance connected to DAC channel output.                           */
-/*       The delay below is specified under conditions:                       */
-/*        - voltage maximum transition (lowest to highest value)              */
-/*        - until voltage reaches final value +-1LSB                          */
-/*        - DAC channel output buffer enabled                                 */
-/*        - load impedance of 5kOhm (min), 50pF (max)                         */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tWAKEUP").                                                      */
-/* Unit: us                                                                   */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
-/* Delay for DAC channel voltage settling time.                               */
-/* Note: DAC channel startup time depends on board application environment:   */
-/*       impedance connected to DAC channel output.                           */
-/*       The delay below is specified under conditions:                       */
-/*        - voltage maximum transition (lowest to highest value)              */
-/*        - until voltage reaches final value +-1LSB                          */
-/*        - DAC channel output buffer enabled                                 */
-/*        - load impedance of 5kOhm min, 50pF max                             */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tSETTLING").                                                    */
-/* Unit: us                                                                   */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12UL /*!< Delay for DAC channel voltage settling time */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in DAC register
-  * @param  __INSTANCE__ DAC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DAC register
-  * @param  __INSTANCE__ DAC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to get DAC channel number in decimal format
-  *         from literals LL_DAC_CHANNEL_x.
-  *         Example:
-  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
-  *            will return decimal number "1".
-  * @note   The input can be a value from functions where a channel
-  *         number is returned.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval 1...2
-  */
-#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
-  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
-
-/**
-  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
-  *         from number in decimal format.
-  *         Example:
-  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
-  *           will return a data equivalent to "LL_DAC_CHANNEL_1".
-  * @note  If the input parameter does not correspond to a DAC channel,
-  *        this macro returns value '0'.
-  * @param  __DECIMAL_NB__ 1...2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  */
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
-  (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1  ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
-
-/**
-  * @brief  Helper macro to define the DAC conversion data full-scale digital
-  *         value corresponding to the selected DAC resolution.
-  * @note   DAC conversion data full-scale corresponds to voltage range
-  *         determined by analog voltage references Vref+ and Vref-
-  *         (refer to reference manual).
-  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_RESOLUTION_12B
-  *         @arg @ref LL_DAC_RESOLUTION_8B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
-  ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
-
-/**
-  * @brief  Helper macro to calculate the DAC conversion data (unit: digital
-  *         value) corresponding to a voltage (unit: mVolt).
-  * @note   This helper macro is intended to provide input data in voltage
-  *         rather than digital value,
-  *         to be used with LL DAC functions such as
-  *         @ref LL_DAC_ConvertData12RightAligned().
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
-  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
-  *                         (unit: mVolt).
-  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_RESOLUTION_12B
-  *         @arg @ref LL_DAC_RESOLUTION_8B
-  * @retval DAC conversion data (unit: digital value)
-  */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
-                                      __DAC_VOLTAGE__,\
-                                      __DAC_RESOLUTION__)                      \
-((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
- / (__VREFANALOG_VOLTAGE__)                                                  \
-)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
-  * @{
-  */
-/**
-  * @brief  Set the conversion trigger source for the selected DAC channel.
-  * @note   For conversion trigger source to be effective, DAC trigger
-  *         must be enabled using function @ref LL_DAC_EnableTrigger().
-  * @note   To set conversion trigger source, DAC channel must be disabled.
-  *         Otherwise, the setting is discarded.
-  * @note   Availability of parameters of trigger sources from timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
-  *         CR       TSEL2          LL_DAC_SetTriggerSource
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  TriggerSource This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_TRIG_SOFTWARE
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the conversion trigger source for the selected DAC channel.
-  * @note   For conversion trigger source to be effective, DAC trigger
-  *         must be enabled using function @ref LL_DAC_EnableTrigger().
-  * @note   Availability of parameters of trigger sources from timer
-  *         depends on timers availability on the selected device.
-  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
-  *         CR       TSEL2          LL_DAC_GetTriggerSource
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_TRIG_SOFTWARE
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
-  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the waveform automatic generation mode
-  *         for the selected DAC channel.
-  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
-  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  WaveAutoGeneration This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the waveform automatic generation mode
-  *         for the selected DAC channel.
-  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
-  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
-  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the noise waveform generation for the selected DAC channel:
-  *         Noise mode and parameters LFSR (linear feedback shift register).
-  * @note   For wave generation to be effective, DAC channel
-  *         wave generation mode must be enabled using
-  *         function @ref LL_DAC_SetWaveAutoGeneration().
-  * @note   This setting can be set when the selected DAC channel is disabled
-  *         (otherwise, the setting operation is ignored).
-  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
-  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  NoiseLFSRMask This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the noise waveform generation for the selected DAC channel:
-  *         Noise mode and parameters LFSR (linear feedback shift register).
-  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
-  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
-  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the triangle waveform generation for the selected DAC channel:
-  *         triangle mode and amplitude.
-  * @note   For wave generation to be effective, DAC channel
-  *         wave generation mode must be enabled using
-  *         function @ref LL_DAC_SetWaveAutoGeneration().
-  * @note   This setting can be set when the selected DAC channel is disabled
-  *         (otherwise, the setting operation is ignored).
-  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
-  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  TriangleAmplitude This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
-                                                     uint32_t TriangleAmplitude)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the triangle waveform generation for the selected DAC channel:
-  *         triangle mode and amplitude.
-  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
-  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
-  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @brief  Set the output buffer for the selected DAC channel.
-  * @rmtoll CR       BOFF1          LL_DAC_SetOutputBuffer\n
-  *         CR       BOFF2          LL_DAC_SetOutputBuffer
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  OutputBuffer This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
-{
-  MODIFY_REG(DACx->CR,
-             DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
-             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get the output buffer state for the selected DAC channel.
-  * @rmtoll CR       BOFF1          LL_DAC_GetOutputBuffer\n
-  *         CR       BOFF2          LL_DAC_GetOutputBuffer
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
-  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
-  */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DAC DMA transfer request of the selected channel.
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_DAC_DMA_GetRegAddr().
-  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
-  *         CR       DMAEN2         LL_DAC_EnableDMAReq
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC DMA transfer request of the selected channel.
-  * @note   To configure DMA source address (peripheral address),
-  *         use function @ref LL_DAC_DMA_GetRegAddr().
-  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
-  *         CR       DMAEN2         LL_DAC_DisableDMAReq
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC DMA transfer request state of the selected channel.
-  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
-  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
-  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return ((READ_BIT(DACx->CR,
-                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Function to help to configure DMA transfer to DAC: retrieve the
-  *         DAC register address from DAC instance and a list of DAC registers
-  *         intended to be used (most commonly) with DMA transfer.
-  * @note   These DAC registers are data holding registers:
-  *         when DAC conversion is requested, DAC generates a DMA transfer
-  *         request to have data available in DAC data holding registers.
-  * @note   This macro is intended to be used with LL DMA driver, refer to
-  *         function "LL_DMA_ConfigAddresses()".
-  *         Example:
-  *           LL_DMA_ConfigAddresses(DMA1,
-  *                                  LL_DMA_CHANNEL_1,
-  *                                  (uint32_t)&< array or variable >,
-  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
-  *                                  LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
-  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
-  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
-  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  Register This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
-  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
-  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
-  * @retval DAC register address
-  */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
-{
-  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
-  /* DAC channel selected.                                                    */
-  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
-                                                            & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
-}
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
-  * @{
-  */
-
-/**
-  * @brief  Enable DAC selected channel.
-  * @rmtoll CR       EN1            LL_DAC_Enable\n
-  *         CR       EN2            LL_DAC_Enable
-  * @note   After enable from off state, DAC channel requires a delay
-  *         for output voltage to reach accuracy +/- 1 LSB.
-  *         Refer to device datasheet, parameter "tWAKEUP".
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC selected channel.
-  * @rmtoll CR       EN1            LL_DAC_Disable\n
-  *         CR       EN2            LL_DAC_Disable
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC enable state of the selected channel.
-  *         (0: DAC channel is disabled, 1: DAC channel is enabled)
-  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
-  *         CR       EN2            LL_DAC_IsEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return ((READ_BIT(DACx->CR,
-                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DAC trigger of the selected channel.
-  * @note   - If DAC trigger is disabled, DAC conversion is performed
-  *           automatically once the data holding register is updated,
-  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
-  *           @ref LL_DAC_ConvertData12RightAligned(), ...
-  *         - If DAC trigger is enabled, DAC conversion is performed
-  *           only when a hardware of software trigger event is occurring.
-  *           Select trigger source using
-  *           function @ref LL_DAC_SetTriggerSource().
-  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
-  *         CR       TEN2           LL_DAC_EnableTrigger
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->CR,
-          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Disable DAC trigger of the selected channel.
-  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
-  *         CR       TEN2           LL_DAC_DisableTrigger
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  CLEAR_BIT(DACx->CR,
-            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
-  * @brief  Get DAC trigger state of the selected channel.
-  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
-  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
-  *         CR       TEN2           LL_DAC_IsTriggerEnabled
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  return ((READ_BIT(DACx->CR,
-                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
-           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Trig DAC conversion by software for the selected DAC channel.
-  * @note   Preliminarily, DAC trigger must be set to software trigger
-  *         using function
-  *           @ref LL_DAC_Init()
-  *           @ref LL_DAC_SetTriggerSource()
-  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
-  *         and DAC trigger must be enabled using
-  *         function @ref LL_DAC_EnableTrigger().
-  * @note   For devices featuring DAC with 2 channels: this function
-  *         can perform a SW start of both DAC channels simultaneously.
-  *         Two channels can be selected as parameter.
-  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
-  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
-  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
-  * @param  DACx DAC instance
-  * @param  DAC_Channel  This parameter can a combination of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  SET_BIT(DACx->SWTRIGR,
-          (DAC_Channel & DAC_SWTR_CHX_MASK));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (LSB aligned on bit 0),
-  *         for the selected DAC channel.
-  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
-  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
-                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
-  MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (MSB aligned on bit 15),
-  *         for the selected DAC channel.
-  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
-  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
-                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
-  MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 8 bits left alignment (LSB aligned on bit 0),
-  *         for the selected DAC channel.
-  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
-  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
-  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
-                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
-  MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
-}
-
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (LSB aligned on bit 0),
-  *         for both DAC channels.
-  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
-  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
-                                                          uint32_t DataChannel2)
-{
-  MODIFY_REG(DACx->DHR12RD,
-             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
-             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 12 bits left alignment (MSB aligned on bit 15),
-  *         for both DAC channels.
-  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
-  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
-                                                         uint32_t DataChannel2)
-{
-  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
-  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
-  /*       the 4 LSB must be taken into account for the shift value.          */
-  MODIFY_REG(DACx->DHR12LD,
-             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
-             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
-}
-
-/**
-  * @brief  Set the data to be loaded in the data holding register
-  *         in format 8 bits left alignment (LSB aligned on bit 0),
-  *         for both DAC channels.
-  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
-  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
-  * @param  DACx DAC instance
-  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
-  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
-                                                         uint32_t DataChannel2)
-{
-  MODIFY_REG(DACx->DHR8RD,
-             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
-             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-
-/**
-  * @brief  Retrieve output data currently generated for the selected DAC channel.
-  * @note   Whatever alignment and resolution settings
-  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
-  *         @ref LL_DAC_ConvertData12RightAligned(), ...),
-  *         output data format is 12 bits right aligned (LSB aligned on bit 0).
-  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
-  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
-  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
-                                                   & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
-
-  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Get DAC underrun flag for DAC channel 1
-  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
-  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Get DAC underrun flag for DAC channel 2
-  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
-  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Clear DAC underrun flag for DAC channel 1
-  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
-  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
-}
-
-
-/**
-  * @brief  Clear DAC underrun flag for DAC channel 2
-  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
-  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_LL_EF_IT_Management IT management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-
-/**
-  * @brief  Enable DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-
-
-/**
-  * @brief  Disable DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-
-/**
-  * @brief  Disable DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-
-
-/**
-  * @brief  Get DMA underrun interrupt for DAC channel 1
-  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
-{
-  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Get DMA underrun interrupt for DAC channel 2
-  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
-  * @param  DACx DAC instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
-{
-  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
-void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h
deleted file mode 100644
index c66e4ba8695..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h
+++ /dev/null
@@ -1,1997 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_DMA_H
-#define __STM32L1xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
-  * @{
-  */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
-  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note: The circular buffer mode cannot be used if the memory to memory
-                                               data transfer direction is configured on the selected Channel
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
-  * @{
-  */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
-  * @{
-  */
-#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
-#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
-#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
-#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
-#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
-#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
-#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
-#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
-#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
-#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
-#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
-#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
-#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
-#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
-  * @{
-  */
-#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
-#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
-#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
-#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
-#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
-#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
-#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
-#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
-#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
-#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
-#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
-#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
-#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
-#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
-#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
-#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
-#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
-#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
-#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
-#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
-#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
-  * @{
-  */
-#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
-#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
-  * @{
-  */
-#define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
-#define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
-  * @{
-  */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
-  * @{
-  */
-#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
-#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
-  * @{
-  */
-#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
-  * @{
-  */
-#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
-#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
-  * @{
-  */
-#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
-#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
-  * @{
-  */
-#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
-#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
-  * @{
-  */
-#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
-#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
-#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
-#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
-  * @{
-  */
-/**
-  * @brief  Convert DMAx_Channely into DMAx
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval DMAx
-  */
-#if defined(DMA2)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
-#else
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
-#endif
-
-/**
-  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval LL_DMA_CHANNEL_y
-  */
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-
-/**
-  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
-  * @param  __DMA_INSTANCE__ DMAx
-  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
-  * @retval DMAx_Channely
-  */
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
- DMA2_Channel7)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Enable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_EnableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Disable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_DisableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Check if DMA channel is enabled or disabled.
-  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_EN) == (DMA_CCR_EN));
-}
-
-/**
-  * @brief  Configure all parameters link to DMA transfer.
-  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
-  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
-  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
-  *         CCR          PINC          LL_DMA_ConfigTransfer\n
-  *         CCR          MINC          LL_DMA_ConfigTransfer\n
-  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          PL            LL_DMA_ConfigTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
-  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
-             Configuration);
-}
-
-/**
-  * @brief  Set Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
-  * @brief  Get Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
-  * @brief  Set DMA mode circular or normal.
-  * @note The circular buffer mode cannot be used if the memory-to-memory
-  * data transfer is configured on the selected Channel.
-  * @rmtoll CCR          CIRC          LL_DMA_SetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
-             Mode);
-}
-
-/**
-  * @brief  Get DMA mode circular or normal.
-  * @rmtoll CCR          CIRC          LL_DMA_GetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_CIRC));
-}
-
-/**
-  * @brief  Set Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
-             PeriphOrM2MSrcIncMode);
-}
-
-/**
-  * @brief  Get Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PINC));
-}
-
-/**
-  * @brief  Set Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
-             MemoryOrM2MDstIncMode);
-}
-
-/**
-  * @brief  Get Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_MINC));
-}
-
-/**
-  * @brief  Set Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
-             PeriphOrM2MSrcDataSize);
-}
-
-/**
-  * @brief  Get Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PSIZE));
-}
-
-/**
-  * @brief  Set Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
-             MemoryOrM2MDstDataSize);
-}
-
-/**
-  * @brief  Get Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_MSIZE));
-}
-
-/**
-  * @brief  Set Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Priority This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
-             Priority);
-}
-
-/**
-  * @brief  Get Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_PL));
-}
-
-/**
-  * @brief  Set Number of data to transfer.
-  * @note   This action has no effect if
-  *         channel is enabled.
-  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
-             DMA_CNDTR_NDT, NbData);
-}
-
-/**
-  * @brief  Get Number of data to transfer.
-  * @note   Once the channel is enabled, the return value indicate the
-  *         remaining bytes to be transmitted.
-  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
-                   DMA_CNDTR_NDT));
-}
-
-/**
-  * @brief  Configure the Source and Destination addresses.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
-  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
-  *         CMAR         MA            LL_DMA_ConfigAddresses
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
-                                            uint32_t DstAddress, uint32_t Direction)
-{
-  /* Direction Memory to Periph */
-  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
-  }
-  /* Direction Periph to Memory and Memory to Memory */
-  else
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
-  }
-}
-
-/**
-  * @brief  Set the Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
-}
-
-/**
-  * @brief  Get Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
-  * @brief  Get Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
-  * @brief  Set the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Get the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
-  * @brief  Get the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Channel 1 global interrupt flag.
-  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
-}
-
-/**
-  * @brief  Get Channel 2 global interrupt flag.
-  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
-}
-
-/**
-  * @brief  Get Channel 3 global interrupt flag.
-  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
-}
-
-/**
-  * @brief  Get Channel 4 global interrupt flag.
-  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
-}
-
-/**
-  * @brief  Get Channel 5 global interrupt flag.
-  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
-}
-
-/**
-  * @brief  Get Channel 6 global interrupt flag.
-  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
-}
-
-/**
-  * @brief  Get Channel 7 global interrupt flag.
-  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
-}
-
-/**
-  * @brief  Get Channel 1 transfer complete flag.
-  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
-}
-
-/**
-  * @brief  Get Channel 2 transfer complete flag.
-  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
-}
-
-/**
-  * @brief  Get Channel 3 transfer complete flag.
-  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
-}
-
-/**
-  * @brief  Get Channel 4 transfer complete flag.
-  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
-}
-
-/**
-  * @brief  Get Channel 5 transfer complete flag.
-  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
-}
-
-/**
-  * @brief  Get Channel 6 transfer complete flag.
-  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
-}
-
-/**
-  * @brief  Get Channel 7 transfer complete flag.
-  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
-}
-
-/**
-  * @brief  Get Channel 1 half transfer flag.
-  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
-}
-
-/**
-  * @brief  Get Channel 2 half transfer flag.
-  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
-}
-
-/**
-  * @brief  Get Channel 3 half transfer flag.
-  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
-}
-
-/**
-  * @brief  Get Channel 4 half transfer flag.
-  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
-}
-
-/**
-  * @brief  Get Channel 5 half transfer flag.
-  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
-}
-
-/**
-  * @brief  Get Channel 6 half transfer flag.
-  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
-}
-
-/**
-  * @brief  Get Channel 7 half transfer flag.
-  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
-}
-
-/**
-  * @brief  Get Channel 1 transfer error flag.
-  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
-}
-
-/**
-  * @brief  Get Channel 2 transfer error flag.
-  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
-}
-
-/**
-  * @brief  Get Channel 3 transfer error flag.
-  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
-}
-
-/**
-  * @brief  Get Channel 4 transfer error flag.
-  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
-}
-
-/**
-  * @brief  Get Channel 5 transfer error flag.
-  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
-}
-
-/**
-  * @brief  Get Channel 6 transfer error flag.
-  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
-}
-
-/**
-  * @brief  Get Channel 7 transfer error flag.
-  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
-}
-
-/**
-  * @brief  Clear Channel 1 global interrupt flag.
-  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 global interrupt flag.
-  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 global interrupt flag.
-  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 global interrupt flag.
-  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 global interrupt flag.
-  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-/**
-  * @brief  Clear Channel 6 global interrupt flag.
-  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-/**
-  * @brief  Clear Channel 7 global interrupt flag.
-  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-
-/**
-  * @brief  Clear Channel 1  transfer complete flag.
-  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  transfer complete flag.
-  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  transfer complete flag.
-  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  transfer complete flag.
-  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  transfer complete flag.
-  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-/**
-  * @brief  Clear Channel 6  transfer complete flag.
-  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-/**
-  * @brief  Clear Channel 7  transfer complete flag.
-  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-
-/**
-  * @brief  Clear Channel 1  half transfer flag.
-  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  half transfer flag.
-  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  half transfer flag.
-  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  half transfer flag.
-  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  half transfer flag.
-  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-/**
-  * @brief  Clear Channel 6  half transfer flag.
-  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-/**
-  * @brief  Clear Channel 7  half transfer flag.
-  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-
-/**
-  * @brief  Clear Channel 1 transfer error flag.
-  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 transfer error flag.
-  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 transfer error flag.
-  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 transfer error flag.
-  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 transfer error flag.
-  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-/**
-  * @brief  Clear Channel 6 transfer error flag.
-  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-/**
-  * @brief  Clear Channel 7 transfer error flag.
-  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
-  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
-  * @{
-  */
-/**
-  * @brief  Enable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Enable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Enable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Disable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Disable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Disable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Check if Transfer complete Interrupt is enabled.
-  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_TCIE) == (DMA_CCR_TCIE));
-}
-
-/**
-  * @brief  Check if Half transfer Interrupt is enabled.
-  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_HTIE) == (DMA_CCR_HTIE));
-}
-
-/**
-  * @brief  Check if Transfer error Interrupt is enabled.
-  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
-                   DMA_CCR_TEIE) == (DMA_CCR_TEIE));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h
deleted file mode 100644
index e6b20d09376..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h
+++ /dev/null
@@ -1,1016 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_EXTI_H
-#define STM32L1xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
-  * @{
-  */
-typedef struct
-{
-
-  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
-                                     This parameter can be set either to ENABLE or DISABLE */
-
-  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
-  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
-  * @{
-  */
-#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
-#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
-#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
-#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
-#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
-#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
-#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
-#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
-#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
-#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
-#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
-#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
-#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
-#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
-#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
-#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
-#endif
-#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
-#endif
-#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
-  * @{
-  */
-#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
-  * @}
-  */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in EXTI register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in EXTI register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_24
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
-  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
-  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_20
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* EXTI */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h
deleted file mode 100644
index 62d1bded956..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_fsmc.h
+++ /dev/null
@@ -1,533 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_fsmc.h
-  * @author  MCD Application Team
-  * @brief   Header file of FSMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_FSMC_H
-#define STM32L1xx_LL_FSMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FSMC_LL
-  * @{
-  */
-
-/** @addtogroup FSMC_LL_Private_Macros
-  * @{
-  */
-#if defined(FSMC_BANK1)
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
-                                       ((__BANK__) == FSMC_NORSRAM_BANK2) || \
-                                       ((__BANK__) == FSMC_NORSRAM_BANK3) || \
-                                       ((__BANK__) == FSMC_NORSRAM_BANK4))
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
-                             ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
-                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
-                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
-                                   ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
-                                   ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
-                                   ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
-                                   ((__SIZE__) == FSMC_PAGE_SIZE_1024))
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
-                                      ((__MODE__) == FSMC_ACCESS_MODE_B) || \
-                                      ((__MODE__) == FSMC_ACCESS_MODE_C) || \
-                                      ((__MODE__) == FSMC_ACCESS_MODE_D))
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
-                                     ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                            ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
-                                             ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
-                                               ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
-                                               ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
-                                         ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
-                                        ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                    ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
-                                       ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
-#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
-                                            ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
-#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-#endif /* FSMC_BANK1 */
-
-/**
-  * @}
-  */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
-  * @{
-  */
-
-#if defined(FSMC_BANK1)
-#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
-#endif /* FSMC_BANK1 */
-
-#if defined(FSMC_BANK1)
-#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
-#endif /* FSMC_BANK1 */
-
-#if defined(FSMC_BANK1)
-/**
-  * @brief  FSMC NORSRAM Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                  */
-
-  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
-                                              multiplexed on the data bus or not.
-                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
-  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
-                                              the corresponding memory device.
-                                              This parameter can be a value of @ref FSMC_Memory_Type                   */
-
-  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width            */
-
-  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
-                                              valid only with synchronous burst Flash memories.
-                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode             */
-
-  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
-                                              the Flash memory in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity          */
-
-  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
-                                              memory, valid only when accessing Flash memories in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wrap_Mode                     */
-
-  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
-                                              clock cycle before the wait state or during the wait state,
-                                              valid only when accessing memories in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Timing                   */
-
-  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
-                                              This parameter can be a value of @ref FSMC_Write_Operation               */
-
-  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
-                                              signal, valid for Flash memory access in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Signal                   */
-
-  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
-                                              This parameter can be a value of @ref FSMC_Extended_Mode                 */
-
-  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
-                                              valid only with asynchronous Flash memories.
-                                              This parameter can be a value of @ref FSMC_AsynchronousWait              */
-
-  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
-                                              This parameter can be a value of @ref FSMC_Write_Burst                   */
-
-
-  uint32_t PageSize;                     /*!< Specifies the memory page size.
-                                              This parameter can be a value of @ref FSMC_Page_Size                     */
-} FSMC_NORSRAM_InitTypeDef;
-
-/**
-  * @brief  FSMC NORSRAM Timing parameters structure definition
-  */
-typedef struct
-{
-  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address setup time.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.   */
-
-  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address hold time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.   */
-
-  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the data setup time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
-                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
-                                              NOR Flash memories.                                                     */
-
-  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the bus turnaround.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is only used for multiplexed NOR Flash memories.   */
-
-  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
-                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and
-                                              Max_Data = 16.
-                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
-                                              accesses.                                                               */
-
-  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
-                                              to the memory before getting the first data.
-                                              The parameter value depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between Min_Data = 2 and Max_Data = 17
-                                                in NOR Flash memories with synchronous burst mode enable              */
-
-  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
-                                              This parameter can be a value of @ref FSMC_Access_Mode                   */
-} FSMC_NORSRAM_TimingTypeDef;
-#endif /* FSMC_BANK1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
-  * @{
-  */
-#if defined(FSMC_BANK1)
-
-/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
-  * @{
-  */
-
-/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
-  * @{
-  */
-#define FSMC_NORSRAM_BANK1                       (0x00000000U)
-#define FSMC_NORSRAM_BANK2                       (0x00000002U)
-#define FSMC_NORSRAM_BANK3                       (0x00000004U)
-#define FSMC_NORSRAM_BANK4                       (0x00000006U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
-  * @{
-  */
-#define FSMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Memory_Type FSMC Memory Type
-  * @{
-  */
-#define FSMC_MEMORY_TYPE_SRAM                    (0x00000000U)
-#define FSMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
-#define FSMC_MEMORY_TYPE_NOR                     (0x00000008U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
-  * @{
-  */
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
-  * @{
-  */
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
-  * @{
-  */
-#define FSMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
-#define FSMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
-  * @{
-  */
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
-  * @{
-  */
-#define FSMC_WRAP_MODE_DISABLE                   (0x00000000U)
-#define FSMC_WRAP_MODE_ENABLE                    (0x00000400U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
-  * @{
-  */
-#define FSMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
-#define FSMC_WAIT_TIMING_DURING_WS               (0x00000800U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Operation FSMC Write Operation
-  * @{
-  */
-#define FSMC_WRITE_OPERATION_DISABLE             (0x00000000U)
-#define FSMC_WRITE_OPERATION_ENABLE              (0x00001000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
-  * @{
-  */
-#define FSMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
-#define FSMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
-  * @{
-  */
-#define FSMC_EXTENDED_MODE_DISABLE               (0x00000000U)
-#define FSMC_EXTENDED_MODE_ENABLE                (0x00004000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
-  * @{
-  */
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Page_Size FSMC Page Size
-  * @{
-  */
-#define FSMC_PAGE_SIZE_NONE                      (0x00000000U)
-#define FSMC_PAGE_SIZE_128                       FSMC_BCRx_CPSIZE_0
-#define FSMC_PAGE_SIZE_256                       FSMC_BCRx_CPSIZE_1
-#define FSMC_PAGE_SIZE_512                       (FSMC_BCRx_CPSIZE_0\
-                                                 | FSMC_BCRx_CPSIZE_1)
-#define FSMC_PAGE_SIZE_1024                      FSMC_BCRx_CPSIZE_2
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Burst FSMC Write Burst
-  * @{
-  */
-#define FSMC_WRITE_BURST_DISABLE                 (0x00000000U)
-#define FSMC_WRITE_BURST_ENABLE                  (0x00080000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
-  * @{
-  */
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
-  * @{
-  */
-#define FSMC_ACCESS_MODE_A                       (0x00000000U)
-#define FSMC_ACCESS_MODE_B                       (0x10000000U)
-#define FSMC_ACCESS_MODE_C                       (0x20000000U)
-#define FSMC_ACCESS_MODE_D                       (0x30000000U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* FSMC_BANK1 */
-
-
-
-/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Macros FSMC_LL  Private Macros
-  * @{
-  */
-#if defined(FSMC_BANK1)
-/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
-  * @brief macros to handle NOR device enable/disable and read/write operations
-  * @{
-  */
-
-/**
-  * @brief  Enable the NORSRAM device access.
-  * @param  __INSTANCE__ FSMC_NORSRAM Instance
-  * @param  __BANK__ FSMC_NORSRAM Bank
-  * @retval None
-  */
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
-                                                       |= FSMC_BCRx_MBKEN)
-
-/**
-  * @brief  Disable the NORSRAM device access.
-  * @param  __INSTANCE__ FSMC_NORSRAM Instance
-  * @param  __BANK__ FSMC_NORSRAM Bank
-  * @retval None
-  */
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
-                                                       &= ~FSMC_BCRx_MBKEN)
-
-/**
-  * @}
-  */
-#endif /* FSMC_BANK1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
-  *  @{
-  */
-
-#if defined(FSMC_BANK1)
-/** @defgroup FSMC_LL_NORSRAM  NOR SRAM
-  *  @{
-  */
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
-  *  @{
-  */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
-                                    FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
-                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
-                                                    FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
-                                                    uint32_t ExtendedMode);
-HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
-                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
-  *  @{
-  */
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* FSMC_BANK1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_FSMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h
deleted file mode 100644
index 60938461a21..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h
+++ /dev/null
@@ -1,989 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_GPIO_H
-#define __STM32L1xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
-
-/** @defgroup GPIO_LL GPIO
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL GPIO Init Structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
-                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
-  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
-  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
-  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
-  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
-  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_AF.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
-  * @{
-  */
-#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
-                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
-                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
-                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
-                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
-                                           GPIO_BSRR_BS_15) /*!< Select all pins */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
-  * @{
-  */
-#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
-  * @{
-  */
-#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
-#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
-  * @{
-  */
-#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
-  * @{
-  */
-#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
-  * @{
-  */
-
-/**
-  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
-  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->MODER,
-                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @param  OutputType This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
-  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
-  * @brief  Return gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
-}
-
-/**
-  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Speed This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
-{
-  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
-             (Speed << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
-                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Pull This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
-  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
-                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
-             (Alternate << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
-             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
-}
-
-
-/**
-  * @brief  Lock configuration of several pins for a dedicated port.
-  * @note   When the lock sequence has been applied on a port bit, the
-  *         value of this port bit can no longer be modified until the
-  *         next reset.
-  * @note   Each lock bit freezes a specific configuration register
-  *         (control and alternate function registers).
-  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  __IO uint32_t temp;
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  WRITE_REG(GPIOx->LCKR, PinMask);
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  temp = READ_REG(GPIOx->LCKR);
-  (void) temp;
-}
-
-/**
-  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
-  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
-  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
-  * @param  GPIOx GPIO Port
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
-  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
-  * @{
-  */
-
-/**
-  * @brief  Return full input data register value for a dedicated port.
-  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
-  * @param  GPIOx GPIO Port
-  * @retval Input data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Write output data register for the port.
-  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
-  * @param  GPIOx GPIO Port
-  * @param  PortValue Level value for each pin of the port
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
-  WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
-  * @brief  Return full output data register value for a dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
-  * @param  GPIOx GPIO Port
-  * @retval Output data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Set several pins to high level on dedicated gpio port.
-  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
-  * @brief  Set several pins to low level on dedicated gpio port.
-  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin\n
-  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-#if defined(GPIO_BRR_BR_0)
-  WRITE_REG(GPIOx->BRR, PinMask);
-#else
-  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
-#endif /* GPIO_BRR_BR_0 */
-}
-
-/**
-  * @brief  Toggle data value for several pin of dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  uint32_t odr = READ_REG(GPIOx->ODR);
-  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_i2c.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_i2c.h
deleted file mode 100644
index 7ad74e8334d..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_i2c.h
+++ /dev/null
@@ -1,1784 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_I2C_H
-#define __STM32L1xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/* Defines used to perform compute and check in the macros */
-#define LL_I2C_MAX_SPEED_STANDARD           100000U
-#define LL_I2C_MAX_SPEED_FAST               400000U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
-                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
-
-  uint32_t ClockSpeed;          /*!< Specifies the clock frequency.
-                                     This parameter must be set to a value lower than 400kHz (in Hz)
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
-                                     or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
-
-  uint32_t DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
-                                     This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
-
-  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
-                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-
-  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
-                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
-
-  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
-                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
-
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
-  * @{
-  */
-#define LL_I2C_SR1_SB                       I2C_SR1_SB              /*!< Start Bit (master mode)                   */
-#define LL_I2C_SR1_ADDR                     I2C_SR1_ADDR            /*!< Address sent (master mode) or
-                                                                         Address matched flag (slave mode)         */
-#define LL_I2C_SR1_BTF                      I2C_SR1_BTF             /*!< Byte Transfer Finished flag               */
-#define LL_I2C_SR1_ADD10                    I2C_SR1_ADD10           /*!< 10-bit header sent (master mode)          */
-#define LL_I2C_SR1_STOPF                    I2C_SR1_STOPF           /*!< Stop detection flag (slave mode)          */
-#define LL_I2C_SR1_RXNE                     I2C_SR1_RXNE            /*!< Data register not empty (receivers)       */
-#define LL_I2C_SR1_TXE                      I2C_SR1_TXE             /*!< Data register empty (transmitters)        */
-#define LL_I2C_SR1_BERR                     I2C_SR1_BERR            /*!< Bus error                                 */
-#define LL_I2C_SR1_ARLO                     I2C_SR1_ARLO            /*!< Arbitration lost                          */
-#define LL_I2C_SR1_AF                       I2C_SR1_AF              /*!< Acknowledge failure flag                  */
-#define LL_I2C_SR1_OVR                      I2C_SR1_OVR             /*!< Overrun/Underrun                          */
-#define LL_I2C_SR1_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode)       */
-#define LL_I2C_SR1_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode)       */
-#define LL_I2C_SR1_SMALERT                  I2C_ISR_SMALERT         /*!< SMBus alert (SMBus mode)                  */
-#define LL_I2C_SR2_MSL                      I2C_SR2_MSL             /*!< Master/Slave flag                         */
-#define LL_I2C_SR2_BUSY                     I2C_SR2_BUSY            /*!< Bus busy flag                             */
-#define LL_I2C_SR2_TRA                      I2C_SR2_TRA             /*!< Transmitter/receiver direction            */
-#define LL_I2C_SR2_GENCALL                  I2C_SR2_GENCALL         /*!< General call address (Slave mode)         */
-#define LL_I2C_SR2_SMBDEFAULT               I2C_SR2_SMBDEFAULT      /*!< SMBus Device default address (Slave mode) */
-#define LL_I2C_SR2_SMBHOST                  I2C_SR2_SMBHOST         /*!< SMBus Host address (Slave mode)           */
-#define LL_I2C_SR2_DUALF                    I2C_SR2_DUALF           /*!< Dual flag  (Slave mode)                   */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
-  * @{
-  */
-#define LL_I2C_CR2_ITEVTEN                  I2C_CR2_ITEVTEN         /*!< Events interrupts enable */
-#define LL_I2C_CR2_ITBUFEN                  I2C_CR2_ITBUFEN         /*!< Buffer interrupts enable */
-#define LL_I2C_CR2_ITERREN                  I2C_CR2_ITERREN         /*!< Error interrupts enable  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
-  * @{
-  */
-#define LL_I2C_OWNADDRESS1_7BIT             0x00004000U                                /*!< Own address 1 is a 7-bit address.   */
-#define LL_I2C_OWNADDRESS1_10BIT            (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address.  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
-  * @{
-  */
-#define LL_I2C_DUTYCYCLE_2                  0x00000000U             /*!< I2C fast mode Tlow/Thigh = 2        */
-#define LL_I2C_DUTYCYCLE_16_9               I2C_CCR_DUTY            /*!< I2C fast mode Tlow/Thigh = 16/9     */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
-  * @{
-  */
-#define LL_I2C_CLOCK_SPEED_STANDARD_MODE    0x00000000U             /*!< Master clock speed range is standard mode */
-#define LL_I2C_CLOCK_SPEED_FAST_MODE        I2C_CCR_FS              /*!< Master clock speed range is fast mode     */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
-  * @{
-  */
-#define LL_I2C_MODE_I2C                     0x00000000U                                                 /*!< I2C Master or Slave mode                                    */
-#define LL_I2C_MODE_SMBUS_HOST              (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge                              */
-#define LL_I2C_MODE_SMBUS_DEVICE            I2C_CR1_SMBUS                                               /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP        (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)                   /*!< SMBus Device Default address acknowledge                    */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
-  * @{
-  */
-#define LL_I2C_ACK                          I2C_CR1_ACK             /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK                         0x00000000U             /*!< NACK is sent after current received byte.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
-  * @{
-  */
-#define LL_I2C_DIRECTION_WRITE              I2C_SR2_TRA             /*!< Bus is in write transfer */
-#define LL_I2C_DIRECTION_READ               0x00000000U             /*!< Bus is in read transfer  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Convert Peripheral Clock Frequency in Mhz.
-  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
-  * @retval Value of peripheral clock (in Mhz)
-  */
-#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__)                               (uint32_t)((__PCLK__)/1000000U)
-
-/**
-  * @brief  Convert Peripheral Clock Frequency in Hz.
-  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
-  * @retval Value of peripheral clock (in Hz)
-  */
-#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__)                               (uint32_t)((__PCLK__)*1000000U)
-
-/**
-  * @brief  Compute I2C Clock rising time.
-  * @param  __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
-  * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
-  * @retval Value between Min_Data=0x02 and Max_Data=0x3F
-  */
-#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__)                    (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-
-/**
-  * @brief  Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
-  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
-  * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
-  * @param  __DUTYCYCLE__ This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DUTYCYCLE_2
-  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
-  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
-  */
-#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)       (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
-                                                                                  (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
-                                                                                  (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
-
-/**
-  * @brief  Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
-  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
-  * @param  __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
-  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
-  */
-#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__)             (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
-
-/**
-  * @brief  Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
-  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
-  * @param  __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
-  * @param  __DUTYCYCLE__ This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DUTYCYCLE_2
-  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
-  * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
-  */
-#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)  (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
-                                                                            (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
-                                                                            (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
-
-/**
-  * @brief  Get the Least significant bits of a 10-Bits address.
-  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__)                             ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-/**
-  * @brief  Convert a 10-Bits address to a 10-Bits header with Write direction.
-  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
-  * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
-  */
-#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__)                        ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-
-/**
-  * @brief  Convert a 10-Bits address to a 10-Bits header with Read direction.
-  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
-  * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
-  */
-#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__)                         ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable I2C peripheral (PE = 1).
-  * @rmtoll CR1          PE            LL_I2C_Enable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Disable I2C peripheral (PE = 0).
-  * @rmtoll CR1          PE            LL_I2C_Disable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Check if the I2C peripheral is enabled or disabled.
-  * @rmtoll CR1          PE            LL_I2C_IsEnabled
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
-}
-
-
-/**
-  * @brief  Enable DMA transmission requests.
-  * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
-  * @brief  Disable DMA transmission requests.
-  * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
-  * @brief  Check if DMA transmission requests are enabled or disabled.
-  * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
-  * @brief  Enable DMA reception requests.
-  * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
-  * @brief  Disable DMA reception requests.
-  * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
-  * @brief  Check if DMA reception requests are enabled or disabled.
-  * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer.
-  * @rmtoll DR           DR            LL_I2C_DMA_GetRegAddr
-  * @param  I2Cx I2C Instance.
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t) & (I2Cx->DR);
-}
-
-/**
-  * @brief  Enable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Disable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Check if Clock stretching is enabled or disabled.
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
-}
-
-/**
-  * @brief  Enable General Call.
-  * @note   When enabled the Address 0x00 is ACKed.
-  * @rmtoll CR1          ENGC          LL_I2C_EnableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
-  * @brief  Disable General Call.
-  * @note   When disabled the Address 0x00 is NACKed.
-  * @rmtoll CR1          ENGC          LL_I2C_DisableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
-  * @brief  Check if General Call is enabled or disabled.
-  * @rmtoll CR1          ENGC          LL_I2C_IsEnabledGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
-}
-
-/**
-  * @brief  Set the Own Address1.
-  * @rmtoll OAR1         ADD0          LL_I2C_SetOwnAddress1\n
-  *         OAR1         ADD1_7        LL_I2C_SetOwnAddress1\n
-  *         OAR1         ADD8_9        LL_I2C_SetOwnAddress1\n
-  *         OAR1         ADDMODE       LL_I2C_SetOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
-  * @param  OwnAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
-  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
-  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
-  * @brief  Set the 7bits Own Address2.
-  * @note   This action has no effect if own address2 is enabled.
-  * @rmtoll OAR2         ADD2          LL_I2C_SetOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
-{
-  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         ENDUAL        LL_I2C_EnableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
-  * @brief  Disable  acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         ENDUAL        LL_I2C_DisableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR2         ENDUAL        LL_I2C_IsEnabledOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
-}
-
-/**
-  * @brief  Configure the Peripheral clock frequency.
-  * @rmtoll CR2          FREQ          LL_I2C_SetPeriphClock
-  * @param  I2Cx I2C Instance.
-  * @param  PeriphClock Peripheral Clock (in Hz)
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
-}
-
-/**
-  * @brief  Get the Peripheral clock frequency.
-  * @rmtoll CR2          FREQ          LL_I2C_GetPeriphClock
-  * @param  I2Cx I2C Instance.
-  * @retval Value of Peripheral Clock (in Hz)
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
-}
-
-/**
-  * @brief  Configure the Duty cycle (Fast mode only).
-  * @rmtoll CCR          DUTY          LL_I2C_SetDutyCycle
-  * @param  I2Cx I2C Instance.
-  * @param  DutyCycle This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DUTYCYCLE_2
-  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
-{
-  MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
-}
-
-/**
-  * @brief  Get the Duty cycle (Fast mode only).
-  * @rmtoll CCR          DUTY          LL_I2C_GetDutyCycle
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_DUTYCYCLE_2
-  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
-}
-
-/**
-  * @brief  Configure the I2C master clock speed mode.
-  * @rmtoll CCR          FS            LL_I2C_SetClockSpeedMode
-  * @param  I2Cx I2C Instance.
-  * @param  ClockSpeedMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
-  *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
-{
-  MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
-}
-
-/**
-  * @brief  Get the the I2C master speed mode.
-  * @rmtoll CCR          FS            LL_I2C_GetClockSpeedMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
-  *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
-}
-
-/**
-  * @brief  Configure the SCL, SDA rising time.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll TRISE        TRISE         LL_I2C_SetRiseTime
-  * @param  I2Cx I2C Instance.
-  * @param  RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
-{
-  MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
-}
-
-/**
-  * @brief  Get the SCL, SDA rising time.
-  * @rmtoll TRISE        TRISE         LL_I2C_GetRiseTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x02 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
-}
-
-/**
-  * @brief  Configure the SCL high and low period.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CCR          CCR           LL_I2C_SetClockPeriod
-  * @param  I2Cx I2C Instance.
-  * @param  ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
-{
-  MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
-}
-
-/**
-  * @brief  Get the SCL high and low period.
-  * @rmtoll CCR          CCR           LL_I2C_GetClockPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
-}
-
-/**
-  * @brief  Configure the SCL speed.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR2          FREQ          LL_I2C_ConfigSpeed\n
-  *         TRISE        TRISE         LL_I2C_ConfigSpeed\n
-  *         CCR          FS            LL_I2C_ConfigSpeed\n
-  *         CCR          DUTY          LL_I2C_ConfigSpeed\n
-  *         CCR          CCR           LL_I2C_ConfigSpeed
-  * @param  I2Cx I2C Instance.
-  * @param  PeriphClock Peripheral Clock (in Hz)
-  * @param  ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
-  * @param  DutyCycle This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DUTYCYCLE_2
-  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
-                                        uint32_t DutyCycle)
-{
-  uint32_t freqrange = 0x0U;
-  uint32_t clockconfig = 0x0U;
-
-  /* Compute frequency range */
-  freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
-
-  /* Configure I2Cx: Frequency range register */
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
-
-  /* Configure I2Cx: Rise Time register */
-  MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
-
-  /* Configure Speed mode, Duty Cycle and Clock control register value */
-  if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
-  {
-    /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
-    clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE                                          | \
-                  __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle)        | \
-                  DutyCycle;
-  }
-  else
-  {
-    /* Set Speed mode at standard for Clock Speed request in standard clock range */
-    clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE                                      | \
-                  __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
-  }
-
-  /* Configure I2Cx: Clock control register */
-  MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
-}
-
-/**
-  * @brief  Configure peripheral mode.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBUS         LL_I2C_SetMode\n
-  *         CR1          SMBTYPE       LL_I2C_SetMode\n
-  *         CR1          ENARP         LL_I2C_SetMode
-  * @param  I2Cx I2C Instance.
-  * @param  PeripheralMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
-}
-
-/**
-  * @brief  Get peripheral mode.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBUS         LL_I2C_GetMode\n
-  *         CR1          SMBTYPE       LL_I2C_GetMode\n
-  *         CR1          ENARP         LL_I2C_GetMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
-}
-
-/**
-  * @brief  Enable SMBus alert (Host or Device mode)
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is drived low and
-  *           Alert Response Address Header acknowledge is enabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is supported.
-  * @rmtoll CR1          ALERT         LL_I2C_EnableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
-  * @brief  Disable SMBus alert (Host or Device mode)
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
-  *           Alert Response Address Header acknowledge is disabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is not supported.
-  * @rmtoll CR1          ALERT         LL_I2C_DisableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
-  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ALERT         LL_I2C_IsEnabledSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
-}
-
-/**
-  * @brief  Enable SMBus Packet Error Calculation (PEC).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ENPEC         LL_I2C_EnableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
-  * @brief  Disable SMBus Packet Error Calculation (PEC).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ENPEC         LL_I2C_DisableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
-  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ENPEC         LL_I2C_IsEnabledSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable TXE interrupt.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_TX\n
-  *         CR2          ITBUFEN       LL_I2C_EnableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Disable TXE interrupt.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_TX\n
-  *         CR2          ITBUFEN       LL_I2C_DisableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Check if the TXE Interrupt is enabled or disabled.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_TX\n
-  *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
-  * @brief  Enable RXNE interrupt.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_RX\n
-  *         CR2          ITBUFEN       LL_I2C_EnableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Disable RXNE interrupt.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_RX\n
-  *         CR2          ITBUFEN       LL_I2C_DisableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Check if the RXNE Interrupt is enabled or disabled.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_RX\n
-  *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
-  * @brief  Enable Events interrupts.
-  * @note   Any of these events will generate interrupt :
-  *         Start Bit (SB)
-  *         Address sent, Address matched (ADDR)
-  *         10-bit header sent (ADD10)
-  *         Stop detection  (STOPF)
-  *         Byte transfer finished (BTF)
-  *
-  * @note   Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
-  *         Receive buffer not empty (RXNE)
-  *         Transmit buffer empty (TXE)
-  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_EVT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
-  * @brief  Disable Events interrupts.
-  * @note   Any of these events will generate interrupt :
-  *         Start Bit (SB)
-  *         Address sent, Address matched (ADDR)
-  *         10-bit header sent (ADD10)
-  *         Stop detection  (STOPF)
-  *         Byte transfer finished (BTF)
-  *         Receive buffer not empty (RXNE)
-  *         Transmit buffer empty (TXE)
-  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_EVT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
-  * @brief  Check if Events interrupts are enabled or disabled.
-  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_EVT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
-}
-
-/**
-  * @brief  Enable Buffer interrupts.
-  * @note   Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
-  *         Receive buffer not empty (RXNE)
-  *         Transmit buffer empty (TXE)
-  * @rmtoll CR2          ITBUFEN       LL_I2C_EnableIT_BUF
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Disable Buffer interrupts.
-  * @note   Any of these Buffer events will generate interrupt :
-  *         Receive buffer not empty (RXNE)
-  *         Transmit buffer empty (TXE)
-  * @rmtoll CR2          ITBUFEN       LL_I2C_DisableIT_BUF
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
-  * @brief  Check if Buffer interrupts are enabled or disabled.
-  * @rmtoll CR2          ITBUFEN       LL_I2C_IsEnabledIT_BUF
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
-}
-
-/**
-  * @brief  Enable Error interrupts.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Bus Error detection (BERR)
-  *         Arbitration Loss (ARLO)
-  *         Acknowledge Failure(AF)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (SMBALERT)
-  * @rmtoll CR2          ITERREN       LL_I2C_EnableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
-  * @brief  Disable Error interrupts.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Bus Error detection (BERR)
-  *         Arbitration Loss (ARLO)
-  *         Acknowledge Failure(AF)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (SMBALERT)
-  * @rmtoll CR2          ITERREN       LL_I2C_DisableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
-  * @brief  Check if Error interrupts are enabled or disabled.
-  * @rmtoll CR2          ITERREN       LL_I2C_IsEnabledIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
-  * @{
-  */
-
-/**
-  * @brief  Indicate the status of Transmit data register empty flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll SR1          TXE           LL_I2C_IsActiveFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
-}
-
-/**
-  * @brief  Indicate the status of Byte Transfer Finished flag.
-  *         RESET: When Data byte transfer not done.
-  *         SET: When Data byte transfer succeeded.
-  * @rmtoll SR1          BTF           LL_I2C_IsActiveFlag_BTF
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
-}
-
-/**
-  * @brief  Indicate the status of Receive data register not empty flag.
-  * @note   RESET: When Receive data register is read.
-  *         SET: When the received data is copied in Receive data register.
-  * @rmtoll SR1          RXNE          LL_I2C_IsActiveFlag_RXNE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
-}
-
-/**
-  * @brief  Indicate the status of Start Bit (master mode).
-  * @note   RESET: When No Start condition.
-  *         SET: When Start condition is generated.
-  * @rmtoll SR1          SB            LL_I2C_IsActiveFlag_SB
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
-}
-
-/**
-  * @brief  Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
-  * @rmtoll SR1          ADDR          LL_I2C_IsActiveFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
-}
-
-/**
-  * @brief  Indicate the status of 10-bit header sent (master mode).
-  * @note   RESET: When no ADD10 event occurred.
-  *         SET: When the master has sent the first address byte (header).
-  * @rmtoll SR1          ADD10         LL_I2C_IsActiveFlag_ADD10
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
-}
-
-/**
-  * @brief  Indicate the status of Acknowledge failure flag.
-  * @note   RESET: No acknowledge failure.
-  *         SET: When an acknowledge failure is received after a byte transmission.
-  * @rmtoll SR1          AF            LL_I2C_IsActiveFlag_AF
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
-}
-
-/**
-  * @brief  Indicate the status of Stop detection flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When a Stop condition is detected.
-  * @rmtoll SR1          STOPF         LL_I2C_IsActiveFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
-}
-
-/**
-  * @brief  Indicate the status of Bus error flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a misplaced Start or Stop condition is detected.
-  * @rmtoll SR1          BERR          LL_I2C_IsActiveFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
-}
-
-/**
-  * @brief  Indicate the status of Arbitration lost flag.
-  * @note   RESET: Clear default value.
-  *         SET: When arbitration lost.
-  * @rmtoll SR1          ARLO          LL_I2C_IsActiveFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
-}
-
-/**
-  * @brief  Indicate the status of Overrun/Underrun flag.
-  * @note   RESET: Clear default value.
-  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
-  * @rmtoll SR1          OVR           LL_I2C_IsActiveFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
-}
-
-/**
-  * @brief  Indicate the status of SMBus PEC error flag in reception.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR1          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
-}
-
-/**
-  * @brief  Indicate the status of SMBus Timeout detection flag.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR1          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
-}
-
-/**
-  * @brief  Indicate the status of SMBus alert flag.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR1          SMBALERT      LL_I2C_IsActiveSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
-}
-
-/**
-  * @brief  Indicate the status of Bus Busy flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Start condition is detected.
-  * @rmtoll SR2          BUSY          LL_I2C_IsActiveFlag_BUSY
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
-}
-
-/**
-  * @brief  Indicate the status of Dual flag.
-  * @note   RESET: Received address matched with OAR1.
-  *         SET: Received address matched with OAR2.
-  * @rmtoll SR2          DUALF         LL_I2C_IsActiveFlag_DUAL
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
-}
-
-/**
-  * @brief  Indicate the status of SMBus Host address reception (Slave mode).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: No SMBus Host address
-  *         SET: SMBus Host address received.
-  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
-  * @rmtoll SR2          SMBHOST       LL_I2C_IsActiveSMBusFlag_SMBHOST
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
-}
-
-/**
-  * @brief  Indicate the status of SMBus Device default address reception (Slave mode).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: No SMBus Device default address
-  *         SET: SMBus Device default address received.
-  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
-  * @rmtoll SR2          SMBDEFAULT    LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
-}
-
-/**
-  * @brief  Indicate the status of General call address reception (Slave mode).
-  * @note   RESET: No General call address
-  *         SET: General call address received.
-  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
-  * @rmtoll SR2          GENCALL       LL_I2C_IsActiveFlag_GENCALL
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
-}
-
-/**
-  * @brief  Indicate the status of Master/Slave flag.
-  * @note   RESET: Slave Mode.
-  *         SET: Master Mode.
-  * @rmtoll SR2          MSL           LL_I2C_IsActiveFlag_MSL
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
-}
-
-/**
-  * @brief  Clear Address Matched flag.
-  * @note   Clearing this flag is done by a read access to the I2Cx_SR1
-  *         register followed by a read access to the I2Cx_SR2 register.
-  * @rmtoll SR1          ADDR          LL_I2C_ClearFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = I2Cx->SR1;
-  (void) tmpreg;
-  tmpreg = I2Cx->SR2;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Acknowledge failure flag.
-  * @rmtoll SR1          AF            LL_I2C_ClearFlag_AF
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
-}
-
-/**
-  * @brief  Clear Stop detection flag.
-  * @note   Clearing this flag is done by a read access to the I2Cx_SR1
-  *         register followed by a write access to I2Cx_CR1 register.
-  * @rmtoll SR1          STOPF         LL_I2C_ClearFlag_STOP\n
-  *         CR1          PE            LL_I2C_ClearFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = I2Cx->SR1;
-  (void) tmpreg;
-  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Clear Bus error flag.
-  * @rmtoll SR1          BERR          LL_I2C_ClearFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
-}
-
-/**
-  * @brief  Clear Arbitration lost flag.
-  * @rmtoll SR1          ARLO          LL_I2C_ClearFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
-}
-
-/**
-  * @brief  Clear Overrun/Underrun flag.
-  * @rmtoll SR1          OVR           LL_I2C_ClearFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
-}
-
-/**
-  * @brief  Clear SMBus PEC error flag.
-  * @rmtoll SR1          PECERR        LL_I2C_ClearSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
-}
-
-/**
-  * @brief  Clear SMBus Timeout detection flag.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR1          TIMEOUT       LL_I2C_ClearSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
-}
-
-/**
-  * @brief  Clear SMBus Alert flag.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR1          SMBALERT      LL_I2C_ClearSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable Reset of I2C peripheral.
-  * @rmtoll CR1          SWRST         LL_I2C_EnableReset
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
-  * @brief  Disable Reset of I2C peripheral.
-  * @rmtoll CR1          SWRST         LL_I2C_DisableReset
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
-  * @brief  Check if the I2C peripheral is under reset state or not.
-  * @rmtoll CR1          SWRST         LL_I2C_IsResetEnabled
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
-}
-
-/**
-  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
-  * @note   Usage in Slave or Master mode.
-  * @rmtoll CR1          ACK           LL_I2C_AcknowledgeNextData
-  * @param  I2Cx I2C Instance.
-  * @param  TypeAcknowledge This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ACK
-  *         @arg @ref LL_I2C_NACK
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
-}
-
-/**
-  * @brief  Generate a START or RESTART condition
-  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
-  *         This action has no effect when RELOAD is set.
-  * @rmtoll CR1          START         LL_I2C_GenerateStartCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_START);
-}
-
-/**
-  * @brief  Generate a STOP condition after the current byte transfer (master mode).
-  * @rmtoll CR1          STOP          LL_I2C_GenerateStopCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
-}
-
-/**
-  * @brief  Enable bit POS (master/host mode).
-  * @note   In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
-  * @rmtoll CR1          POS           LL_I2C_EnableBitPOS
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
-  * @brief  Disable bit POS (master/host mode).
-  * @note   In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
-  * @rmtoll CR1          POS           LL_I2C_DisableBitPOS
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
-  * @brief  Check if bit POS  is enabled or disabled.
-  * @rmtoll CR1          POS           LL_I2C_IsEnabledBitPOS
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
-}
-
-/**
-  * @brief  Indicate the value of transfer direction.
-  * @note   RESET: Bus is in read transfer (peripheral point of view).
-  *         SET: Bus is in write transfer (peripheral point of view).
-  * @rmtoll SR2          TRA           LL_I2C_GetTransferDirection
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_DIRECTION_WRITE
-  *         @arg @ref LL_I2C_DIRECTION_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
-}
-
-/**
-  * @brief  Enable DMA last transfer.
-  * @note   This action mean that next DMA EOT is the last transfer.
-  * @rmtoll CR2          LAST          LL_I2C_EnableLastDMA
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
-  * @brief  Disable DMA last transfer.
-  * @note   This action mean that next DMA EOT is not the last transfer.
-  * @rmtoll CR2          LAST          LL_I2C_DisableLastDMA
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
-  * @brief  Check if DMA last transfer is enabled or disabled.
-  * @rmtoll CR2          LAST          LL_I2C_IsEnabledLastDMA
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
-}
-
-/**
-  * @brief  Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This feature is cleared by hardware when the PEC byte is transferred or compared,
-  *         or by a START or STOP condition, it is also cleared by software.
-  * @rmtoll CR1          PEC           LL_I2C_EnableSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
-  * @brief  Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PEC           LL_I2C_DisableSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
-  * @brief  Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PEC           LL_I2C_IsEnabledSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
-}
-
-/**
-  * @brief  Get the SMBus Packet Error byte calculated.
-  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll SR2          PEC           LL_I2C_GetSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
-}
-
-/**
-  * @brief  Read Receive Data register.
-  * @rmtoll DR           DR            LL_I2C_ReceiveData8
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
-  return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
-}
-
-/**
-  * @brief  Write in Transmit Data Register .
-  * @rmtoll DR           DR            LL_I2C_TransmitData8
-  * @param  I2Cx I2C Instance.
-  * @param  Data Value between Min_Data=0x0 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
-  MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_iwdg.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_iwdg.h
deleted file mode 100644
index 00d607087ec..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_iwdg.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_iwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of IWDG LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_IWDG_H
-#define STM32L1xx_LL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(IWDG)
-
-/** @defgroup IWDG_LL IWDG
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
-  * @{
-  */
-#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
-#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
-  * @{
-  */
-#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
-#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
-  * @{
-  */
-#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
-#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
-#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
-#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
-#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
-#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
-#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in IWDG register
-  * @param  __INSTANCE__ IWDG Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in IWDG register
-  * @param  __INSTANCE__ IWDG Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
-  * @{
-  */
-/** @defgroup IWDG_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Start the Independent Watchdog
-  * @note   Except if the hardware watchdog option is selected
-  * @rmtoll KR           KEY           LL_IWDG_Enable
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
-}
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
-}
-
-/**
-  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
-  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
-}
-
-/**
-  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
-  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
-  * @param  IWDGx IWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
-{
-  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
-}
-
-/**
-  * @brief  Select the prescaler of the IWDG
-  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
-  * @param  IWDGx IWDG Instance
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_IWDG_PRESCALER_4
-  *         @arg @ref LL_IWDG_PRESCALER_8
-  *         @arg @ref LL_IWDG_PRESCALER_16
-  *         @arg @ref LL_IWDG_PRESCALER_32
-  *         @arg @ref LL_IWDG_PRESCALER_64
-  *         @arg @ref LL_IWDG_PRESCALER_128
-  *         @arg @ref LL_IWDG_PRESCALER_256
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
-{
-  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
-}
-
-/**
-  * @brief  Get the selected prescaler of the IWDG
-  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
-  * @param  IWDGx IWDG Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_IWDG_PRESCALER_4
-  *         @arg @ref LL_IWDG_PRESCALER_8
-  *         @arg @ref LL_IWDG_PRESCALER_16
-  *         @arg @ref LL_IWDG_PRESCALER_32
-  *         @arg @ref LL_IWDG_PRESCALER_64
-  *         @arg @ref LL_IWDG_PRESCALER_128
-  *         @arg @ref LL_IWDG_PRESCALER_256
-  */
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
-{
-  return (READ_REG(IWDGx->PR));
-}
-
-/**
-  * @brief  Specify the IWDG down-counter reload value
-  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
-{
-  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
-}
-
-/**
-  * @brief  Get the specified IWDG down-counter reload value
-  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
-  * @param  IWDGx IWDG Instance
-  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
-  */
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
-{
-  return (READ_REG(IWDGx->RLR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if flag Prescaler Value Update is set or not
-  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
-  * @param  IWDGx IWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if flag Reload Value Update is set or not
-  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
-  * @param  IWDGx IWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if flags Prescaler & Reload Value Update are reset or not
-  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
-  *         SR           RVU           LL_IWDG_IsReady
-  * @param  IWDGx IWDG Instance
-  * @retval State of bits (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
-{
-  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* IWDG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_opamp.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_opamp.h
deleted file mode 100644
index 2b1ccdda936..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_opamp.h
+++ /dev/null
@@ -1,917 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_opamp.h
-  * @author  MCD Application Team
-  * @brief   Header file of OPAMP LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_OPAMP_H
-#define __STM32L1xx_LL_OPAMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) 
-
-/** @defgroup OPAMP_LL OPAMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
-  * @{
-  */
-
-/* Internal mask for OPAMP power mode:                                        */
-/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for:         */
-/* - OPAMP power mode into control register                                   */
-/* - OPAMP trimming register offset                                           */
-
-/* Internal register offset for OPAMP trimming configuration */
-#define OPAMP_POWERMODE_OTR_REGOFFSET       (0x00000000U)
-#define OPAMP_POWERMODE_LPOTR_REGOFFSET     (0x00000001U)
-#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
-
-/* Mask for OPAMP power mode into control register */
-#define OPAMP_POWERMODE_CSR_BIT_MASK        (OPAMP_CSR_OPA1LPM)
-
-/* Internal mask for OPAMP trimming of transistors differential pair NMOS     */
-/* or PMOS.                                                                   */
-/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
-/* - OPAMP trimming selection of transistors differential pair                */
-/* - OPAMP trimming values of transistors differential pair                   */
-#define OPAMP_TRIMMING_SELECT_SW_OFFSET     (16U)
-#define OPAMP_TRIMMING_SELECT_MASK          ((OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1CAL_L) << OPAMP_TRIMMING_SELECT_SW_OFFSET)
-#define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH | OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW)
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Driver macro reserved for internal use: set a pointer to
-  *         a register from a register basis from which an offset
-  *         is applied.
-  * @param  __REG__ Register basis from which the offset is applied.
-  * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).
-  * @retval Register address
-*/
-#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
-
-/**
-  * @brief  Driver macro reserved for internal use: from OPAMP instance
-  *         selected, return the instance number in decimal format.
-  * @param  __OPAMP_INSTANCE__ OPAMP instance
-  * @retval Instance number in decimal format: value "0" for OPAMP1,
-  *         value "1" for OPAMP2, value "2" for OPAMP3.
-*/
-#define __OPAMP_INSTANCE_DECIMAL(__OPAMP_INSTANCE__)                           \
-  ((uint32_t)(__OPAMP_INSTANCE__) - OPAMP_BASE)
-
-/**
-  * @brief  Driver macro reserved for internal use: from OPAMP instance
-  *         selected, set offset of bits into OPAMP register.
-  * @note   Since all OPAMP instances are sharing the same register
-  *         with 3 area of bits with an offset of 8 bits (except bits
-  *         OPAxCALOUT, OPARANGE, S7SEL2), this function
-  *         returns .
-  * @param  __OPAMP_INSTANCE__ OPAMP instance
-  * @retval Bits offset in register 32 bits: value "0" for OPAMP1,
-  *         value "8" for OPAMP2, value "16" for OPAMP3
-*/
-#define __OPAMP_INSTANCE_BITOFFSET(__OPAMP_INSTANCE__)                         \
-  (((uint32_t)(__OPAMP_INSTANCE__) - OPAMP_BASE) << 3U)
-
-/**
-  * @brief  Driver macro reserved for internal use: from OPAMP instance
-  *         selected, return whether it corresponds to instance OPAMP2.
-  * @param  __OPAMP_INSTANCE__ OPAMP instance
-  * @retval Instance number in decimal format: value "0" for OPAMP1 or OPAMP3,
-  *         value "1" for OPAMP2.
-*/
-#define __OPAMP_IS_INSTANCE_OPAMP2(__OPAMP_INSTANCE__)                         \
-  (((uint32_t)(__OPAMP_INSTANCE__) - OPAMP_BASE) % 2)
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  Structure definition of some features of OPAMP instance.
-  */
-typedef struct
-{
-  uint32_t PowerMode;                   /*!< Set OPAMP power mode.
-                                             This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
-
-  uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
-                                             This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
-
-  uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.
-                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
-
-  uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.
-                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
-                                             @note OPAMP inverting input is used with OPAMP in mode standalone. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
-                                             
-                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
-
-} LL_OPAMP_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
-  * @{
-  */
-
-/** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
-  * @{
-  */
-#define LL_OPAMP_POWERSUPPLY_RANGE_LOW  (0x00000000U)           /*!< Power supply range low. On STM32L1 serie: Vdda lower than 2.4V. */
-#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP_CSR_AOP_RANGE)   /*!< Power supply range high. On STM32L1 serie: Vdda higher than 2.4V. */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
-  * @{
-  */
-#define LL_OPAMP_POWERMODE_NORMAL       (OPAMP_POWERMODE_OTR_REGOFFSET)                       /*!< OPAMP power mode normal */
-#define LL_OPAMP_POWERMODE_LOWPOWER     (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPA1LPM) /*!< OPAMP power mode low-power */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
-  * @{
-  */
-#define LL_OPAMP_MODE_FUNCTIONAL        (0x00000000U)                                                                                  /*!< OPAMP functional mode */
-#define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | OPAMP_CSR_S7SEL2) /*!< OPAMP calibration mode (on STM32L1 serie, it corresponds to all OPAMP input internal switches opened) */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
-  * @{
-  */
-#define LL_OPAMP_MODE_STANDALONE        (0x00000000U)           /*!< OPAMP functional mode, OPAMP operation in standalone (on STM32L1 serie, it corresponds to OPAMP internal switches S3 opened (switch SanB state depends on switch S4 state)) */
-#define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_S3SEL1)      /*!< OPAMP functional mode, OPAMP operation in follower (on STM32L1 serie, it corresponds to OPAMP internal switches S3 and SanB closed) */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
-  * @{
-  */
-#define LL_OPAMP_INPUT_NONINVERT_IO0      (OPAMP_CSR_S5SEL1)      /*!< OPAMP non inverting input connected to GPIO pin (low leakage input) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH1    (OPAMP_CSR_S6SEL1)      /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP1, OPAMP2) */
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH2    (OPAMP_CSR_S7SEL2)      /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP2, OPAMP3) */
-#if defined(OPAMP3)
-#define LL_OPAMP_INPUT_NONINV_DAC1_CH2_OPAMP3 (OPAMP_CSR_S6SEL1)  /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP3) */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
-  * @{
-  */
-#define LL_OPAMP_INPUT_INVERT_IO0        (OPAMP_CSR_S4SEL1)      /*!< OPAMP inverting input connected to GPIO pin (low leakage input). Note: OPAMP inverting input is used with OPAMP in mode standalone. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_IO1        (OPAMP_CSR_ANAWSEL1)    /*!< OPAMP inverting input connected to GPIO pin (alternative IO pin, not low leakage, availability depends on STM32L1 serie devices packages). Note: OPAMP inverting input is used with OPAMP in mode standalone. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (0x00000000U)           /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower) */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
-  * @{
-  */
-#define LL_OPAMP_TRIMMING_FACTORY       (0x00000000U)           /*!< OPAMP trimming factors set to factory values */
-#define LL_OPAMP_TRIMMING_USER          (OPAMP_OTR_OT_USER)     /*!< OPAMP trimming factors set to user values */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
-  * @{
-  */
-#define LL_OPAMP_TRIMMING_NMOS          (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH | (OPAMP_CSR_OPA1CAL_H << OPAMP_TRIMMING_SELECT_SW_OFFSET)) /*!< OPAMP trimming of transistors differential pair NMOS */
-#define LL_OPAMP_TRIMMING_PMOS          (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW  | (OPAMP_CSR_OPA1CAL_L << OPAMP_TRIMMING_SELECT_SW_OFFSET)) /*!< OPAMP trimming of transistors differential pair PMOS */
-#define LL_OPAMP_TRIMMING_NONE          (0x00000000U)                                                                                   /*!< OPAMP trimming unselect transistors differential pair NMOS and PMOs */
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
-  * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
-  *         not timeout values.
-  *         For details on delays values, refer to descriptions in source code
-  *         above each literal definition.
-  * @{
-  */
-
-/* Delay for OPAMP startup time (transition from state disable to enable).    */
-/* Note: OPAMP startup time depends on board application environment:         */
-/*       impedance connected to OPAMP output.                                 */
-/*       The delay below is specified under conditions:                       */
-/*        - OPAMP in mode low power                                           */
-/*        - load impedance of 4kOhm (min), 50pF (max)                         */
-/* Literal set to maximum value (refer to device datasheet,                   */
-/* parameter "tWAKEUP").                                                      */
-/* Unit: us                                                                   */
-#define LL_OPAMP_DELAY_STARTUP_US         (30U)  /*!< Delay for OPAMP startup time */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
-  * @{
-  */
-/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
-  * @{
-  */
-/**
-  * @brief  Write a value in OPAMP register
-  * @param  __INSTANCE__ OPAMP Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in OPAMP register
-  * @param  __INSTANCE__ OPAMP Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to select the OPAMP common instance
-  *         to which is belonging the selected OPAMP instance.
-  * @note   OPAMP common register instance can be used to
-  *         set parameters common to several OPAMP instances.
-  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
-  * @param  __OPAMPx__ OPAMP instance
-  * @retval OPAMP common instance
-  */
-#if defined(OPAMP1) && defined(OPAMP2) && defined(OPAMP3)
-#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
-  (OPAMP123_COMMON)
-#else
-#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \
-  (OPAMP12_COMMON)
-#endif
-
-/**
-  * @brief  Helper macro to check if all OPAMP instances sharing the same
-  *         OPAMP common instance are disabled.
-  * @note   This check is required by functions with setting conditioned to
-  *         OPAMP state:
-  *         All OPAMP instances of the OPAMP common group must be disabled.
-  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
-  * @retval 0: All OPAMP instances sharing the same OPAMP common instance
-  *            are disabled.
-  *         1: At least one OPAMP instance sharing the same OPAMP common instance
-  *            is enabled
-  */
-#if defined(OPAMP1) && defined(OPAMP2) && defined(OPAMP3)
-#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
-  (LL_OPAMP_IsEnabled(OPAMP1) |                                                \
-   LL_OPAMP_IsEnabled(OPAMP2) |                                                \
-   LL_OPAMP_IsEnabled(OPAMP3)  )
-#else
-#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \
-  (LL_OPAMP_IsEnabled(OPAMP1) |                                                \
-   LL_OPAMP_IsEnabled(OPAMP2)  )
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
-  * @{
-  */
-
-/** @defgroup OPAMP_LL_EF_Configuration_opamp_common Configuration of OPAMP hierarchical scope: common to several OPAMP instances
-  * @{
-  */
-
-/**
-  * @brief  Set OPAMP power range.
-  * @note   The OPAMP power range applies to several OPAMP instances
-  *         (if several OPAMP instances available on the selected device).
-  * @note   On this STM32 serie, setting of this feature is conditioned to
-  *         OPAMP state:
-  *         All OPAMP instances of the OPAMP common group must be disabled.
-  *         This check can be done with function @ref LL_OPAMP_IsEnabled() for each
-  *         OPAMP instance or by using helper macro
-  *         @ref __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE().
-  * @rmtoll CSR      AOP_RANGE      LL_OPAMP_SetCommonPowerRange
-  * @param  OPAMPxy_COMMON OPAMP common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
-  * @param  PowerRange This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
-  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
-{
-  /* Prevent unused parameter warning */
-  (void)(OPAMPxy_COMMON);
-    
-  MODIFY_REG(OPAMP->CSR, OPAMP_CSR_AOP_RANGE, PowerRange);
-}
-
-/**
-  * @brief  Get OPAMP power range.
-  * @note   The OPAMP power range applies to several OPAMP instances
-  *         (if several OPAMP instances available on the selected device).
-  * @rmtoll CSR      AOP_RANGE      LL_OPAMP_GetCommonPowerRange
-  * @param  OPAMPxy_COMMON OPAMP common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
-  *         @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
-{
-  /* Prevent unused parameter warning */
-  (void)(OPAMPxy_COMMON);
-
-  return (uint32_t)(READ_BIT(OPAMP->CSR, OPAMP_CSR_AOP_RANGE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
-  * @{
-  */
-
-/**
-  * @brief  Set OPAMP power mode.
-  * @note   The OPAMP must be disabled to change this configuration.
-  * @rmtoll CSR      OPA1LPM        LL_OPAMP_SetPowerMode\n
-  *         CSR      OPA2LPM        LL_OPAMP_SetPowerMode\n
-  *         CSR      OPA3LPM        LL_OPAMP_SetPowerMode
-  * @param  OPAMPx OPAMP instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
-  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
-{
-  MODIFY_REG(OPAMP->CSR,
-             OPAMP_CSR_OPA1LPM << __OPAMP_INSTANCE_BITOFFSET(OPAMPx),
-             (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx));
-}
-
-/**
-  * @brief  Get OPAMP power mode.
-  * @rmtoll CSR      OPA1LPM        LL_OPAMP_GetPowerMode\n
-  *         CSR      OPA2LPM        LL_OPAMP_GetPowerMode\n
-  *         CSR      OPA3LPM        LL_OPAMP_GetPowerMode
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
-  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
-{
-  uint32_t power_mode = (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPA1LPM << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)));
-  
-  /* Shift variable to position corresponding to bitfield of OPAMP1 */
-  power_mode >>= __OPAMP_INSTANCE_BITOFFSET(OPAMPx);
-  
-  /* Construct data corresponding to literal LL_OPAMP_POWERMODE_x */
-  return (uint32_t)(power_mode | (power_mode >> (POSITION_VAL(OPAMP_CSR_OPA1LPM))));
-}
-
-/**
-  * @brief  Set OPAMP mode calibration or functional.
-  * @note   OPAMP mode corresponds to functional or calibration mode:
-  *          - functional mode: OPAMP operation in standalone, follower, ...
-  *            Set functional mode using function
-  *            @ref LL_OPAMP_SetFunctionalMode().
-  *          - calibration mode: offset calibration of the selected
-  *            transistors differential pair NMOS or PMOS.
-  * @note   On this STM32 serie, entering in calibration mode makes
-  *         loosing OPAMP internal switches configuration.
-  *         Therefore, when going back to functional mode,
-  *         functional mode must be set again using
-  *         @ref LL_OPAMP_SetFunctionalMode().
-  * @rmtoll CSR      S3SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S4SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S5SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S6SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S7SEL2         LL_OPAMP_SetMode
-  * @param  OPAMPx OPAMP instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
-  *         @arg @ref LL_OPAMP_MODE_CALIBRATION
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
-{
-  CLEAR_BIT(OPAMP->CSR,
-            ((Mode & ~OPAMP_CSR_S7SEL2) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | ((Mode & OPAMP_CSR_S7SEL2) * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx)));
-}
-
-/**
-  * @brief  Get OPAMP mode calibration or functional.
-  * @note   OPAMP mode corresponds to functional or calibration mode:
-  *          - functional mode: OPAMP operation in standalone, follower, ...
-  *            Set functional mode using function
-  *            @ref LL_OPAMP_SetFunctionalMode().
-  *          - calibration mode: offset calibration of the selected
-  *            transistors differential pair NMOS or PMOS.
-  * @rmtoll CSR      S3SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S4SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S5SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S6SELx         LL_OPAMP_SetMode\n
-  * @rmtoll CSR      S7SEL2         LL_OPAMP_SetMode
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL
-  *         @arg @ref LL_OPAMP_MODE_CALIBRATION
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
-{
-  return (uint32_t)(((READ_BIT(OPAMP->CSR,
-                               ((LL_OPAMP_MODE_CALIBRATION & ~OPAMP_CSR_S7SEL2) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx)))
-                     ) == 0U) * LL_OPAMP_MODE_CALIBRATION);
-}
-
-/**
-  * @brief  Set OPAMP functional mode by setting internal connections.
-  *         OPAMP operation in standalone, follower, ...
-  * @note   This function reset bit of calibration mode to ensure
-  *         to be in functional mode, in order to have OPAMP parameters
-  *         (inputs selection, ...) set with the corresponding OPAMP mode
-  *         to be effective.
-  * @rmtoll CSR      S3SELx        LL_OPAMP_SetFunctionalMode
-  * @param  OPAMPx OPAMP instance
-  * @param  FunctionalMode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_MODE_STANDALONE
-  *         @arg @ref LL_OPAMP_MODE_FOLLOWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
-{
-  /* Note: Bits OPAMP_CSR_OPAxCAL_y reset to ensure to be in functional mode */
-  MODIFY_REG(OPAMP->CSR,
-             (OPAMP_CSR_S3SEL1 | OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1CAL_L) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx),
-             FunctionalMode << __OPAMP_INSTANCE_BITOFFSET(OPAMPx));
-}
-
-/**
-  * @brief  Get OPAMP functional mode from setting of internal connections.
-  *         OPAMP operation in standalone, follower, ...
-  * @rmtoll CSR      S3SELx        LL_OPAMP_GetFunctionalMode
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_MODE_STANDALONE
-  *         @arg @ref LL_OPAMP_MODE_FOLLOWER
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
-{
-  return (uint32_t)(READ_BIT(OPAMP->CSR, OPAMP_CSR_S3SEL1 << __OPAMP_INSTANCE_BITOFFSET(OPAMPx))
-                    >> __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
-  * @{
-  */
-
-/**
-  * @brief  Set OPAMP non-inverting input connection.
-  * @rmtoll CSR      S5SELx         LL_OPAMP_SetInputNonInverting\n
-  * @rmtoll CSR      S6SELx         LL_OPAMP_SetInputNonInverting\n
-  * @rmtoll CSR      S7SEL2         LL_OPAMP_SetInputNonInverting
-  * @param  OPAMPx OPAMP instance
-  * @param  InputNonInverting This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
-  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
-  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
-  *         
-  *         (1) Parameter specific to OPAMP instances: OPAMP1, OPAMP2.\n
-  *         (2) Parameter specific to OPAMP instances: OPAMP2, OPAMP3.
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
-{
-  MODIFY_REG(OPAMP->CSR,
-             ((OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx)),
-             (InputNonInverting << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | ((InputNonInverting & OPAMP_CSR_S7SEL2) * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-            );
-}
-
-/**
-  * @brief  Get OPAMP non-inverting input connection.
-  * @rmtoll CSR      S5SELx         LL_OPAMP_GetInputNonInverting\n
-  * @rmtoll CSR      S6SELx         LL_OPAMP_GetInputNonInverting\n
-  * @rmtoll CSR      S7SEL2         LL_OPAMP_GetInputNonInverting
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
-  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
-  *         @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
-  *         
-  *         (1) Parameter specific to OPAMP instances: OPAMP1, OPAMP2.\n
-  *         (2) Parameter specific to OPAMP instances: OPAMP2, OPAMP3.
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
-{
-  uint32_t input_non_inverting_opamp_x = READ_BIT(OPAMP->CSR,
-                                                  (OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-                                                  | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-                                                 );
-  
-  return (((input_non_inverting_opamp_x & ~OPAMP_CSR_S7SEL2) >> __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | (input_non_inverting_opamp_x & OPAMP_CSR_S7SEL2));
-}
-
-/**
-  * @brief  Set OPAMP inverting input connection.
-  * @note   OPAMP inverting input is used with OPAMP in mode standalone.
-  *         Otherwise (OPAMP in mode follower), OPAMP inverting input
-  *         is not used (not connected to GPIO pin).
-  * @rmtoll CSR      S4SELx         LL_OPAMP_SetInputInverting\n
-  * @rmtoll CSR      ANAWSELx        LL_OPAMP_SetInputInverting
-  * @param  OPAMPx OPAMP instance
-  * @param  InputInverting This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1        (1)
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
-  *         
-  *         (1) Alternative IO pin, not low leakage, availability depends on STM32L1 serie devices packages.
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
-{
-  MODIFY_REG(OPAMP->CSR,
-             ((OPAMP_CSR_S4SEL1) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | ((OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx)),
-             ((InputInverting & OPAMP_CSR_S4SEL1) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)) | ((InputInverting & OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx))
-            );
-}
-
-/**
-  * @brief  Get OPAMP inverting input connection.
-  * @rmtoll CSR      S4SELx         LL_OPAMP_SetInputInverting\n
-  * @rmtoll CSR      ANAWSELx        LL_OPAMP_SetInputInverting
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1        (1)
-  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
-  *         
-  *         (1) Alternative IO pin, not low leakage, availability depends on STM32L1 serie devices packages.
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
-{
-  uint32_t input_inverting_opamp_x = READ_BIT(OPAMP->CSR,
-                                                (OPAMP_CSR_S4SEL1) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-                                              | (OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx)
-                                             );
-  
-#if defined(OPAMP3)
-  return (  ((input_inverting_opamp_x & (OPAMP_CSR_S4SEL1 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S4SEL3)) >> __OPAMP_INSTANCE_BITOFFSET(OPAMPx))
-          | ((input_inverting_opamp_x & (OPAMP_CSR_ANAWSEL1 | OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_ANAWSEL3)) >> __OPAMP_INSTANCE_DECIMAL(OPAMPx)));
-#else
-  return (  ((input_inverting_opamp_x & (OPAMP_CSR_S4SEL1 | OPAMP_CSR_S4SEL2)) >> __OPAMP_INSTANCE_BITOFFSET(OPAMPx))
-          | ((input_inverting_opamp_x & (OPAMP_CSR_ANAWSEL1 | OPAMP_CSR_ANAWSEL2)) >> __OPAMP_INSTANCE_DECIMAL(OPAMPx)));
-#endif
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
-  * @{
-  */
-
-/**
-  * @brief  Set OPAMP trimming mode.
-  * @note   The OPAMP trimming mode applies to several OPAMP instances
-  *         (if several OPAMP instances available on the selected device).
-  * @rmtoll OTR      OT_USER        LL_OPAMP_SetCommonTrimmingMode
-  * @param  OPAMPxy_COMMON OPAMP common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
-  * @param  TrimmingMode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
-  *         @arg @ref LL_OPAMP_TRIMMING_USER
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetCommonTrimmingMode(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t TrimmingMode)
-{
-  /* Note: On STM32L1 serie, OPAMP trimming mode bit "OPAMP_OTR_OT_USER" is   */
-  /*       write only, cannot be read.                                        */
-  MODIFY_REG(OPAMPxy_COMMON->OTR,
-             OPAMP_OTR_OT_USER,
-             TrimmingMode);
-}
-
-/**
-  * @brief  Get OPAMP trimming mode.
-  * @note   The OPAMP trimming mode applies to several OPAMP instances
-  *         (if several OPAMP instances available on the selected device).
-  * @rmtoll OTR      OT_USER        LL_OPAMP_GetCommonTrimmingMode
-  * @param  OPAMPxy_COMMON OPAMP common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_OPAMP_COMMON_INSTANCE() )
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY
-  *         @arg @ref LL_OPAMP_TRIMMING_USER
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetCommonTrimmingMode(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
-{
-  return (uint32_t)(READ_BIT(OPAMPxy_COMMON->OTR, OPAMP_OTR_OT_USER));
-}
-
-/**
-  * @brief  Set OPAMP offset to calibrate the selected transistors
-  *         differential pair NMOS or PMOS.
-  * @note   Preliminarily, OPAMP must be set in mode calibration
-  *         using function @ref LL_OPAMP_SetMode().
-  * @rmtoll CSR      OPA1CAL_H      LL_OPAMP_SetCalibrationSelection\n
-  *         CSR      OPA1CAL_L      LL_OPAMP_SetCalibrationSelection
-  * @param  OPAMPx OPAMP instance
-  * @param  TransistorsDiffPair This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_NONE
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
-{
-  /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */
-  /* containing other bits reserved for other purpose.                        */
-  MODIFY_REG(OPAMP->CSR,
-             (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1CAL_L) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx),
-             ((TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK) >> OPAMP_TRIMMING_SELECT_SW_OFFSET) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-            );
-}
-
-/**
-  * @brief  Get OPAMP offset to calibrate the selected transistors
-  *         differential pair NMOS or PMOS.
-  * @note   Preliminarily, OPAMP must be set in mode calibration
-  *         using function @ref LL_OPAMP_SetMode().
-  * @rmtoll CSR      OPA1CAL_H      LL_OPAMP_SetCalibrationSelection\n
-  *         CSR      OPA1CAL_L      LL_OPAMP_SetCalibrationSelection
-  * @param  OPAMPx OPAMP instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_NONE
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
-{
-  uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMP->CSR,
-                                                      (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1CAL_L) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-                                                     )
-                                             >> __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-                                            );
-  
-  return ((CalibrationSelection << OPAMP_TRIMMING_SELECT_SW_OFFSET) |
-          ((OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW) << (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos * ((CalibrationSelection & OPAMP_CSR_OPA1CAL_H) != 0U))));
-}
-
-/**
-  * @brief  Get OPAMP calibration result of toggling output.
-  * @note   This functions returns:
-  *         0 if OPAMP calibration output is reset
-  *         1 if OPAMP calibration output is set
-  * @rmtoll CSR      OPAxCALOUT     LL_OPAMP_IsCalibrationOutputSet
-  * @param  OPAMPx OPAMP instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
-{
-  return (READ_BIT(OPAMP->CSR, (OPAMP_CSR_OPA1CALOUT << __OPAMP_INSTANCE_DECIMAL(OPAMPx)))
-          == (OPAMP_CSR_OPA1CALOUT << __OPAMP_INSTANCE_DECIMAL(OPAMPx)));
-}
-
-/**
-  * @brief  Set OPAMP trimming factor for the selected transistors
-  *         differential pair NMOS or PMOS, corresponding to the selected
-  *         power mode.
-  * @note   On STM32L1 serie, OPAMP trimming mode must be re-configured 
-  *         at each update of trimming values in power mode normal.
-  *         Refer to function @ref LL_OPAMP_SetCommonTrimmingMode().
-  * @rmtoll OTR      AOx_OPT_OFFSET_TRIM_HIGH    LL_OPAMP_SetTrimmingValue\n
-  *         OTR      AOx_OPT_OFFSET_TRIM_LOW     LL_OPAMP_SetTrimmingValue\n
-  *         LPOTR    AOx_OPT_OFFSET_TRIM_LP_HIGH LL_OPAMP_SetTrimmingValue\n
-  *         LPOTR    AOx_OPT_OFFSET_TRIM_LP_LOW  LL_OPAMP_SetTrimmingValue
-  * @param  OPAMPx OPAMP instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
-  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
-  * @param  TransistorsDiffPair This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
-  * @param  TrimmingValue 0x00...0x1F
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
-{
-  uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMP->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
-  
-  /* Set bits with position in register depending on parameter                */
-  /* "TransistorsDiffPair".                                                   */
-  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
-  /* containing other bits reserved for other purpose.                        */
-  MODIFY_REG(*preg,
-             (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) << (OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos * __OPAMP_INSTANCE_DECIMAL(OPAMPx)),
-             TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) + (OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos * __OPAMP_INSTANCE_DECIMAL(OPAMPx))));
-}
-
-/**
-  * @brief  Get OPAMP trimming factor for the selected transistors
-  *         differential pair NMOS or PMOS, corresponding to the selected
-  *         power mode.
-  * @rmtoll OTR      AOx_OPT_OFFSET_TRIM_HIGH    LL_OPAMP_GetTrimmingValue\n
-  *         OTR      AOx_OPT_OFFSET_TRIM_LOW     LL_OPAMP_GetTrimmingValue\n
-  *         LPOTR    AOx_OPT_OFFSET_TRIM_LP_HIGH LL_OPAMP_GetTrimmingValue\n
-  *         LPOTR    AOx_OPT_OFFSET_TRIM_LP_LOW  LL_OPAMP_GetTrimmingValue
-  * @param  OPAMPx OPAMP instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL
-  *         @arg @ref LL_OPAMP_POWERMODE_LOWPOWER
-  * @param  TransistorsDiffPair This parameter can be one of the following values:
-  *         @arg @ref LL_OPAMP_TRIMMING_NMOS
-  *         @arg @ref LL_OPAMP_TRIMMING_PMOS
-  * @retval 0x0...0x1F
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
-{
-  uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMP->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
-  
-  /* Retrieve bits with position in register depending on parameter           */
-  /* "TransistorsDiffPair".                                                   */
-  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */
-  /* containing other bits reserved for other purpose.                        */
-  return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) << (OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos * __OPAMP_INSTANCE_DECIMAL(OPAMPx)))
-                    >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) + (OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos * __OPAMP_INSTANCE_DECIMAL(OPAMPx)))
-                   );
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
-  * @{
-  */
-/**
-  * @brief  Enable OPAMP instance.
-  * @note   After enable from off state, OPAMP requires a delay
-  *         to fullfill wake up time specification.
-  *         Refer to device datasheet, parameter "tWAKEUP".
-  * @rmtoll CSR      OPAxPD         LL_OPAMP_Enable
-  * @param  OPAMPx OPAMP instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
-{
-  CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_OPA1PD << __OPAMP_INSTANCE_BITOFFSET(OPAMPx));
-}
-
-/**
-  * @brief  Disable OPAMP instance.
-  * @rmtoll CSR      OPAxPD         LL_OPAMP_Disable
-  * @param  OPAMPx OPAMP instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
-{
-  SET_BIT(OPAMP->CSR, OPAMP_CSR_OPA1PD << __OPAMP_INSTANCE_BITOFFSET(OPAMPx));
-}
-
-/**
-  * @brief  Get OPAMP instance enable state
-  *         (0: OPAMP is disabled, 1: OPAMP is enabled)
-  * @rmtoll CSR      OPAxPD         LL_OPAMP_IsEnabled
-  * @param  OPAMPx OPAMP instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
-{
-  return (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPA1PD << __OPAMP_INSTANCE_BITOFFSET(OPAMPx))
-          != (OPAMP_CSR_OPA1PD << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
-ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
-void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* OPAMP1 || OPAMP2 || OPAMP3 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h
deleted file mode 100644
index 18b64d1d55e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h
+++ /dev/null
@@ -1,721 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_PWR_H
-#define __STM32L1xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
-  * @{
-  */
-#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
-#if defined(PWR_PVD_SUPPORT)
-#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
-#endif /* PWR_PVD_SUPPORT */
-#if defined(PWR_CSR_VREFINTRDYF)
-#define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
-#endif /* PWR_CSR_VREFINTRDYF */
-#define LL_PWR_CSR_VOS                     PWR_CSR_VOSF           /*!< Voltage scaling select flag */
-#define LL_PWR_CSR_REGLPF                  PWR_CSR_REGLPF         /*!< Regulator low power flag */
-#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
-#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
-  * @{
-  */
-#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0)                   /*!< 1.8V (range 1) */
-#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)                   /*!< 1.5V (range 2) */
-#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0 | PWR_CR_VOS_1)    /*!< 1.2V (range 3) */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
-  * @{
-  */
-#define LL_PWR_MODE_STOP                      0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES  Regulator Mode In Low Power Modes
-  * @{
-  */
-#define LL_PWR_REGU_LPMODES_MAIN           0x00000000U        /*!< Voltage Regulator in main mode during deepsleep/sleep/low-power run mode */
-#define LL_PWR_REGU_LPMODES_LOW_POWER      (PWR_CR_LPSDSR)    /*!< Voltage Regulator in low-power mode during deepsleep/sleep/low-power run mode */
-/**
-  * @}
-  */
-#if defined(PWR_CR_LPDS)
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
-  * @}
-  */
-#endif /* PWR_CR_LPDS */
-
-#if defined(PWR_PVD_SUPPORT)
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
-  * @{
-  */
-#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 1.9 V */
-#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.1 V */
-#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.9 V */
-#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 3.1 V */
-#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< External input analog voltage   (Compare internally to VREFINT) */
-/**
-  * @}
-  */
-#endif /* PWR_PVD_SUPPORT */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-  * @{
-  */
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
-#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in PWR register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in PWR register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Switch the Regulator from main mode to low-power mode
-  * @rmtoll CR    LPRUN       LL_PWR_EnableLowPowerRunMode
-  * @note   Remind to set the Regulator to low power before enabling
-  *         LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPRUN);
-}
-
-/**
-  * @brief  Switch the Regulator from low-power mode to main mode
-  * @rmtoll CR    LPRUN       LL_PWR_DisableLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
-}
-
-/**
-  * @brief  Check if the Regulator is in low-power mode
-  * @rmtoll CR    LPRUN       LL_PWR_IsEnabledLowPowerRunMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
-{
-  return ((READ_BIT(PWR->CR, PWR_CR_LPRUN) == PWR_CR_LPRUN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set voltage Regulator to low-power and switch from
-  *         run main mode to run low-power mode.
-  * @rmtoll CR    LPSDSR       LL_PWR_EnterLowPowerRunMode\n
-  *         CR    LPRUN        LL_PWR_EnterLowPowerRunMode
-  * @note   This "high level" function is introduced to provide functional
-  *         compatibility with other families. Notice that the two registers
-  *         have to be written sequentially, so this function is not atomic.
-  *         To assure atomicity you can call separately the following functions:
-  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
-  *         - @ref LL_PWR_EnableLowPowerRunMode();
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
-  SET_BIT(PWR->CR, PWR_CR_LPRUN);  /* => LL_PWR_EnableLowPowerRunMode() */
-}
-
-/**
-  * @brief  Set voltage Regulator to main and switch from
-  *         run main mode to low-power mode.
-  * @rmtoll CR    LPSDSR       LL_PWR_ExitLowPowerRunMode\n
-  *         CR    LPRUN        LL_PWR_ExitLowPowerRunMode
-  * @note   This "high level" function is introduced to provide functional
-  *         compatibility with other families. Notice that the two registers
-  *         have to be written sequentially, so this function is not atomic.
-  *         To assure atomicity you can call separately the following functions:
-  *         - @ref LL_PWR_DisableLowPowerRunMode();
-  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);   /* => LL_PWR_DisableLowPowerRunMode() */
-  CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);  /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
-}
-/**
-  * @brief  Set the main internal Regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
-}
-
-/**
-  * @brief  Get the main internal Regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
-}
-
-/**
-  * @brief  Enable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Disable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Check if the backup domain is enabled
-  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
-  return ((READ_BIT(PWR->CR, PWR_CR_DBP) == PWR_CR_DBP) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set voltage Regulator mode during low power modes
-  * @rmtoll CR    LPSDSR       LL_PWR_SetRegulModeLP
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
-  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
-}
-
-/**
-  * @brief  Get voltage Regulator mode during low power modes
-  * @rmtoll CR    LPSDSR       LL_PWR_GetRegulModeLP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
-  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
-}
-
-#if defined(PWR_CR_LPDS)
-/**
-  * @brief  Set voltage Regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
-  * @brief  Get voltage Regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-#endif /* PWR_CR_LPDS */
-
-/**
-  * @brief  Set Power Down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  * @note   Set the Regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)
-  *         before setting MODE_STOP. If the Regulator remains in "main mode",
-  *         it consumes more power without providing any additional feature.
-  *         In MODE_STANDBY the Regulator is automatically off.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
-}
-
-/**
-  * @brief  Get Power Down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
-  * @param  PVDLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
-  * @brief  Get the voltage threshold detection
-  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
-  * @brief  Enable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Disable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Check if Power Voltage Detector is enabled
-  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
-  return ((READ_BIT(PWR->CR, PWR_CR_PVDE) == PWR_CR_PVDE) ? 1UL : 0UL);
-}
-#endif /* PWR_PVD_SUPPORT */
-
-/**
-  * @brief  Enable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Disable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Check if the WakeUp PINx functionality is enabled
-  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
-  return ((READ_BIT(PWR->CSR, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
-  * @rmtoll CR    ULP       LL_PWR_EnableUltraLowPower
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
-  * @rmtoll CR    ULP       LL_PWR_DisableUltraLowPower
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_ULP);
-}
-
-/**
-  * @brief  Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
-  * @rmtoll CR    ULP       LL_PWR_IsEnabledUltraLowPower
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
-{
-  return ((READ_BIT(PWR->CR, PWR_CR_ULP) == PWR_CR_ULP) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
-  * @rmtoll CR    FWU       LL_PWR_EnableFastWakeUp
-  * @note   Works in conjunction with ultra low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
-  * @rmtoll CR    FWU       LL_PWR_DisableFastWakeUp
-  * @note   Works in conjunction with ultra low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_FWU);
-}
-
-/**
-  * @brief  Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
-  * @rmtoll CR    FWU       LL_PWR_IsEnabledFastWakeUp
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
-{
-  return ((READ_BIT(PWR->CR, PWR_CR_FWU) == PWR_CR_FWU) ? 1UL : 0UL);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Wake-up Flag
-  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_WUF) == PWR_CSR_WUF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Standby Flag
-  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_SBF) == PWR_CSR_SBF) ? 1UL : 0UL);
-}
-
-#if defined(PWR_PVD_SUPPORT)
-/**
-  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
-  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_PVDO) == PWR_CSR_PVDO) ? 1UL : 0UL);
-}
-#endif /* PWR_PVD_SUPPORT */
-
-#if defined(PWR_CSR_VREFINTRDYF)
-/**
-  * @brief  Get Internal Reference VrefInt Flag
-  * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == PWR_CSR_VREFINTRDYF) ? 1UL : 0UL);
-}
-#endif /* PWR_CSR_VREFINTRDYF */
-/**
-  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
-  * @rmtoll CSR   VOSF       LL_PWR_IsActiveFlag_VOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_VOSF) == PWR_CSR_VOSF) ? 1UL : 0UL);
-}
-/**
-  * @brief Indicate whether the Regulator is ready in main mode or is in low-power mode
-  * @rmtoll CSR   REGLPF       LL_PWR_IsActiveFlag_REGLPF
-  * @note Take care, return value "0" means the Regulator is ready.  Return value "1" means the output voltage range is still changing.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
-{
-  return ((READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == PWR_CSR_REGLPF) ? 1UL : 0UL);
-}
-/**
-  * @brief  Clear Standby Flag
-  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
-  * @brief  Clear Wake-up Flags
-  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_PWR_DeInit(void);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup PWR_LL_EF_Legacy_Functions PWR legacy functions name
-  * @{
-  */
-/* Old functions name kept for legacy purpose, to be replaced by the          */
-/* current functions name.                                                    */
-#define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(PWR) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h
deleted file mode 100644
index b04bbd9f8aa..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h
+++ /dev/null
@@ -1,1799 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_RCC_H
-#define __STM32L1xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
-  * @{
-  */
-
-/**
-  * @brief  RCC Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
-  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
-  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
-  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
-  * @brief    Defines used to adapt values of different oscillators
-  * @note     These values could be modified in the user environment according to
-  *           HW set-up.
-  * @{
-  */
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE    37000U    /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CIR_MSIRDYC                RCC_CIR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
-#if defined(RCC_LSECSS_SUPPORT)
-#define LL_RCC_CIR_LSECSSC                RCC_CIR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
-#endif /* RCC_LSECSS_SUPPORT */
-#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIR_MSIRDYF                RCC_CIR_MSIRDYF     /*!< MSI Ready Interrupt flag */
-#if defined(RCC_LSECSS_SUPPORT)
-#define LL_RCC_CIR_LSECSSF                RCC_CIR_LSECSSF    /*!< LSE Clock Security System Interrupt flag */
-#endif /* RCC_LSECSS_SUPPORT */
-#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF       /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIR_MSIRDYIE               RCC_CIR_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
-#if defined(RCC_LSECSS_SUPPORT)
-#define LL_RCC_CIR_LSECSSIE               RCC_CIR_LSECSSIE      /*!< LSE CSS Interrupt Enable */
-#endif /* RCC_LSECSS_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
-  * @{
-  */
-#define LL_RCC_RTC_HSE_DIV_2               0x00000000U          /*!< HSE is divided by 2 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
-#define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
-  * @{
-  */
-#define LL_RCC_MSIRANGE_0                  RCC_ICSCR_MSIRANGE_0  /*!< MSI = 65.536 KHz */
-#define LL_RCC_MSIRANGE_1                  RCC_ICSCR_MSIRANGE_1  /*!< MSI = 131.072 KHz*/
-#define LL_RCC_MSIRANGE_2                  RCC_ICSCR_MSIRANGE_2  /*!< MSI = 262.144 KHz */
-#define LL_RCC_MSIRANGE_3                  RCC_ICSCR_MSIRANGE_3  /*!< MSI = 524.288 KHz */
-#define LL_RCC_MSIRANGE_4                  RCC_ICSCR_MSIRANGE_4  /*!< MSI = 1.048 MHz */
-#define LL_RCC_MSIRANGE_5                  RCC_ICSCR_MSIRANGE_5  /*!< MSI = 2.097 MHz */
-#define LL_RCC_MSIRANGE_6                  RCC_ICSCR_MSIRANGE_6  /*!< MSI = 4.194 MHz */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
-  * @{
-  */
-#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
-  * @{
-  */
-#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
-  * @{
-  */
-#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
-  * @{
-  */
-#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_MSI          /*!< MSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_PLLCLK           RCC_CFGR_MCOSEL_PLL          /*!< PLLCLK selection as MCO source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
-  * @{
-  */
-#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1  /*!< MCO Clock divided by 1  */
-#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2  /*!< MCO Clock divided by 2  */
-#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4  /*!< MCO Clock divided by 4  */
-#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8  /*!< MCO Clock divided by 8  */
-#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
-  * @{
-  */
-#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
-  * @{
-  */
-#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler
-                                                                             (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
-  * @{
-  */
-#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock * 3  */
-#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock * 4  */
-#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock * 6  */
-#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock * 8  */
-#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
-#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
-#define LL_RCC_PLL_MUL_24                  RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
-#define LL_RCC_PLL_MUL_32                  RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
-#define LL_RCC_PLL_MUL_48                  RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
-  * @{
-  */
-#define LL_RCC_PLL_DIV_2                   RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
-#define LL_RCC_PLL_DIV_3                   RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
-#define LL_RCC_PLL_DIV_4                   RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
-  * @{
-  */
-#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI                           /*!< HSI clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE                           /*!< HSE clock selected as PLL entry clock source */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RCC register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RCC register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
-  *                                      @ref LL_RCC_PLL_GetMultiplicator (),
-  *                                      @ref LL_RCC_PLL_GetDivider ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
-  * @param  __PLLMUL__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  * @param  __PLLDIV__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__,  __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1U))
-
-/**
-  * @brief  Helper macro to calculate the HCLK frequency
-  * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
-  *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
-  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
-  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval HCLK clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
-  * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
-  *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
-  * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
-  *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
-
-/**
-  * @brief  Helper macro to calculate the MSI frequency (in Hz)
-  * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
-  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
-  * @param  __MSIRANGE__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  * @retval MSI clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1U))))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_LL_EF_HSE HSE
-  * @{
-  */
-
-/**
-  * @brief  Enable the Clock Security System.
-  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Disable the Clock Security System.
-  * @note Cannot be disabled in HSE is ready (only by hardware)
-  * @rmtoll CR           CSSON         LL_RCC_HSE_DisableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Enable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Disable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Enable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Disable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Check if HSE oscillator Ready
-  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the RTC prescaler (divider)
-  * @rmtoll CR           RTCPRE        LL_RCC_SetRTC_HSEPrescaler
-  * @param  Div This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
-{
-  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
-}
-
-/**
-  * @brief  Get the RTC divider (prescaler)
-  * @rmtoll CR           RTCPRE        LL_RCC_GetRTC_HSEPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI HSI
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Disable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Check if HSI clock is ready
-  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get HSI Calibration value
-  * @note When HSITRIM is written, HSICAL is updated with the sum of
-  *       HSITRIM and the factory trim value
-  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
-}
-
-/**
-  * @brief  Set HSI Calibration trimming
-  * @note user-programmable trimming value that is added to the HSICAL
-  * @note Default value is 16, which, when added to the HSICAL value,
-  *       should trim the HSI to 16 MHz +/- 1 %
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
-  * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @brief  Get HSI Calibration trimming
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
-  * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSE LSE
-  * @{
-  */
-
-/**
-  * @brief  Enable  Low Speed External (LSE) crystal.
-  * @rmtoll CSR         LSEON         LL_RCC_LSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSEON);
-}
-
-/**
-  * @brief  Disable  Low Speed External (LSE) crystal.
-  * @rmtoll CSR         LSEON         LL_RCC_LSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
-}
-
-/**
-  * @brief  Enable external clock source (LSE bypass).
-  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
-}
-
-/**
-  * @brief  Disable external clock source (LSE bypass).
-  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Enable Clock security system on LSE.
-  * @rmtoll CSR         LSECSSON      LL_RCC_LSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
-}
-
-/**
-  * @brief  Disable Clock security system on LSE.
-  * @note   Clock security system can be disabled only after a LSE
-  *         failure detection. In that case it MUST be disabled by software.
-  * @rmtoll CSR          LSECSSON      LL_RCC_LSE_DisableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
-}
-
-#endif /* RCC_LSECSS_SUPPORT */
-/**
-  * @brief  Check if LSE oscillator Ready
-  * @rmtoll CSR         LSERDY        LL_RCC_LSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Check if CSS on LSE failure Detection
-  * @rmtoll CSR         LSECSSD       LL_RCC_LSE_IsCSSDetected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
-}
-
-#endif /* RCC_LSECSS_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSI LSI
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Disable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Check if LSI is Ready
-  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MSI MSI
-  * @{
-  */
-
-/**
-  * @brief  Enable MSI oscillator
-  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-}
-
-/**
-  * @brief  Disable MSI oscillator
-  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
-}
-
-/**
-  * @brief  Check if MSI oscillator Ready
-  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
-  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_SetRange
-  * @param  Range This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
-}
-
-/**
-  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
-  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_GetRange
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_MSIRANGE_0
-  *         @arg @ref LL_RCC_MSIRANGE_1
-  *         @arg @ref LL_RCC_MSIRANGE_2
-  *         @arg @ref LL_RCC_MSIRANGE_3
-  *         @arg @ref LL_RCC_MSIRANGE_4
-  *         @arg @ref LL_RCC_MSIRANGE_5
-  *         @arg @ref LL_RCC_MSIRANGE_6
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
-}
-
-/**
-  * @brief  Get MSI Calibration value
-  * @note When MSITRIM is written, MSICAL is updated with the sum of
-  *       MSITRIM and the factory trim value
-  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
-}
-
-/**
-  * @brief  Set MSI Calibration trimming
-  * @note user-programmable trimming value that is added to the MSICAL
-  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
-  * @param  Value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
-}
-
-/**
-  * @brief  Get MSI Calibration trimming
-  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_System System
-  * @{
-  */
-
-/**
-  * @brief  Configure the system clock source
-  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
-  * @brief  Get the system clock source
-  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Set AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
-  * @brief  Set APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
-  * @brief  Set APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
-  * @brief  Get AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
-  * @brief  Get APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
-  * @brief  Get APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MCO MCO
-  * @{
-  */
-
-/**
-  * @brief  Configure MCOx
-  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
-  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
-  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1_DIV_1
-  *         @arg @ref LL_RCC_MCO1_DIV_2
-  *         @arg @ref LL_RCC_MCO1_DIV_4
-  *         @arg @ref LL_RCC_MCO1_DIV_8
-  *         @arg @ref LL_RCC_MCO1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
-}
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup RCC_LL_EF_RTC RTC
-  * @{
-  */
-
-/**
-  * @brief  Set RTC Clock Source
-  * @note Once the RTC clock source has been selected, it cannot be changed any more unless
-  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
-  *       set). The RTCRST bit can be used to reset them.
-  * @rmtoll CSR         RTCSEL        LL_RCC_SetRTCClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
-}
-
-/**
-  * @brief  Get RTC Clock Source
-  * @rmtoll CSR         RTCSEL        LL_RCC_GetRTCClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
-}
-
-/**
-  * @brief  Enable RTC
-  * @rmtoll CSR         RTCEN         LL_RCC_EnableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
-}
-
-/**
-  * @brief  Disable RTC
-  * @rmtoll CSR         RTCEN         LL_RCC_DisableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
-}
-
-/**
-  * @brief  Check if RTC has been enabled or not
-  * @rmtoll CSR         RTCEN         LL_RCC_IsEnabledRTC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Force the Backup domain reset
-  * @rmtoll CSR         RTCRST         LL_RCC_ForceBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
-}
-
-/**
-  * @brief  Release the Backup domain reset
-  * @rmtoll CSR         RTCRST         LL_RCC_ReleaseBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_PLL PLL
-  * @{
-  */
-
-/**
-  * @brief  Enable PLL
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Disable PLL
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Check if PLL Ready
-  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure PLL used for SYSCLK Domain
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         CFGR         PLLDIV        LL_RCC_PLL_ConfigDomain_SYS
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLMul This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  * @param  PLLDiv This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
-}
-
-/**
-  * @brief  Configure PLL clock source
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_SetMainSource
-  * @param  PLLSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
-}
-
-/**
-  * @brief  Get PLL multiplication Factor
-  * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_MUL_3
-  *         @arg @ref LL_RCC_PLL_MUL_4
-  *         @arg @ref LL_RCC_PLL_MUL_6
-  *         @arg @ref LL_RCC_PLL_MUL_8
-  *         @arg @ref LL_RCC_PLL_MUL_12
-  *         @arg @ref LL_RCC_PLL_MUL_16
-  *         @arg @ref LL_RCC_PLL_MUL_24
-  *         @arg @ref LL_RCC_PLL_MUL_32
-  *         @arg @ref LL_RCC_PLL_MUL_48
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
-}
-
-/**
-  * @brief  Get Division factor for the main PLL and other PLL
-  * @rmtoll CFGR         PLLDIV        LL_RCC_PLL_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLL_DIV_2
-  *         @arg @ref LL_RCC_PLL_DIV_3
-  *         @arg @ref LL_RCC_PLL_DIV_4
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear LSI ready interrupt flag
-  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
-  * @brief  Clear LSE ready interrupt flag
-  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
-  * @brief  Clear MSI ready interrupt flag
-  * @rmtoll CIR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
-}
-
-/**
-  * @brief  Clear HSI ready interrupt flag
-  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
-  * @brief  Clear HSE ready interrupt flag
-  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
-  * @brief  Clear PLL ready interrupt flag
-  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-/**
-  * @brief  Clear Clock security system interrupt flag
-  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Clear LSE Clock security system interrupt flag
-  * @rmtoll CIR         LSECSSC       LL_RCC_ClearFlag_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
-}
-
-#endif /* RCC_LSECSS_SUPPORT */
-/**
-  * @brief  Check if LSI ready interrupt occurred or not
-  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == RCC_CIR_LSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LSE ready interrupt occurred or not
-  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == RCC_CIR_LSERDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if MSI ready interrupt occurred or not
-  * @rmtoll CIR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == RCC_CIR_MSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSI ready interrupt occurred or not
-  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == RCC_CIR_HSIRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSE ready interrupt occurred or not
-  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == RCC_CIR_HSERDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if PLL ready interrupt occurred or not
-  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == RCC_CIR_PLLRDYF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Clock security system interrupt occurred or not
-  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_CSSF) == RCC_CIR_CSSF) ? 1UL : 0UL);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Check if LSE Clock security system interrupt occurred or not
-  * @rmtoll CIR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == RCC_CIR_LSECSSF) ? 1UL : 0UL);
-}
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
-  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Low Power reset is set or not.
-  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag is set or not.
-  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Pin reset is set or not.
-  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag POR/PDR reset is set or not.
-  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Window Watchdog reset is set or not.
-  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI ready interrupt
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
-  * @brief  Enable LSE ready interrupt
-  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
-  * @brief  Enable MSI ready interrupt
-  * @rmtoll CIR         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSI ready interrupt
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSE ready interrupt
-  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
-  * @brief  Enable PLL ready interrupt
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Enable LSE clock security system interrupt
-  * @rmtoll CIR         LSECSSIE      LL_RCC_EnableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
-}
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @brief  Disable LSI ready interrupt
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
-  * @brief  Disable LSE ready interrupt
-  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
-  * @brief  Disable MSI ready interrupt
-  * @rmtoll CIR         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSI ready interrupt
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSE ready interrupt
-  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
-  * @brief  Disable PLL ready interrupt
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Disable LSE clock security system interrupt
-  * @rmtoll CIR         LSECSSIE      LL_RCC_DisableIT_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
-}
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == RCC_CIR_LSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == RCC_CIR_LSERDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == RCC_CIR_MSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == RCC_CIR_HSIRDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == RCC_CIR_HSERDYIE) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == RCC_CIR_PLLRDYIE) ? 1UL : 0UL);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
-  * @rmtoll CIR         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == RCC_CIR_LSECSSIE) ? 1UL : 0UL);
-}
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_RCC_DeInit(void);
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
-  * @{
-  */
-void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RCC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rtc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rtc.h
deleted file mode 100644
index 2276b08949e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rtc.h
+++ /dev/null
@@ -1,3767 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_rtc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_RTC_H
-#define __STM32L1xx_LL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(RTC)
-
-/** @defgroup RTC_LL RTC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_LL_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define LL_RTC_INIT_MASK              0xFFFFFFFFU
-
-/* Write protection defines */
-#define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
-#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
-#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
-
-/* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY            24U
-#define RTC_OFFSET_DAY                16U
-#define RTC_OFFSET_MONTH              8U
-#define RTC_OFFSET_HOUR               16U
-#define RTC_OFFSET_MINUTE             8U
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_Private_Macros RTC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  RTC Init structures definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
-                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetHourFormat(). */
-
-  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
-                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetAsynchPrescaler(). */
-
-  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
-                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
-
-                              This feature can be modified afterwards using unitary function
-                              @ref LL_RTC_SetSynchPrescaler(). */
-} LL_RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
-                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
-
-  uint8_t Hours;       /*!< Specifies the RTC Time Hours.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
-
-  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
-
-  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
-                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
-} LL_RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month.
-                         This parameter can be a value of @ref RTC_LL_EC_MONTH
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
-
-  uint8_t Day;      /*!< Specifies the RTC Date Day.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99
-
-                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
-} LL_RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
-                                      or @ref LL_RTC_ALMB_SetMask() for ALARM B
-                                 */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
-                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
-                                      for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
-                                 */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
-                                      If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
-                                      for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
-
-                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
-
-                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
-                                      for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
-                                 */
-} LL_RTC_AlarmTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EC_FORMAT FORMAT
-  * @{
-  */
-#define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
-  * @{
-  */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
-  * @{
-  */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RTC_ReadReg function
-  * @{
-  */
-#if defined(RTC_SMOOTHCALIB_SUPPORT)
-#define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
-#endif /* RTC_SMOOTHCALIB_SUPPORT */
-#define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
-#define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
-#define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
-#define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
-#define LL_RTC_ISR_TSF                     RTC_ISR_TSF
-#define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
-#define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
-#define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
-#define LL_RTC_ISR_INITF                   RTC_ISR_INITF
-#define LL_RTC_ISR_RSF                     RTC_ISR_RSF
-#define LL_RTC_ISR_INITS                   RTC_ISR_INITS
-#define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
-#define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
-#define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
-#define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
-  * @{
-  */
-#define LL_RTC_CR_TSIE                     RTC_CR_TSIE
-#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
-#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
-#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
-#define LL_RTC_TAFCR_TAMPIE               RTC_TAFCR_TAMPIE
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
-  * @{
-  */
-#define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
-#define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
-#define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
-#define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
-#define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
-#define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
-#define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_MONTH  MONTH
-  * @{
-  */
-#define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
-#define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
-#define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
-#define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
-#define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
-#define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
-#define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
-#define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
-#define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
-#define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
-#define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
-#define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
-  * @{
-  */
-#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
-#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
-  * @{
-  */
-#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
-#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
-#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
-#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
-  * @{
-  */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
-#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
-  * @{
-  */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
-#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
-  * @{
-  */
-#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
-/**
-  * @}
-  */
-
-#if defined(RTC_SHIFTR_ADD1S)
-/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
-  * @{
-  */
-#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
-#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
-/**
-  * @}
-  */
-#endif /* RTC_SHIFTR_ADD1S */
-
-/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
-  * @{
-  */
-#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
-#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
-  * @{
-  */
-#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
-  * @{
-  */
-#define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
-#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
-  * @{
-  */
-#define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
-  * @{
-  */
-#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
-  * @{
-  */
-#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
-#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER  TAMPER
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_1                    RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_2                    RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_3                    RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
-  * @{
-  */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
-#define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAFCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAFCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAFCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
-  * @{
-  */
-#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
-#define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAFCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAFCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAFCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
-/**
-  * @}
-  */
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
-  * @{
-  */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAFCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAFCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAFCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAFCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
-/**
-  * @}
-  */
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
-  * @{
-  */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
-  * @{
-  */
-#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
-/**
-  * @}
-  */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EC_BKP  BACKUP
-  * @{
-  */
-#define LL_RTC_BKP_DR0                     0x00000000U
-#define LL_RTC_BKP_DR1                     0x00000001U
-#define LL_RTC_BKP_DR2                     0x00000002U
-#define LL_RTC_BKP_DR3                     0x00000003U
-#define LL_RTC_BKP_DR4                     0x00000004U
-#if RTC_BKP_NUMBER > 5
-#define LL_RTC_BKP_DR5                     0x00000005U
-#define LL_RTC_BKP_DR6                     0x00000006U
-#define LL_RTC_BKP_DR7                     0x00000007U
-#define LL_RTC_BKP_DR8                     0x00000008U
-#define LL_RTC_BKP_DR9                     0x00000009U
-#define LL_RTC_BKP_DR10                    0x0000000AU
-#define LL_RTC_BKP_DR11                    0x0000000BU
-#define LL_RTC_BKP_DR12                    0x0000000CU
-#define LL_RTC_BKP_DR13                    0x0000000DU
-#define LL_RTC_BKP_DR14                    0x0000000EU
-#define LL_RTC_BKP_DR15                    0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5 */
-
-#if RTC_BKP_NUMBER > 16
-#define LL_RTC_BKP_DR16                    0x00000010U
-#define LL_RTC_BKP_DR17                    0x00000011U
-#define LL_RTC_BKP_DR18                    0x00000012U
-#define LL_RTC_BKP_DR19                    0x00000013U
-#endif /* RTC_BKP_NUMBER > 16 */
-
-#if RTC_BKP_NUMBER > 20
-#define LL_RTC_BKP_DR20                    0x00000014U
-#define LL_RTC_BKP_DR21                    0x00000015U
-#define LL_RTC_BKP_DR22                    0x00000016U
-#define LL_RTC_BKP_DR23                    0x00000017U
-#define LL_RTC_BKP_DR24                    0x00000018U
-#define LL_RTC_BKP_DR25                    0x00000019U
-#define LL_RTC_BKP_DR26                    0x0000001AU
-#define LL_RTC_BKP_DR27                    0x0000001BU
-#define LL_RTC_BKP_DR28                    0x0000001CU
-#define LL_RTC_BKP_DR29                    0x0000001DU
-#define LL_RTC_BKP_DR30                    0x0000001EU
-#define LL_RTC_BKP_DR31                    0x0000001FU
-#endif /* RTC_BKP_NUMBER > 20 */
-/**
-  * @}
-  */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
-  * @{
-  */
-#define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
-#if defined(RTC_CR_COSEL)
-#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
-#endif
-#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 512 Hz */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_CALIB_SIGN Coarse digital calibration sign
-  * @{
-  */
-#define LL_RTC_CALIB_SIGN_POSITIVE         0x00000000U           /*!< Positive calibration: calendar update frequency is increased */
-#define LL_RTC_CALIB_SIGN_NEGATIVE         RTC_CALIBR_DCS        /*!< Negative calibration: calendar update frequency is decreased */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
-  * @{
-  */
-#define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
-#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
-  * @{
-  */
-#define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RTC register
-  * @param  __INSTANCE__ RTC Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
-
-/**
-  * @brief  Read a value in RTC register
-  * @param  __INSTANCE__ RTC Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Convert Convert helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
-  * @param  __VALUE__ Byte to be converted
-  * @retval Converted byte
-  */
-#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
-
-/**
-  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
-  * @param  __VALUE__ BCD value to be converted
-  * @retval Converted byte
-  */
-#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Date Date helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to retrieve weekday.
-  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Year in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Year in BCD format (0x00 . . . 0x99)
-  */
-#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Month in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve Day in BCD format
-  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
-  * @retval Day in BCD format (0x01 . . . 0x31)
-  */
-#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EM_Time Time helper Macros
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to retrieve hour in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
-  */
-#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve minute in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Minutes in BCD format (0x00. . .0x59)
-  */
-#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
-
-/**
-  * @brief  Helper macro to retrieve second in BCD format
-  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
-  * @retval Seconds in  format (0x00. . .0x59)
-  */
-#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Set Hours format (24 hour/day or AM/PM hour format)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           FMT           LL_RTC_SetHourFormat
-  * @param  RTCx RTC Instance
-  * @param  HourFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
-  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
-}
-
-/**
-  * @brief  Get Hours format (24 hour/day or AM/PM hour format)
-  * @rmtoll CR           FMT           LL_RTC_GetHourFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
-  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
-}
-
-/**
-  * @brief  Select the flag to be routed to RTC_ALARM output
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
-  * @param  RTCx RTC Instance
-  * @param  AlarmOutput This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
-  *         @arg @ref LL_RTC_ALARMOUT_ALMA
-  *         @arg @ref LL_RTC_ALARMOUT_ALMB
-  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
-}
-
-/**
-  * @brief  Get the flag to be routed to RTC_ALARM output
-  * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
-  *         @arg @ref LL_RTC_ALARMOUT_ALMA
-  *         @arg @ref LL_RTC_ALARMOUT_ALMB
-  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
-}
-
-/**
-  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
-  * @note   Used only when RTC_ALARM is mapped on PC13
-  * @rmtoll TAFCR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
-  * @param  RTCx RTC Instance
-  * @param  Output This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
-{
-  MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
-}
-
-/**
-  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
-  * @note   used only when RTC_ALARM is mapped on PC13
-  * @rmtoll TAFCR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
-  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
-}
-
-/**
-  * @brief  Enable initialization mode
-  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
-  *         and prescaler register (RTC_PRER).
-  *         Counters are stopped and start counting from the new value when INIT is reset.
-  * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Set the Initialization mode */
-  WRITE_REG(RTCx->ISR, LL_RTC_INIT_MASK);
-}
-
-/**
-  * @brief  Disable initialization mode (Free running mode)
-  * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Exit Initialization mode */
-  WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
-}
-
-/**
-  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
-  * @param  RTCx RTC Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
-}
-
-/**
-  * @brief  Get Output polarity
-  * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
-  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
-}
-
-#if defined(RTC_CR_BYPSHAD)
-/**
-  * @brief  Enable Bypass the shadow registers
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
-  * @brief  Disable Bypass the shadow registers
-  * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
-}
-
-/**
-  * @brief  Check if Shadow registers bypass is enabled or not.
-  * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
-}
-
-#endif /* RTC_CR_BYPSHAD */
-/**
-  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
-  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
-  * @brief  Set Asynchronous prescaler factor
-  * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
-  * @param  RTCx RTC Instance
-  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
-{
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
-  * @brief  Set Synchronous prescaler factor
-  * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
-  * @param  RTCx RTC Instance
-  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
-{
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
-}
-
-/**
-  * @brief  Get Asynchronous prescaler factor
-  * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
-  * @brief  Get Synchronous prescaler factor
-  * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
-}
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
-}
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
-  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Time Time
-  * @{
-  */
-
-/**
-  * @brief  Set time format (AM/24-hour or PM notation)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get time format (AM or PM notation)
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
-}
-
-/**
-  * @brief  Set Hours in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
-  * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
-  *         TR           HU            LL_RTC_TIME_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
-             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
-}
-
-/**
-  * @brief  Get Hours in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
-  *       Binary format
-  * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
-  *         TR           HU            LL_RTC_TIME_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
-}
-
-/**
-  * @brief  Set Minutes in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
-  *         TR           MNU           LL_RTC_TIME_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
-             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get Minutes in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
-  *       to Binary format
-  * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
-  *         TR           MNU           LL_RTC_TIME_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
-}
-
-/**
-  * @brief  Set Seconds in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
-  *         TR           SU            LL_RTC_TIME_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
-             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
-}
-
-/**
-  * @brief  Get Seconds in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
-  *       to Binary format
-  * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
-  *         TR           SU            LL_RTC_TIME_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
-}
-
-/**
-  * @brief  Set time (hour, minute and second) in BCD format
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @note TimeFormat and Hours should follow the same format
-  * @rmtoll TR           PM            LL_RTC_TIME_Config\n
-  *         TR           HT            LL_RTC_TIME_Config\n
-  *         TR           HU            LL_RTC_TIME_Config\n
-  *         TR           MNT           LL_RTC_TIME_Config\n
-  *         TR           MNU           LL_RTC_TIME_Config\n
-  *         TR           ST            LL_RTC_TIME_Config\n
-  *         TR           SU            LL_RTC_TIME_Config
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
-  *         @arg @ref LL_RTC_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24                                                                                    | \
-         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
-         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
-  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
-}
-
-/**
-  * @brief  Get time (hour, minute and second) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
-  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  *       are available to get independently each parameter.
-  * @rmtoll TR           HT            LL_RTC_TIME_Get\n
-  *         TR           HU            LL_RTC_TIME_Get\n
-  *         TR           MNT           LL_RTC_TIME_Get\n
-  *         TR           MNU           LL_RTC_TIME_Get\n
-  *         TR           ST            LL_RTC_TIME_Get\n
-  *         TR           SU            LL_RTC_TIME_Get
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
-  return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) |  \
-                    (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
-                    ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
-}
-
-/**
-  * @brief  Memorize whether the daylight saving time change has been performed
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
-  * @brief  Disable memorization whether the daylight saving time change has been performed.
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
-  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
-  * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Subtract 1 hour (winter time change)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_SUB1H);
-}
-
-/**
-  * @brief  Add 1 hour (summer time change)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ADD1H);
-}
-
-#if defined(RTC_SUBSECOND_SUPPORT)
-/**
-  * @brief  Get Sub second value in the synchronous prescaler counter.
-  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
-  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
-  *        SubSeconds value in second fraction ratio with time unit following
-  *        generic formula:
-  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending
-  *        (ie. SHFP=0) when PREDIV_S >= SS.
-  * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Sub second value (number between 0 and 65535)
-  */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
-}
-#endif /* RTC_SUBSECOND_SUPPORT */
-
-#if defined(RTC_SHIFTR_ADD1S)
-/**
-  * @brief  Synchronize to a remote clock with a high degree of precision.
-  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   When REFCKON is set, firmware must not write to Shift control register.
-  * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
-  *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
-  * @param  RTCx RTC Instance
-  * @param  ShiftSecond This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
-  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
-  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
-{
-  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
-}
-#endif /* RTC_SHIFTR_ADD1S */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Date Date
-  * @{
-  */
-
-/**
-  * @brief  Set Year in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
-  * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
-  *         DR           YU            LL_RTC_DATE_SetYear
-  * @param  RTCx RTC Instance
-  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
-             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
-}
-
-/**
-  * @brief  Get Year in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
-  * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
-  *         DR           YU            LL_RTC_DATE_GetYear
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x99
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
-}
-
-/**
-  * @brief  Set Week day
-  * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
-}
-
-/**
-  * @brief  Get Week day
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
-}
-
-/**
-  * @brief  Set Month in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
-  * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
-  *         DR           MU            LL_RTC_DATE_SetMonth
-  * @param  RTCx RTC Instance
-  * @param  Month This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
-             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
-}
-
-/**
-  * @brief  Get Month in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
-  * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
-  *         DR           MU            LL_RTC_DATE_GetMonth
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
-}
-
-/**
-  * @brief  Set Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
-  *         DR           DU            LL_RTC_DATE_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
-             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
-}
-
-/**
-  * @brief  Get Day in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
-  *         DR           DU            LL_RTC_DATE_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
-}
-
-/**
-  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
-  * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
-  *         DR           MT            LL_RTC_DATE_Config\n
-  *         DR           MU            LL_RTC_DATE_Config\n
-  *         DR           DT            LL_RTC_DATE_Config\n
-  *         DR           DU            LL_RTC_DATE_Config\n
-  *         DR           YT            LL_RTC_DATE_Config\n
-  *         DR           YU            LL_RTC_DATE_Config
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @param  Month This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
-{
-  uint32_t temp;
-
-  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
-         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
-         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
-         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
-
-  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
-}
-
-/**
-  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
-  *       before reading this bit
-  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
-  * and __LL_RTC_GET_DAY are available to get independently each parameter.
-  * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
-  *         DR           MT            LL_RTC_DATE_Get\n
-  *         DR           MU            LL_RTC_DATE_Get\n
-  *         DR           DT            LL_RTC_DATE_Get\n
-  *         DR           DU            LL_RTC_DATE_Get\n
-  *         DR           YT            LL_RTC_DATE_Get\n
-  *         DR           YU            LL_RTC_DATE_Get
-  * @param  RTCx RTC Instance
-  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
-  */
-__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
-{
-  uint32_t temp;
-
-  temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
-  return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
-                    (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
-                    (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
-                    ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_ALARMA ALARMA
-  * @{
-  */
-
-/**
-  * @brief  Enable Alarm A
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
-  * @brief  Disable Alarm A
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
-  * @brief  Specify the Alarm A masks.
-  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
-  *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMA_MASK_NONE
-  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMA_MASK_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
-}
-
-/**
-  * @brief  Get the Alarm A masks.
-  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
-  *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMA_MASK_NONE
-  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMA_MASK_ALL
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
-}
-
-/**
-  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
-  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
-  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
-  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
-  * @brief  Set ALARM A Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
-  *         ALRMAR       DU            LL_RTC_ALMA_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
-             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
-  *         ALRMAR       DU            LL_RTC_ALMA_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
-  * @brief  Set ALARM A Weekday
-  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
-}
-
-/**
-  * @brief  Get ALARM A Weekday
-  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
-  * @brief  Set Alarm A time format (AM/24-hour or PM notation)
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get Alarm A time format (AM or PM notation)
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
-}
-
-/**
-  * @brief  Set ALARM A Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
-  *         ALRMAR       HU            LL_RTC_ALMA_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
-             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
-  *         ALRMAR       HU            LL_RTC_ALMA_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
-}
-
-/**
-  * @brief  Set ALARM A Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
-             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
-}
-
-/**
-  * @brief  Set ALARM A Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
-  *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
-             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM A Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
-  *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
-}
-
-/**
-  * @brief  Set Alarm A Time (hour, minute and second) in BCD format
-  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
-  *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
-         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
-
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
-}
-
-/**
-  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
-  *         ALRMAR       SU            LL_RTC_ALMA_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
-}
-
-#if defined(RTC_SUBSECOND_SUPPORT)
-/**
-  * @brief  Set Alarm A Mask the most-significant bits starting at this bit
-  * @note This register can be written only when ALRAE is reset in RTC_CR register,
-  *       or in initialization mode.
-  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Get Alarm A Mask the most-significant bits starting at this bit
-  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Set Alarm A Sub seconds value
-  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
-  * @param  RTCx RTC Instance
-  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
-}
-
-/**
-  * @brief  Get Alarm A Sub seconds value
-  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
-}
-#endif /* RTC_SUBSECOND_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_ALARMB ALARMB
-  * @{
-  */
-
-/**
-  * @brief  Enable Alarm B
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
-  * @brief  Disable Alarm B
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
-  * @brief  Specify the Alarm B masks.
-  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
-  *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
-  * @param  RTCx RTC Instance
-  * @param  Mask This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMB_MASK_NONE
-  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMB_MASK_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
-}
-
-/**
-  * @brief  Get the Alarm B masks.
-  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
-  *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_RTC_ALMB_MASK_NONE
-  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
-  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
-  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
-  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
-  *         @arg @ref LL_RTC_ALMB_MASK_ALL
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
-}
-
-/**
-  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
-  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
-  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
-  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
-  * @brief  Set ALARM B Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
-  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
-  *         ALRMBR       DU            LL_RTC_ALMB_SetDay
-  * @param  RTCx RTC Instance
-  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
-             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
-  *         ALRMBR       DU            LL_RTC_ALMB_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
-  * @brief  Set ALARM B Weekday
-  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
-  * @param  RTCx RTC Instance
-  * @param  WeekDay This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
-}
-
-/**
-  * @brief  Get ALARM B Weekday
-  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
-  * @brief  Set ALARM B time format (AM/24-hour or PM notation)
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
-  * @param  RTCx RTC Instance
-  * @param  TimeFormat This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
-}
-
-/**
-  * @brief  Get ALARM B time format (AM or PM notation)
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
-}
-
-/**
-  * @brief  Set ALARM B Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
-  *         ALRMBR       HU            LL_RTC_ALMB_SetHour
-  * @param  RTCx RTC Instance
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
-             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
-  *         ALRMBR       HU            LL_RTC_ALMB_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
-}
-
-/**
-  * @brief  Set ALARM B Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
-  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
-  * @param  RTCx RTC Instance
-  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
-             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
-}
-
-/**
-  * @brief  Set ALARM B Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
-  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
-  *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
-  * @param  RTCx RTC Instance
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
-  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
-             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
-}
-
-/**
-  * @brief  Get ALARM B Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
-  *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
-}
-
-/**
-  * @brief  Set Alarm B Time (hour, minute and second) in BCD format
-  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
-  *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
-  * @param  RTCx RTC Instance
-  * @param  Format12_24 This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
-  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
-  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
-  uint32_t temp;
-
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
-         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
-         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
-
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
-}
-
-/**
-  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
-  *         ALRMBR       SU            LL_RTC_ALMB_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
-}
-
-#if defined(RTC_SUBSECOND_SUPPORT)
-/**
-  * @brief  Set Alarm B Mask the most-significant bits starting at this bit
-  * @note This register can be written only when ALRBE is reset in RTC_CR register,
-  *       or in initialization mode.
-  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
-  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Get Alarm B Mask the most-significant bits starting at this bit
-  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
-}
-
-/**
-  * @brief  Set Alarm B Sub seconds value
-  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
-  * @param  RTCx RTC Instance
-  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
-{
-  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
-}
-
-/**
-  * @brief  Get Alarm B Sub seconds value
-  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
-}
-#endif /* RTC_SUBSECOND_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Timestamp Timestamp
-  * @{
-  */
-
-/**
-  * @brief  Enable Timestamp
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSE           LL_RTC_TS_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
-  * @brief  Disable Timestamp
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSE           LL_RTC_TS_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
-  * @brief  Set Time-stamp event active edge
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
-  * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
-  * @param  RTCx RTC Instance
-  * @param  Edge This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
-}
-
-/**
-  * @brief  Get Time-stamp event active edge
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
-  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
-}
-
-/**
-  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
-  * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
-  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
-}
-
-/**
-  * @brief  Get Timestamp Hours in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
-  * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
-  *         TSTR         HU            LL_RTC_TS_GetHour
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Minutes in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
-  * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
-  *         TSTR         MNU           LL_RTC_TS_GetMinute
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Seconds in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
-  * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
-  *         TSTR         SU            LL_RTC_TS_GetSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x59
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
-  * @brief  Get Timestamp time (hour, minute and second) in BCD format
-  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
-  * are available to get independently each parameter.
-  * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
-  *         TSTR         HU            LL_RTC_TS_GetTime\n
-  *         TSTR         MNT           LL_RTC_TS_GetTime\n
-  *         TSTR         MNU           LL_RTC_TS_GetTime\n
-  *         TSTR         ST            LL_RTC_TS_GetTime\n
-  *         TSTR         SU            LL_RTC_TS_GetTime
-  * @param  RTCx RTC Instance
-  * @retval Combination of hours, minutes and seconds.
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSTR,
-                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
-  * @brief  Get Timestamp Week day
-  * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
-  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
-  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
-  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
-  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Month in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
-  * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
-  *         TSDR         MU            LL_RTC_TS_GetMonth
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_MONTH_JANUARY
-  *         @arg @ref LL_RTC_MONTH_FEBRUARY
-  *         @arg @ref LL_RTC_MONTH_MARCH
-  *         @arg @ref LL_RTC_MONTH_APRIL
-  *         @arg @ref LL_RTC_MONTH_MAY
-  *         @arg @ref LL_RTC_MONTH_JUNE
-  *         @arg @ref LL_RTC_MONTH_JULY
-  *         @arg @ref LL_RTC_MONTH_AUGUST
-  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
-  *         @arg @ref LL_RTC_MONTH_OCTOBER
-  *         @arg @ref LL_RTC_MONTH_NOVEMBER
-  *         @arg @ref LL_RTC_MONTH_DECEMBER
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
-}
-
-/**
-  * @brief  Get Timestamp Day in BCD format
-  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
-  * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
-  *         TSDR         DU            LL_RTC_TS_GetDay
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x01 and Max_Data=0x31
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
-  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
-  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
-  * and __LL_RTC_GET_DAY are available to get independently each parameter.
-  * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
-  *         TSDR         MT            LL_RTC_TS_GetDate\n
-  *         TSDR         MU            LL_RTC_TS_GetDate\n
-  *         TSDR         DT            LL_RTC_TS_GetDate\n
-  *         TSDR         DU            LL_RTC_TS_GetDate
-  * @param  RTCx RTC Instance
-  * @retval Combination of Weekday, Day and Month
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-#if defined(RTC_SUBSECOND_SUPPORT)
-/**
-  * @brief  Get time-stamp sub second value
-  * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
-}
-#endif /* RTC_SUBSECOND_SUPPORT */
-
-#if defined(RTC_TAFCR_TAMPTS)
-/**
-  * @brief  Activate timestamp on tamper detection event
-  * @rmtoll TAFCR       TAMPTS        LL_RTC_TS_EnableOnTamper
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-
-/**
-  * @brief  Disable timestamp on tamper detection event
-  * @rmtoll TAFCR       TAMPTS        LL_RTC_TS_DisableOnTamper
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-#endif /* RTC_TAFCR_TAMPTS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_Tamper Tamper
-  * @{
-  */
-
-/**
-  * @brief  Enable RTC_TAMPx input detection
-  * @rmtoll TAFCR       TAMP1E        LL_RTC_TAMPER_Enable\n
-  *         TAFCR       TAMP2E        LL_RTC_TAMPER_Enable\n
-  *         TAFCR       TAMP3E        LL_RTC_TAMPER_Enable
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_1
-  *         @arg @ref LL_RTC_TAMPER_2 (*)
-  *         @arg @ref LL_RTC_TAMPER_3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
-  * @brief  Clear RTC_TAMPx input detection
-  * @rmtoll TAFCR       TAMP1E        LL_RTC_TAMPER_Disable\n
-  *         TAFCR       TAMP2E        LL_RTC_TAMPER_Disable\n
-  *         TAFCR       TAMP3E        LL_RTC_TAMPER_Disable
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_1
-  *         @arg @ref LL_RTC_TAMPER_2 (*)
-  *         @arg @ref LL_RTC_TAMPER_3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-#if defined(RTC_TAFCR_TAMPPUDIS)
-/**
-  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
-  * @rmtoll TAFCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-
-/**
-  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
-  * @rmtoll TAFCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-#endif /* RTC_TAFCR_TAMPPUDIS */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/**
-  * @brief  Set RTC_TAMPx precharge duration
-  * @rmtoll TAFCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
-  * @param  RTCx RTC Instance
-  * @param  Duration This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
-{
-  MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
-}
-
-/**
-  * @brief  Get RTC_TAMPx precharge duration
-  * @rmtoll TAFCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
-  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
-}
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/**
-  * @brief  Set RTC_TAMPx filter count
-  * @rmtoll TAFCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
-  * @param  RTCx RTC Instance
-  * @param  FilterCount This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
-{
-  MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
-}
-
-/**
-  * @brief  Get RTC_TAMPx filter count
-  * @rmtoll TAFCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
-  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
-}
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/**
-  * @brief  Set Tamper sampling frequency
-  * @rmtoll TAFCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
-  * @param  RTCx RTC Instance
-  * @param  SamplingFreq This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
-{
-  MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
-}
-
-/**
-  * @brief  Get Tamper sampling frequency
-  * @rmtoll TAFCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
-  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
-  */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
-}
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/**
-  * @brief  Enable Active level for Tamper input
-  * @rmtoll TAFCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
-  *         TAFCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
-  *         TAFCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*)
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
-  * @brief  Disable Active level for Tamper input
-  * @rmtoll TAFCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
-  *         TAFCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
-  *         TAFCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
-  * @param  RTCx RTC Instance
-  * @param  Tamper This parameter can be a combination of the following values:
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*)
-  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
-  CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Wakeup Wakeup
-  * @{
-  */
-
-/**
-  * @brief  Enable Wakeup timer
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
-  * @brief  Disable Wakeup timer
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
-  * @brief  Check if Wakeup timer is enabled or not
-  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Wakeup clock
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
-  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
-  * @param  RTCx RTC Instance
-  * @param  WakeupClock This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
-{
-  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
-}
-
-/**
-  * @brief  Get Wakeup clock
-  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
-  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
-}
-
-/**
-  * @brief  Set Wakeup auto-reload value
-  * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
-  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
-  * @param  RTCx RTC Instance
-  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
-{
-  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
-}
-
-/**
-  * @brief  Get Wakeup auto-reload value
-  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
-}
-
-/**
-  * @}
-  */
-#endif /* RTC_WAKEUP_SUPPORT */
-
-#if defined(RTC_BACKUP_SUPPORT)
-/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
-  * @param  RTCx RTC Instance
-  * @param  BackupRegister This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_BKP_DR0
-  *         @arg @ref LL_RTC_BKP_DR1
-  *         @arg @ref LL_RTC_BKP_DR2
-  *         @arg @ref LL_RTC_BKP_DR3
-  *         @arg @ref LL_RTC_BKP_DR4
-  *         @arg @ref LL_RTC_BKP_DR5 (*)
-  *         @arg @ref LL_RTC_BKP_DR6 (*)
-  *         @arg @ref LL_RTC_BKP_DR7 (*)
-  *         @arg @ref LL_RTC_BKP_DR8 (*)
-  *         @arg @ref LL_RTC_BKP_DR9 (*)
-  *         @arg @ref LL_RTC_BKP_DR10 (*)
-  *         @arg @ref LL_RTC_BKP_DR11 (*)
-  *         @arg @ref LL_RTC_BKP_DR12 (*)
-  *         @arg @ref LL_RTC_BKP_DR13 (*)
-  *         @arg @ref LL_RTC_BKP_DR14 (*)
-  *         @arg @ref LL_RTC_BKP_DR15 (*)
-  *         @arg @ref LL_RTC_BKP_DR16 (*)
-  *         @arg @ref LL_RTC_BKP_DR17 (*)
-  *         @arg @ref LL_RTC_BKP_DR18 (*)
-  *         @arg @ref LL_RTC_BKP_DR19 (*)
-  *         @arg @ref LL_RTC_BKP_DR20 (*)
-  *         @arg @ref LL_RTC_BKP_DR21 (*)
-  *         @arg @ref LL_RTC_BKP_DR22 (*)
-  *         @arg @ref LL_RTC_BKP_DR23 (*)
-  *         @arg @ref LL_RTC_BKP_DR24 (*)
-  *         @arg @ref LL_RTC_BKP_DR25 (*)
-  *         @arg @ref LL_RTC_BKP_DR26 (*)
-  *         @arg @ref LL_RTC_BKP_DR27 (*)
-  *         @arg @ref LL_RTC_BKP_DR28 (*)
-  *         @arg @ref LL_RTC_BKP_DR29 (*)
-  *         @arg @ref LL_RTC_BKP_DR30 (*)
-  *         @arg @ref LL_RTC_BKP_DR31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp = 0U;
-
-  tmp = (uint32_t)(&(RTCx->BKP0R));
-  tmp += (BackupRegister * 4U);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
-  * @param  RTCx RTC Instance
-  * @param  BackupRegister This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_BKP_DR0
-  *         @arg @ref LL_RTC_BKP_DR1
-  *         @arg @ref LL_RTC_BKP_DR2
-  *         @arg @ref LL_RTC_BKP_DR3
-  *         @arg @ref LL_RTC_BKP_DR4
-  *         @arg @ref LL_RTC_BKP_DR5 (*)
-  *         @arg @ref LL_RTC_BKP_DR6 (*)
-  *         @arg @ref LL_RTC_BKP_DR7 (*)
-  *         @arg @ref LL_RTC_BKP_DR8 (*)
-  *         @arg @ref LL_RTC_BKP_DR9 (*)
-  *         @arg @ref LL_RTC_BKP_DR10 (*)
-  *         @arg @ref LL_RTC_BKP_DR11 (*)
-  *         @arg @ref LL_RTC_BKP_DR12 (*)
-  *         @arg @ref LL_RTC_BKP_DR13 (*)
-  *         @arg @ref LL_RTC_BKP_DR14 (*)
-  *         @arg @ref LL_RTC_BKP_DR15 (*)
-  *         @arg @ref LL_RTC_BKP_DR16 (*)
-  *         @arg @ref LL_RTC_BKP_DR17 (*)
-  *         @arg @ref LL_RTC_BKP_DR18 (*)
-  *         @arg @ref LL_RTC_BKP_DR19 (*)
-  *         @arg @ref LL_RTC_BKP_DR20 (*)
-  *         @arg @ref LL_RTC_BKP_DR21 (*)
-  *         @arg @ref LL_RTC_BKP_DR22 (*)
-  *         @arg @ref LL_RTC_BKP_DR23 (*)
-  *         @arg @ref LL_RTC_BKP_DR24 (*)
-  *         @arg @ref LL_RTC_BKP_DR25 (*)
-  *         @arg @ref LL_RTC_BKP_DR26 (*)
-  *         @arg @ref LL_RTC_BKP_DR27 (*)
-  *         @arg @ref LL_RTC_BKP_DR28 (*)
-  *         @arg @ref LL_RTC_BKP_DR29 (*)
-  *         @arg @ref LL_RTC_BKP_DR30 (*)
-  *         @arg @ref LL_RTC_BKP_DR31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
-{
-  uint32_t tmp = 0U;
-
-  tmp = (uint32_t)(&(RTCx->BKP0R));
-  tmp += (BackupRegister * 4U);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @}
-  */
-#endif /* RTC_BACKUP_SUPPORT */
-
-/** @defgroup RTC_LL_EF_Calibration Calibration
-  * @{
-  */
-
-/**
-  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
-  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
-  *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
-  * @param  RTCx RTC Instance
-  * @param  Frequency This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ (*)
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
-{
-#if defined(RTC_CR_COSEL)
-  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
-#else
-  MODIFY_REG(RTCx->CR, RTC_CR_COE, Frequency);
-#endif /* RTC_CR_COSEL */
-}
-
-/**
-  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
-  * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
-  *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ (*)
-  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
-{
-#if defined(RTC_CR_COSEL)
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
-#else
-  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE));
-#endif /* RTC_CR_COSEL */
-}
-
-/**
-  * @brief  Enable Coarse digital calibration
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           DCE           LL_RTC_CAL_EnableCoarseDigital
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_EnableCoarseDigital(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_DCE);
-}
-
-/**
-  * @brief  Disable Coarse digital calibration
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CR           DCE           LL_RTC_CAL_DisableCoarseDigital
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_DisableCoarseDigital(RTC_TypeDef  *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_DCE);
-}
-
-/**
-  * @brief  Set the coarse digital calibration
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
-  * @rmtoll CALIBR       DCS           LL_RTC_CAL_ConfigCoarseDigital\n
-  *         CALIBR       DC            LL_RTC_CAL_ConfigCoarseDigital
-  * @param  RTCx RTC Instance
-  * @param  Sign This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
-  *         @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
-  * @param  Value value of coarse calibration expressed in ppm (coded on 5 bits)
-  * @note   This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
-  * @note   This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef *RTCx, uint32_t Sign, uint32_t Value)
-{
-  MODIFY_REG(RTCx->CALIBR, RTC_CALIBR_DCS | RTC_CALIBR_DC, Sign | Value);
-}
-
-/**
-  * @brief  Get the coarse digital calibration value
-  * @rmtoll CALIBR       DC            LL_RTC_CAL_GetCoarseDigitalValue
-  * @param  RTCx RTC Instance
-  * @retval value of coarse calibration expressed in ppm (coded on 5 bits)
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalValue(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DC));
-}
-
-/**
-  * @brief  Get the coarse digital calibration sign
-  * @rmtoll CALIBR       DCS           LL_RTC_CAL_GetCoarseDigitalSign
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
-  *         @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DCS));
-}
-
-#if defined(RTC_SMOOTHCALIB_SUPPORT)
-/**
-  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
-  * @param  RTCx RTC Instance
-  * @param  Pulse This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
-  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
-}
-
-/**
-  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
-  * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the calibration cycle period
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
-  *         CALR         CALW16        LL_RTC_CAL_SetPeriod
-  * @param  RTCx RTC Instance
-  * @param  Period This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
-}
-
-/**
-  * @brief  Get the calibration cycle period
-  * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
-  *         CALR         CALW16        LL_RTC_CAL_GetPeriod
-  * @param  RTCx RTC Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
-  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
-}
-
-/**
-  * @brief  Set Calibration minus
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
-  * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
-  * @param  RTCx RTC Instance
-  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
-{
-  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
-}
-
-/**
-  * @brief  Get Calibration minus
-  * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
-  * @param  RTCx RTC Instance
-  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
-  */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
-{
-  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
-}
-#endif /* RTC_SMOOTHCALIB_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-#if defined(RTC_SMOOTHCALIB_SUPPORT)
-/**
-  * @brief  Get Recalibration pending Flag
-  * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
-}
-#endif /* RTC_SMOOTHCALIB_SUPPORT */
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP3 detection flag
-  * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP2 detection flag
-  * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Get RTC_TAMP1 detection flag
-  * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Get Time-stamp overflow flag
-  * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Time-stamp flag
-  * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Get Wakeup timer flag
-  * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Get Alarm B flag
-  * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Alarm A flag
-  * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
-
-}
-
-#if defined(RTC_TAMPER3_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP3 detection flag
-  * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER3_SUPPORT */
-
-#if defined(RTC_TAMPER2_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP2 detection flag
-  * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER2_SUPPORT */
-
-#if defined(RTC_TAMPER1_SUPPORT)
-/**
-  * @brief  Clear RTC_TAMP1 detection flag
-  * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_TAMPER1_SUPPORT */
-
-/**
-  * @brief  Clear Time-stamp overflow flag
-  * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Clear Time-stamp flag
-  * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Clear Wakeup timer flag
-  * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Clear Alarm B flag
-  * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Clear Alarm A flag
-  * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Get Initialization flag
-  * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Registers synchronization flag
-  * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Registers synchronization flag
-  * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
-{
-  WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
-  * @brief  Get Initialization status flag
-  * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_ISR_SHPF)
-/**
-  * @brief  Get Shift operation pending flag
-  * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
-}
-#endif /* RTC_ISR_SHPF */
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Get Wakeup timer write flag
-  * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Get Alarm B write flag
-  * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Alarm A write flag
-  * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable Time-stamp interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-/**
-  * @brief  Disable Time-stamp interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Enable Wakeup timer interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-
-/**
-  * @brief  Disable Wakeup timer interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Enable Alarm B interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
-  * @brief  Disable Alarm B interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
-  * @brief  Enable Alarm A interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
-  * @brief  Disable Alarm A interrupt
-  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
-  * @brief  Enable all Tamper Interrupt
-  * @rmtoll TAFCR       TAMPIE        LL_RTC_EnableIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
-{
-  SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
-  * @brief  Disable all Tamper Interrupt
-  * @rmtoll TAFCR       TAMPIE        LL_RTC_DisableIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
-{
-  CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
-  * @brief  Check if  Time-stamp interrupt is enabled or not
-  * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
-}
-
-#if defined(RTC_WAKEUP_SUPPORT)
-/**
-  * @brief  Check if  Wakeup timer interrupt is enabled or not
-  * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
-}
-#endif /* RTC_WAKEUP_SUPPORT */
-
-/**
-  * @brief  Check if  Alarm B interrupt is enabled or not
-  * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if  Alarm A interrupt is enabled or not
-  * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
-
-}
-
-/**
-  * @brief  Check if all the TAMPER interrupts are enabled or not
-  * @rmtoll TAFCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
-  * @param  RTCx RTC Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
-{
-  return ((READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
-void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
-void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
-void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RTC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h
deleted file mode 100644
index 71610065735..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_sdmmc.h
+++ /dev/null
@@ -1,1115 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @brief   Header file of SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_SDMMC_H
-#define STM32L1xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(SDIO)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  SDMMC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
-                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
-  
-}SDIO_InitTypeDef;
-  
-
-/** 
-  * @brief  SDMMC Command Control structure 
-  */
-typedef struct                                                                                            
-{
-  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDMMC response type.
-                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
-}SDIO_CmdInitTypeDef;
-
-
-/** 
-  * @brief  SDMMC Data Control structure 
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
- 
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
- 
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
- 
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
- 
-  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
-}SDIO_DataInitTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-#define SDMMC_ERROR_NONE                                0x00000000U    /*!< No error                                                      */
-#define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    /*!< Command response received (but CRC check failed)              */
-#define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    /*!< Data block sent/received (CRC check failed)                   */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    /*!< Command response timeout                                      */
-#define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    /*!< Data timeout                                                  */
-#define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    /*!< Transmit FIFO underrun                                        */
-#define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    /*!< Receive FIFO overrun                                          */
-#define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    /*!< Misaligned address                                            */
-#define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    /*!< Transferred block length is not allowed for the card or the
-                                                                            number of transferred bytes does not match the block length   */
-#define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    /*!< An error in the sequence of erase command occurs              */
-#define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    /*!< An invalid selection for erase groups                         */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    /*!< Attempt to program a write protect block                      */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    /*!< Sequence or password error has been detected in unlock
-                                                                            command or if there was an attempt to access a locked card    */
-#define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    /*!< CRC check of the previous command failed                      */
-#define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    /*!< Command is not legal for the card state                       */
-#define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    /*!< Card internal ECC was applied but failed to correct the data  */
-#define SDMMC_ERROR_CC_ERR                              0x00008000U    /*!< Internal card controller error                                */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    /*!< General or unknown error                                      */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    /*!< The card could not sustain data reading in stream rmode       */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    /*!< The card could not sustain data programming in stream mode    */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    /*!< CID/CSD overwrite error                                       */
-#define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    /*!< Only partial address space was erased                         */
-#define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    /*!< Command has been executed without using internal ECC          */
-#define SDMMC_ERROR_ERASE_RESET                         0x00400000U    /*!< Erase sequence was cleared before executing because an out
-                                                                            of erase sequence command was received                        */
-#define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    /*!< Error in sequence of authentication                           */
-#define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    /*!< Error in case of invalid voltage range                        */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    /*!< Error when addressed block is out of range                    */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    /*!< Error when command request is not applicable                  */
-#define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    /*!< the used parameter is not valid                               */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    /*!< Error when feature is not insupported                         */
-#define SDMMC_ERROR_BUSY                                0x20000000U    /*!< Error when transfer process is busy                           */
-#define SDMMC_ERROR_DMA                                 0x40000000U    /*!< Error while DMA transfer                                      */
-#define SDMMC_ERROR_TIMEOUT                             0x80000000U    /*!< Timeout error                                                 */
-
-/** 
-  * @brief SDMMC Commands Index 
-  */
-#define SDMMC_CMD_GO_IDLE_STATE                                 0U    /*!< Resets the SD memory card.                                                               */
-#define SDMMC_CMD_SEND_OP_COND                                  1U    /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID                                  2U    /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SDMMC_CMD_SET_REL_ADDR                                  3U    /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SDMMC_CMD_SET_DSR                                       4U    /*!< Programs the DSR of all cards.                                                           */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
-                                                                           operating condition register (OCR) content in the response on the CMD line.              */
-#define SDMMC_CMD_HS_SWITCH                                     6U    /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SDMMC_CMD_SEL_DESEL_CARD                                7U    /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
-                                                                           and asks the card whether card supports voltage.                                         */
-#define SDMMC_CMD_SEND_CSD                                      9U    /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SDMMC_CMD_SEND_CID                                      10U   /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   /*!< SD card doesn't support it.                                                              */
-#define SDMMC_CMD_STOP_TRANSMISSION                             12U   /*!< Forces the card to stop transmission.                                                    */
-#define SDMMC_CMD_SEND_STATUS                                   13U   /*!< Addressed card sends its status register.                                                */
-#define SDMMC_CMD_HS_BUSTEST_READ                               14U   /*!< Reserved                                                                                 */
-#define SDMMC_CMD_GO_INACTIVE_STATE                             15U   /*!< Sends an addressed card into the inactive state.                                         */
-#define SDMMC_CMD_SET_BLOCKLEN                                  16U   /*!< Sets the block length (in bytes for SDSC) for all following block commands
-                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                           for SDHS and SDXC.                                                                       */
-#define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
-                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SDMMC_CMD_READ_MULT_BLOCK                               18U   /*!< Continuously transfers data blocks from card to host until interrupted by
-                                                                           STOP_TRANSMISSION command.                                                               */
-#define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   /*!< Speed class control command.                                                             */
-#define SDMMC_CMD_SET_BLOCK_COUNT                               23U   /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
-                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SDMMC_CMD_PROG_CID                                      26U   /*!< Reserved for manufacturers.                                                              */
-#define SDMMC_CMD_PROG_CSD                                      27U   /*!< Programming of the programmable bits of the CSD.                                         */
-#define SDMMC_CMD_SET_WRITE_PROT                                28U   /*!< Sets the write protection bit of the addressed group.                                    */
-#define SDMMC_CMD_CLR_WRITE_PROT                                29U   /*!< Clears the write protection bit of the addressed group.                                  */
-#define SDMMC_CMD_SEND_WRITE_PROT                               30U   /*!< Asks the card to send the status of the write protection bits.                           */
-#define SDMMC_CMD_SD_ERASE_GRP_START                            32U   /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SDMMC_CMD_SD_ERASE_GRP_END                              33U   /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SDMMC_CMD_ERASE_GRP_START                               35U   /*!< Sets the address of the first write block to be erased. Reserved for each command
-                                                                           system set by switch function command (CMD6).                                            */
-#define SDMMC_CMD_ERASE_GRP_END                                 36U   /*!< Sets the address of the last write block of the continuous range to be erased.
-                                                                           Reserved for each command system set by switch function command (CMD6).                  */
-#define SDMMC_CMD_ERASE                                         38U   /*!< Reserved for SD security applications.                                                   */
-#define SDMMC_CMD_FAST_IO                                       39U   /*!< SD card doesn't support it (Reserved).                                                   */
-#define SDMMC_CMD_GO_IRQ_STATE                                  40U   /*!< SD card doesn't support it (Reserved).                                                   */
-#define SDMMC_CMD_LOCK_UNLOCK                                   42U   /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
-                                                                           the SET_BLOCK_LEN command.                                                               */
-#define SDMMC_CMD_APP_CMD                                       55U   /*!< Indicates to the card that the next command is an application specific command rather
-                                                                           than a standard command.                                                                 */
-#define SDMMC_CMD_GEN_CMD                                       56U   /*!< Used either to transfer a data block to the card or to get a data block from the card
-                                                                           for general purpose/application specific commands.                                       */
-#define SDMMC_CMD_NO_CMD                                        64U   /*!< No command                                                                               */
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDMMC_APP_CMD should be sent before sending these commands. 
-  */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
-                                                                            widths are given in SCR register.                                                       */
-#define SDMMC_CMD_SD_APP_STATUS                                 13U   /*!< (ACMD13) Sends the SD status.                                                            */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
-                                                                           32bit+CRC data block.                                                                    */
-#define SDMMC_CMD_SD_APP_OP_COND                                41U   /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
-                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
-#define SDMMC_CMD_SD_APP_SEND_SCR                               51U   /*!< Reads the SD Configuration Register (SCR).                                               */
-#define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   /*!< For SD I/O card only, reserved for security specification.                               */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   /*!< For SD I/O card only, reserved for security specification.                               */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SDMMC_CMD_SD_APP_GET_MKB                                43U
-#define SDMMC_CMD_SD_APP_GET_MID                                44U
-#define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
-#define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
-#define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
-#define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
-#define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U
-
-/** 
-  * @brief  Masks for errors Card Status R1 (OCR Register) 
-  */
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
-#define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
-#define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
-#define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
-#define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
-#define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
-#define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
-#define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
-#define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
-#define SDMMC_OCR_CC_ERROR                            0x00100000U
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
-#define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
-#define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
-#define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
-#define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
-#define SDMMC_OCR_ERASE_RESET                         0x00002000U
-#define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
-#define SDMMC_OCR_ERRORBITS                           0xFDFFE008U
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
-#define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
-#define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
-
-#define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
-#define SDMMC_HIGH_CAPACITY                           0x40000000U
-#define SDMMC_STD_CAPACITY                            0x00000000U
-#define SDMMC_CHECK_PATTERN                           0x000001AAU
-#define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
-
-#define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
-
-#define SDMMC_MAX_TRIAL                               0x0000FFFFU
-
-#define SDMMC_ALLZERO                                 0x00000000U
-
-#define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
-#define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
-#define SDMMC_CARD_LOCKED                             0x02000000U
-
-#ifndef SDMMC_DATATIMEOUT
-#define SDMMC_DATATIMEOUT                             0xFFFFFFFFU
-#endif /* SDMMC_DATATIMEOUT */
-
-#define SDMMC_0TO7BITS                                0x000000FFU
-#define SDMMC_8TO15BITS                               0x0000FF00U
-#define SDMMC_16TO23BITS                              0x00FF0000U
-#define SDMMC_24TO31BITS                              0xFF000000U
-#define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
-
-#define SDMMC_HALFFIFO                                0x00000008U
-#define SDMMC_HALFFIFOBYTES                           0x00000020U
-
-/** 
-  * @brief  Command Class supported
-  */
-#define SDIO_CCCC_ERASE                       0x00000020U
-
-#define SDIO_CMDTIMEOUT                       5000U         /* Command send and response timeout */
-#define SDIO_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
-#define SDIO_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */
-
-/** @defgroup SDIO_LL_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDIO_CLOCK_EDGE_RISING               0x00000000U
-#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
-                                          ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U
-#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
-                                              ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U
-#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
-                                                ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Bus_Wide Bus Width
-  * @{
-  */
-#define SDIO_BUS_WIDE_1B                      0x00000000U
-#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
-                                        ((WIDE) == SDIO_BUS_WIDE_4B) || \
-                                        ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                        ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDIO_LL_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
-/**
-  * @}
-  */  
-    
-/** @defgroup SDIO_LL_Command_Index Command Index
-  * @{
-  */
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Response_Type Response Type
-  * @{
-  */
-#define SDIO_RESPONSE_NO                    0x00000000U
-#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
-                                            ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
-                                            ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDIO_WAIT_NO                        0x00000000U
-#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
-#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
-                                    ((WAIT) == SDIO_WAIT_IT) || \
-                                    ((WAIT) == SDIO_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_CPSM_State CPSM State
-  * @{
-  */
-#define SDIO_CPSM_DISABLE                   0x00000000U
-#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
-                                    ((CPSM) == SDIO_CPSM_ENABLE))
-/**
-  * @}
-  */  
-
-/** @defgroup SDIO_LL_Response_Registers Response Register
-  * @{
-  */
-#define SDIO_RESP1                          0x00000000U
-#define SDIO_RESP2                          0x00000004U
-#define SDIO_RESP3                          0x00000008U
-#define SDIO_RESP4                          0x0000000CU
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
-                                    ((RESP) == SDIO_RESP2) || \
-                                    ((RESP) == SDIO_RESP3) || \
-                                    ((RESP) == SDIO_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Data_Length Data Length
-  * @{
-  */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Data_Block_Size  Data Block Size
-  * @{
-  */
-#define SDIO_DATABLOCK_SIZE_1B               0x00000000U
-#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
-#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 
-#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
-                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U
-#define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
-                                           ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDIO_TRANSFER_MODE_BLOCK             0x00000000U
-#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
-                                             ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_DPSM_State DPSM State
-  * @{
-  */
-#define SDIO_DPSM_DISABLE                    0x00000000U
-#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
-                                    ((DPSM) == SDIO_DPSM_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDIO_READ_WAIT_MODE_DATA2                0x00000000U
-#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
-                                             ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */  
-
-/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
-#define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
-#define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
-#define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
-#define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
-#define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
-#define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
-#define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
-#define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
-#define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
-#define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
-#define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
-#define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
-#define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
-#define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
-#define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
-#define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
-#define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
-#define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
-#define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
-#define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
-#define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
-#define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
-#define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
-/**
-  * @}
-  */ 
-
-/** @defgroup SDIO_LL_Flags Flags
-  * @{
-  */
-#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
-#define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
-                                                         SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
-                                                         SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
-                                                         SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
-
-#define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
-                                                         SDIO_FLAG_CMDSENT))
-
-#define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
-                                                         SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
-  * @{
-  */
-/* ------------ SDIO registers bit address in the alias region -------------- */
-#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
-#define CLKEN_BITNUMBER           0x08U
-#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
-#define SDIOSUSPEND_BITNUMBER     0x0BU
-#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER      0x0CU
-#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER            0x0DU
-#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER          0x0EU
-#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
-#define DMAEN_BITNUMBER           0x03U
-#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER         0x08U
-#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER          0x09U
-#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER           0x0AU
-#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER          0x0BU
-#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
-  * @brief SDIO_LL registers bit address in the alias region
-  * @{
-  */
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */ 
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
-                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
-                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
-                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
-                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
-                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
-
-/* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x1)
-/**
-  * @}
-  */
-
-/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
- 
-/**
-  * @brief  Enable the SDIO device.
-  * @param  __INSTANCE__: SDIO Instance  
-  * @retval None
-  */
-#define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO device.
-  * @param  __INSTANCE__: SDIO Instance  
-  * @retval None
-  */
-#define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @param  __INSTANCE__: SDIO Instance  
-  * @retval None
-  */
-#define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @param  __INSTANCE__: SDIO Instance   
-  * @retval None
-  */
-#define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
- 
-/**
-  * @brief  Enable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt 
-  * @retval None
-  */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
-  * @retval None
-  */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDIO flag is set or not. 
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
-  * @retval The new state of SDIO_FLAG (SET or RESET).
-  */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
-
-
-/**
-  * @brief  Clears the SDIO pending flags.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
-  * @retval None
-  */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
-  * @retval The new state of SDIO_IT (SET or RESET).
-  */
-#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDIO's interrupt pending bits.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
-  * @retval None
-  */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */
-#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */
-#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */
-#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */
-#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @retval None
-  */
-#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @retval None
-  */
-#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */
-#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @retval None
-  */
-#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
-/**
-  * @brief  Enable the command completion signal.
-  * @retval None
-  */    
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
-
-/**
-  * @brief  Disable the command completion signal.
-  * @retval None
-  */  
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
-
-/**
-  * @brief  Enable the CE-ATA interrupt.
-  * @retval None
-  */    
-#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
-
-/**
-  * @brief  Disable the CE-ATA interrupt.
-  * @retval None
-  */  
-#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
-
-/**
-  * @brief  Enable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
-
-/**
-  * @brief  Disable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-   
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */  
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
-  * @}
-  */
-  
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
-uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
-uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
-
-/* SDMMC Commands management functions */
-uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
-uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
-uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
-uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
-uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* SDIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h
deleted file mode 100644
index 4b883212c98..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h
+++ /dev/null
@@ -1,2002 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_SPI_H
-#define STM32L1xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @defgroup SPI_LL SPI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  SPI Init structures definition
-  */
-typedef struct
-{
-  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
-                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
-  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
-                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
-  uint32_t DataWidth;               /*!< Specifies the SPI data width.
-                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
-  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
-                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
-  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
-                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
-  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
-  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
-                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
-                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
-  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
-  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
-                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
-  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
-                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
-  * @{
-  */
-#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
-#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
-#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
-#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
-#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
-#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
-#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
-#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
-#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
-  * @brief  SPI TI Mode not supported for Category 1 and 2
-  * @{
-  */
-#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
-#if defined(SPI_CR2_FRF)
-#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
-#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
-  * @{
-  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
-  * @{
-  */
-#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
-  * @{
-  */
-#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
-#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
-#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
-  * @{
-  */
-#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
-#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
-#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
-#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
-  * @{
-  */
-#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable SPI peripheral
-  * @rmtoll CR1          SPE           LL_SPI_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Disable SPI peripheral
-  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
-  * @rmtoll CR1          SPE           LL_SPI_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Check if SPI peripheral is enabled
-  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set SPI operation mode to Master or Slave
-  * @note   This bit should not be changed when communication is ongoing.
-  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
-  *         CR1          SSI           LL_SPI_SetMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
-  * @brief  Get SPI operation mode (Master or Slave)
-  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
-  *         CR1          SSI           LL_SPI_GetMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-#if defined(SPI_CR2_FRF)
-/**
-  * @brief  Set serial protocol used. TI Mode not supported for Category 1 and 2.
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR2          FRF           LL_SPI_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
-  * @brief  Get serial protocol used
-  * @rmtoll CR2          FRF           LL_SPI_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-#endif
-
-/**
-  * @brief  Set clock phase
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
-  * @param  SPIx SPI Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Get clock phase
-  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
-  * @brief  Set clock polarity
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Get clock polarity
-  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
-  * @brief  Set baud rate prescaler
-  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
-  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @param  BaudRate This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
-  * @brief  Get baud rate prescaler
-  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
-  * @brief  Set transfer bit order
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Get transfer bit order
-  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
-  * @brief  Set transfer direction mode
-  * @note   For Half-Duplex mode, Rx Direction is set by default.
-  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
-  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
-  * @param  SPIx SPI Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
-  * @brief  Get transfer direction mode
-  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
-  * @brief  Set frame data width
-  * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
-  * @param  SPIx SPI Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
-}
-
-/**
-  * @brief  Get frame data width
-  * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
-  * @{
-  */
-
-/**
-  * @brief  Enable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Disable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Check if CRC is enabled
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set CRCNext to transfer CRC on the line
-  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
-  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
-  * @brief  Set polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
-  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
-  * @brief  Get polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
-  * @brief  Get Rx CRC
-  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
-  * @brief  Get Tx CRC
-  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
-  * @{
-  */
-
-/**
-  * @brief  Set NSS mode
-  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
-  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
-  * @param  SPIx SPI Instance
-  * @param  NSS This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
-  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
-  * @brief  Get NSS mode
-  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
-  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
-  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
-  return (Ssm | Ssoe);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get mode fault error flag
-  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get busy flag
-  * @note   The BSY flag is cleared under any one of the following conditions:
-  * -When the SPI is correctly disabled
-  * -When a fault is detected in Master mode (MODF bit set to 1)
-  * -In Master mode, when it finishes a data transmission and no new data is ready to be
-  * sent
-  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
-  * each data transfer.
-  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
-}
-
-#if defined(SPI_CR2_FRF)
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
-}
-#endif
-
-/**
-  * @brief  Clear CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
-  * @brief  Clear mode fault error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_SR
-  *         register followed by a write access to the SPIx_CR1 register
-  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg_sr;
-  tmpreg_sr = SPIx->SR;
-  (void) tmpreg_sr;
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_DR
-  *         register followed by a read access to the SPIx_SR register
-  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->DR;
-  (void) tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @note   Clearing this flag is done by reading SPIx_SR register
-  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Enable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Disable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Disable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Check if error interrupt is enabled
-  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Rx buffer not empty interrupt is enabled
-  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
-  * @param  SPIx SPI Instance
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
-  return (uint32_t) &(SPIx->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData8
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
-  return (*((__IO uint8_t *)&SPIx->DR));
-}
-
-/**
-  * @brief  Read 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
-  * @brief  Write 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData8
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  *((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @brief  Write 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  SPIx->DR = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
-  * @{
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  I2S Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
-                                         This parameter can be a value of @ref I2S_LL_EC_MODE
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
-  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
-  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
-  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
-  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
-                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
-                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
-  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
-                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2S_ReadReg function
-  * @{
-  */
-#define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
-#define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
-#define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
-#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
-#define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
-#define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
-#define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
-  * @{
-  */
-#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
-#define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
-  * @{
-  */
-#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
-#define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
-#define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
-#define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
-#define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
-#define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
-  * @{
-  */
-#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
-#define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
-  * @{
-  */
-#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
-  * @{
-  */
-
-#define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
-#define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
-#define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
-#define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
-#define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
-#define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
-#define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
-#define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
-#define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
-#define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Select I2S mode and Enable I2S peripheral
-  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
-  *         I2SCFGR      I2SE          LL_I2S_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Disable I2S peripheral
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Check if I2S peripheral is enabled
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
-  * @param  SPIx SPI Instance
-  * @param  DataFormat This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
-  * @brief  Get I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
-  * @brief  Set I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
-  * @brief  Get I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
-  * @brief  Set I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
-  * @brief  Get I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
-  * @brief  Set I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
-  * @brief  Get I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
-  * @brief  Set I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
-  * @brief  Get I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
-  * @brief  Set I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
-  * @brief  Get I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
-  * @brief  Enable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Disable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Check if the master clock output (Pin MCK) is enabled
-  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
-  * @brief  Get busy flag
-  * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Get underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
-}
-
-#if defined(SPI_CR2_FRF)
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-#endif
-
-/**
-  * @brief  Get channel side flag.
-  * @note   0: Channel Left has to be transmitted or has been received\n
-  *         1: Channel Right has to be transmitted or has been received\n
-  *         It has no significance in PCM mode.
-  * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Clear underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Enable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Disable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Disable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Check if ERR IT is enabled
-  * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Check if RXNE IT is enabled
-  * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if TXE IT is enabled
-  * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
-  * @brief  Write 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-  LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h
deleted file mode 100644
index d4dcfd06c52..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h
+++ /dev/null
@@ -1,2006 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_system.h
-  * @author  MCD Application Team
-  * @brief   Header file of SYSTEM LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL SYSTEM driver contains a set of generic APIs that can be
-    used by user:
-      (+) Some of the FLASH features need to be handled in the SYSTEM file.
-      (+) Access to DBGCMU registers
-      (+) Access to SYSCFG registers
-      (+) Access to Routing Interfaces registers
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_SYSTEM_H
-#define __STM32L1xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI)
-
-/** @defgroup SYSTEM_LL SYSTEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
-  * @{
-  */
-
-/**
- * @brief Power-down in Run mode Flash key
- */
-#define FLASH_PDKEY1                  (0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2                  (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
-                                                       to unlock the RUN_PD bit in FLASH_ACR */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
-* @{
-*/
-#define LL_SYSCFG_REMAP_FLASH              (0x00000000U)                                         /*<! Main Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*<! System Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */
-#if defined(FSMC_R_BASE)
-#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
-#endif /* FSMC_R_BASE */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE
-  * @{
-  */
-#define LL_SYSCFG_BOOTMODE_FLASH               (0x00000000U)             /*<! Main Flash memory boot mode */
-#define LL_SYSCFG_BOOTMODE_SYSTEMFLASH         SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */
-#if defined(FSMC_BANK1)
-#define LL_SYSCFG_BOOTMODE_FSMC                SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */
-#endif /* FSMC_BANK1 */
-#define LL_SYSCFG_BOOTMODE_SRAM                SYSCFG_MEMRMP_BOOT_MODE   /*<! Embedded SRAM boot mode */
-/**
-  * @}
-  */
-
-#if defined(LCD)
-/** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection
-  * @{
-  */
-#define LL_SYSCFG_LCDCAPA_PB2              SYSCFG_PMC_LCD_CAPA_0 /*<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 */
-#define LL_SYSCFG_LCDCAPA_PB12             SYSCFG_PMC_LCD_CAPA_1 /*<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 */
-#define LL_SYSCFG_LCDCAPA_PB0              SYSCFG_PMC_LCD_CAPA_2 /*<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 */
-#define LL_SYSCFG_LCDCAPA_PE11             SYSCFG_PMC_LCD_CAPA_3 /*<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 */
-#define LL_SYSCFG_LCDCAPA_PE12             SYSCFG_PMC_LCD_CAPA_4 /*<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 */
-/**
-  * @}
-  */
-
-#endif /* LCD */
-
-/** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT
-  * @{
-  */
-#define LL_SYSCFG_EXTI_PORTA               0U /*!< EXTI PORT A                        */
-#define LL_SYSCFG_EXTI_PORTB               1U /*!< EXTI PORT B                        */
-#define LL_SYSCFG_EXTI_PORTC               2U /*!< EXTI PORT C                        */
-#define LL_SYSCFG_EXTI_PORTD               3U /*!< EXTI PORT D                        */
-#if defined(GPIOE)
-#define LL_SYSCFG_EXTI_PORTE               4U /*!< EXTI PORT E                        */
-#endif /* GPIOE */
-#if defined(GPIOF)
-#define LL_SYSCFG_EXTI_PORTF               6U /*!< EXTI PORT F                        */
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_SYSCFG_EXTI_PORTG               7U /*!< EXTI PORT G                        */
-#endif /* GPIOG */
-#define LL_SYSCFG_EXTI_PORTH               5U /*!< EXTI PORT H                        */
-/**
-  * @}
-  */
-
-/** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE
-  * @{
-  */
-#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16U | 0U)  /* EXTI_POSITION_0 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16U | 0U)  /* EXTI_POSITION_4 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16U | 0U)  /* EXTI_POSITION_8 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16U | 0U)  /* EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16U | 1U)  /* EXTI_POSITION_0 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16U | 1U)  /* EXTI_POSITION_4 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16U | 1U)  /* EXTI_POSITION_8 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16U | 1U)  /* EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16U | 2U)  /* EXTI_POSITION_0 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16U | 2U)  /* EXTI_POSITION_4 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16U | 2U)  /* EXTI_POSITION_8 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16U | 2U)  /* EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16U | 3U)  /* EXTI_POSITION_0 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16U | 3U)  /* EXTI_POSITION_4 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16U | 3U)  /* EXTI_POSITION_8 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16U | 3U)  /* EXTI_POSITION_12 | EXTICR[3] */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
-  * @{
-  */
-#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP             /*!< TIM2 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP             /*!< TIM3 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP             /*!< TIM4 counter stopped when core is halted */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP             /*!< TIM5 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP             /*!< TIM6 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP             /*!< TIM7 counter stopped when core is halted */
-#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP              /*!< RTC Counter stopped when Core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP             /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP             /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP             /*!< TIM9 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP            /*!< TIM10 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP            /*!< TIM11 counter stopped when core is halted */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection
-  * @{
-  */
-#define LL_RI_TIM_SELECT_NONE              (0x00000000U)           /*!< No timer selected */
-#define LL_RI_TIM_SELECT_TIM2              RI_ICR_TIM_0            /*!< Timer 2 selected */
-#define LL_RI_TIM_SELECT_TIM3              RI_ICR_TIM_1            /*!< Timer 3 selected */
-#define LL_RI_TIM_SELECT_TIM4              RI_ICR_TIM              /*!< Timer 4 selected */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number
-  * @{
-  */
-#define LL_RI_INPUTCAPTURE_1               (RI_ICR_IC1 | RI_ICR_IC1OS) /*!< Input Capture 1 select output */
-#define LL_RI_INPUTCAPTURE_2               (RI_ICR_IC2 | RI_ICR_IC2OS) /*!< Input Capture 2 select output */
-#define LL_RI_INPUTCAPTURE_3               (RI_ICR_IC3 | RI_ICR_IC3OS) /*!< Input Capture 3 select output */
-#define LL_RI_INPUTCAPTURE_4               (RI_ICR_IC4 | RI_ICR_IC4OS) /*!< Input Capture 4 select output */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing
-  * @{
-  */
-                                                         /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4   */
-#define LL_RI_INPUTCAPTUREROUTING_0        (0x00000000U) /*!< PA0       PA1      PA2       PA3      */
-#define LL_RI_INPUTCAPTUREROUTING_1        (0x00000001U) /*!< PA4       PA5      PA6       PA7      */
-#define LL_RI_INPUTCAPTUREROUTING_2        (0x00000002U) /*!< PA8       PA9      PA10      PA11     */
-#define LL_RI_INPUTCAPTUREROUTING_3        (0x00000003U) /*!< PA12      PA13     PA14      PA15     */
-#define LL_RI_INPUTCAPTUREROUTING_4        (0x00000004U) /*!< PC0       PC1      PC2       PC3      */
-#define LL_RI_INPUTCAPTUREROUTING_5        (0x00000005U) /*!< PC4       PC5      PC6       PC7      */
-#define LL_RI_INPUTCAPTUREROUTING_6        (0x00000006U) /*!< PC8       PC9      PC10      PC11     */
-#define LL_RI_INPUTCAPTUREROUTING_7        (0x00000007U) /*!< PC12      PC13     PC14      PC15     */
-#define LL_RI_INPUTCAPTUREROUTING_8        (0x00000008U) /*!< PD0       PD1      PD2       PD3      */
-#define LL_RI_INPUTCAPTUREROUTING_9        (0x00000009U) /*!< PD4       PD5      PD6       PD7      */
-#define LL_RI_INPUTCAPTUREROUTING_10       (0x0000000AU) /*!< PD8       PD9      PD10      PD11     */
-#define LL_RI_INPUTCAPTUREROUTING_11       (0x0000000BU) /*!< PD12      PD13     PD14      PD15     */
-#if defined(GPIOE)
-#define LL_RI_INPUTCAPTUREROUTING_12       (0x0000000CU) /*!< PE0       PE1      PE2       PE3      */
-#define LL_RI_INPUTCAPTUREROUTING_13       (0x0000000DU) /*!< PE4       PE5      PE6       PE7      */
-#define LL_RI_INPUTCAPTUREROUTING_14       (0x0000000EU) /*!< PE8       PE9      PE10      PE11     */
-#define LL_RI_INPUTCAPTUREROUTING_15       (0x0000000FU) /*!< PE12      PE13     PE14      PE15     */
-#endif /* GPIOE */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC
-  * @{
-  */
-#define LL_RI_IOSWITCH_CH0                 RI_ASCR1_CH_0    /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH1                 RI_ASCR1_CH_1    /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH2                 RI_ASCR1_CH_2    /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH3                 RI_ASCR1_CH_3    /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH4                 RI_ASCR1_CH_4    /*!< CH4: Analog switch control     */
-#define LL_RI_IOSWITCH_CH5                 RI_ASCR1_CH_5    /*!< CH5: Comparator 1 analog switch*/
-#define LL_RI_IOSWITCH_CH6                 RI_ASCR1_CH_6    /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH7                 RI_ASCR1_CH_7    /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH8                 RI_ASCR1_CH_8    /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH9                 RI_ASCR1_CH_9    /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH10                RI_ASCR1_CH_10   /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH11                RI_ASCR1_CH_11   /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH12                RI_ASCR1_CH_12   /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH13                RI_ASCR1_CH_13   /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH14                RI_ASCR1_CH_14   /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH15                RI_ASCR1_CH_15   /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH18                RI_ASCR1_CH_18   /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH19                RI_ASCR1_CH_19   /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH20                RI_ASCR1_CH_20   /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH21                RI_ASCR1_CH_21   /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH22                RI_ASCR1_CH_22   /*!< Analog I/O switch control of channels CH22 */
-#define LL_RI_IOSWITCH_CH23                RI_ASCR1_CH_23   /*!< Analog I/O switch control of channels CH23  */
-#define LL_RI_IOSWITCH_CH24                RI_ASCR1_CH_24   /*!< Analog I/O switch control of channels CH24  */
-#define LL_RI_IOSWITCH_CH25                RI_ASCR1_CH_25   /*!< Analog I/O switch control of channels CH25  */
-#define LL_RI_IOSWITCH_VCOMP               RI_ASCR1_VCOMP   /*!< VCOMP (ADC channel 26) is an internal switch
-                                                                 used to connect selected channel to COMP1 non inverting input */
-#if defined(RI_ASCR1_CH_27)
-#define LL_RI_IOSWITCH_CH27                RI_ASCR1_CH_27   /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH28                RI_ASCR1_CH_28   /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH29                RI_ASCR1_CH_29   /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH30                RI_ASCR1_CH_30   /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
-#define LL_RI_IOSWITCH_CH31                RI_ASCR1_CH_31   /*!< CH31/GR11-5 I/O Analog switch control */
-#endif /* RI_ASCR1_CH_27 */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC
-  * @{
-  */
-#define LL_RI_IOSWITCH_GR10_1              RI_ASCR2_GR10_1 /*!< GR10-1 I/O analog switch control */
-#define LL_RI_IOSWITCH_GR10_2              RI_ASCR2_GR10_2 /*!< GR10-2 I/O analog switch control */
-#define LL_RI_IOSWITCH_GR10_3              RI_ASCR2_GR10_3 /*!< GR10-3 I/O analog switch control */
-#define LL_RI_IOSWITCH_GR10_4              RI_ASCR2_GR10_4 /*!< GR10-4 I/O analog switch control */
-#define LL_RI_IOSWITCH_GR6_1               RI_ASCR2_GR6_1  /*!< GR6-1 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR6_2               RI_ASCR2_GR6_2  /*!< GR6-2 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR5_1               RI_ASCR2_GR5_1  /*!< GR5-1 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR5_2               RI_ASCR2_GR5_2  /*!< GR5-2 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR5_3               RI_ASCR2_GR5_3  /*!< GR5-3 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR4_1               RI_ASCR2_GR4_1  /*!< GR4-1 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR4_2               RI_ASCR2_GR4_2  /*!< GR4-2 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR4_3               RI_ASCR2_GR4_3  /*!< GR4-3 I/O analog switch control  */
-#if defined(RI_ASCR2_CH0b)
-#define LL_RI_IOSWITCH_CH0b                RI_ASCR2_CH0b   /*!< CH0b-GR03-3 I/O analog switch control  */
-#if defined(RI_ASCR2_CH1b)
-#define LL_RI_IOSWITCH_CH1b                RI_ASCR2_CH1b   /*!< CH1b-GR03-4 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH2b                RI_ASCR2_CH2b   /*!< CH2b-GR03-5 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH3b                RI_ASCR2_CH3b   /*!< CH3b-GR09-3 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH6b                RI_ASCR2_CH6b   /*!< CH6b-GR09-4 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH7b                RI_ASCR2_CH7b   /*!< CH7b-GR02-3 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH8b                RI_ASCR2_CH8b   /*!< CH8b-GR02-4 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH9b                RI_ASCR2_CH9b   /*!< CH9b-GR02-5 I/O analog switch control  */
-#define LL_RI_IOSWITCH_CH10b               RI_ASCR2_CH10b  /*!< CH10b-GR07-5 I/O analog switch control */
-#define LL_RI_IOSWITCH_CH11b               RI_ASCR2_CH11b  /*!< CH11b-GR07-6 I/O analog switch control */
-#define LL_RI_IOSWITCH_CH12b               RI_ASCR2_CH12b  /*!< CH12b-GR07-7 I/O analog switch control */
-#endif /* RI_ASCR2_CH1b */
-#define LL_RI_IOSWITCH_GR6_3               RI_ASCR2_GR6_3  /*!< GR6-3 I/O analog switch control  */
-#define LL_RI_IOSWITCH_GR6_4               RI_ASCR2_GR6_4  /*!< GR6-4 I/O analog switch control  */
-#endif /* RI_ASCR2_CH0b */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT
-  * @{
-  */
-#define LL_RI_HSYTERESIS_PORT_A            0U         /*!< HYSTERESIS PORT A  */
-#define LL_RI_HSYTERESIS_PORT_B            1U         /*!< HYSTERESIS PORT B  */
-#define LL_RI_HSYTERESIS_PORT_C            2U         /*!< HYSTERESIS PORT C  */
-#define LL_RI_HSYTERESIS_PORT_D            3U         /*!< HYSTERESIS PORT D  */
-#if defined(GPIOE)
-#define LL_RI_HSYTERESIS_PORT_E            4U         /*!< HYSTERESIS PORT E  */
-#endif /* GPIOE */
-#if defined(GPIOF)
-#define LL_RI_HSYTERESIS_PORT_F            5U         /*!< HYSTERESIS PORT F  */
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_RI_HSYTERESIS_PORT_G            6U         /*!< HYSTERESIS PORT G  */
-#endif /* GPIOG */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_PIN RI PIN
-  * @{
-  */
-#define LL_RI_PIN_0                        ((uint16_t)0x0001U)  /*!< Pin 0 selected */
-#define LL_RI_PIN_1                        ((uint16_t)0x0002U)  /*!< Pin 1 selected */
-#define LL_RI_PIN_2                        ((uint16_t)0x0004U)  /*!< Pin 2 selected */
-#define LL_RI_PIN_3                        ((uint16_t)0x0008U)  /*!< Pin 3 selected */
-#define LL_RI_PIN_4                        ((uint16_t)0x0010U)  /*!< Pin 4 selected */
-#define LL_RI_PIN_5                        ((uint16_t)0x0020U)  /*!< Pin 5 selected */
-#define LL_RI_PIN_6                        ((uint16_t)0x0040U)  /*!< Pin 6 selected */
-#define LL_RI_PIN_7                        ((uint16_t)0x0080U)  /*!< Pin 7 selected */
-#define LL_RI_PIN_8                        ((uint16_t)0x0100U)  /*!< Pin 8 selected */
-#define LL_RI_PIN_9                        ((uint16_t)0x0200U)  /*!< Pin 9 selected */
-#define LL_RI_PIN_10                       ((uint16_t)0x0400U)  /*!< Pin 10 selected */
-#define LL_RI_PIN_11                       ((uint16_t)0x0800U)  /*!< Pin 11 selected */
-#define LL_RI_PIN_12                       ((uint16_t)0x1000U)  /*!< Pin 12 selected */
-#define LL_RI_PIN_13                       ((uint16_t)0x2000U)  /*!< Pin 13 selected */
-#define LL_RI_PIN_14                       ((uint16_t)0x4000U)  /*!< Pin 14 selected */
-#define LL_RI_PIN_15                       ((uint16_t)0x8000U)  /*!< Pin 15 selected */
-#define LL_RI_PIN_ALL                      ((uint16_t)0xFFFFU)  /*!< All pins selected */
-/**
-  * @}
-  */
-
-#if defined(RI_ASMR1_PA)
-/** @defgroup SYSTEM_LL_EC_PORT RI PORT
-  * @{
-  */
-#define LL_RI_PORT_A                       0U         /*!< PORT A   */
-#define LL_RI_PORT_B                       1U         /*!< PORT B   */
-#define LL_RI_PORT_C                       2U         /*!< PORT C   */
-#if defined(GPIOF)
-#define LL_RI_PORT_F                       3U         /*!< PORT F   */
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_RI_PORT_G                       4U         /*!< PORT G   */
-#endif /* GPIOG */
-/**
-  * @}
-  */
-
-#endif /* RI_ASMR1_PA */
-
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
-  * @{
-  */
-#define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
-#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
-  * @{
-  */
-
-/**
-  * @brief  Set memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
-  * @param  Memory This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
-{
-  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
-}
-
-/**
-  * @brief  Get memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
-}
-
-/**
-  * @brief  Return the boot mode as configured by user.
-  * @rmtoll SYSCFG_MEMRMP BOOT_MODE     LL_SYSCFG_GetBootMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BOOTMODE_FLASH
-  *         @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*)
-  *         @arg @ref LL_SYSCFG_BOOTMODE_SRAM
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE));
-}
-
-/**
-  * @brief  Enable internal pull-up on USB DP line.
-  * @rmtoll SYSCFG_PMC   USB_PU        LL_SYSCFG_EnableUSBPullUp
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void)
-{
-  SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
-}
-
-/**
-  * @brief  Disable internal pull-up on USB DP line.
-  * @rmtoll SYSCFG_PMC   USB_PU        LL_SYSCFG_DisableUSBPullUp
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void)
-{
-  CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
-}
-
-#if defined(LCD)
-/**
-  * @brief  Enable decoupling capacitance connection.
-  * @rmtoll SYSCFG_PMC   LCD_CAPA      LL_SYSCFG_EnableLCDCapacitanceConnection
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB2
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB12
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB0
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PE11
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PE12
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin)
-{
-  SET_BIT(SYSCFG->PMC, Pin);
-}
-
-/**
-  * @brief  DIsable decoupling capacitance connection.
-  * @rmtoll SYSCFG_PMC   LCD_CAPA      LL_SYSCFG_DisableLCDCapacitanceConnection
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB2
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB12
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PB0
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PE11
-  *         @arg @ref LL_SYSCFG_LCDCAPA_PE12
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin)
-{
-  CLEAR_BIT(SYSCFG->PMC, Pin);
-}
-#endif /* LCD */
-
-/**
-  * @brief  Configure source input for the EXTI external interrupt.
-  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI15        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI15        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI15        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI0         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI1         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI2         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI3         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI4         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI5         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI6         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI7         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI8         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI9         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI10        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI11        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *
-  *         (*) value not defined in all devices.
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
-  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
-}
-
-/**
-  * @brief  Get the configured defined for specific EXTI Line
-  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI4         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI5         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI6         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI7         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI8         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI9         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI10        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI11        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI12        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI13        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI14        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR1 EXTI15        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI0         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI1         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI2         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI3         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI8         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI9         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI10        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI11        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI12        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI13        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI14        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTI15        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI0         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI1         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI2         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI3         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI4         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI5         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI6         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI7         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI12        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI13        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI14        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTI15        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI0         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI1         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI2         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI3         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI4         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI5         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI6         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI7         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI8         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI9         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI10        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI11        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_GetEXTISource
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16)) >> POSITION_VAL(Line >> 16));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
-  * @{
-  */
-
-/**
-  * @brief  Return the device identifier
-  * @note 0x416: Cat.1 device\n
-  *       0x429: Cat.2 device\n
-  *       0x427: Cat.3 device\n
-  *       0x436: Cat.4 device or Cat.3 device(1)\n
-  *       0x437: Cat.5 device\n
-  *
-  *       (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with
-  *       RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin.
-  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
-  * @brief  Return the device revision identifier
-  * @note This field indicates the revision of the device.
-          For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018...
-  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Set Trace pin assignment control
-  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
-  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
-  * @param  PinAssignment This parameter can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRACE_NONE
-  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
-  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
-  * @brief  Get Trace pin assignment control
-  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
-  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRACE_NONE
-  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
-  * @brief  Freeze APB1 peripherals (group1 peripherals)
-  * @rmtoll APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
-  * @rmtoll APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Freeze APB2 peripherals
-  * @rmtoll APB2_FZ      DBG_TIM9_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         APB2_FZ      DBG_TIM10_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         APB2_FZ      DBG_TIM11_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB2 peripherals
-  * @rmtoll APB2_FZ      DBG_TIM9_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         APB2_FZ      DBG_TIM10_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         APB2_FZ      DBG_TIM11_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
-  * @}
-  */
-
-#if defined(COMP_CSR_VREFOUTEN)
-/** @defgroup SYSTEM_LL_EF_VREFOUT VREFOUT
-  * @{
-  */
-
-/**
-  * @brief  Enable the output of internal reference voltage (VrefInt) on I/O pin.
-  * @note   The VrefInt output can be routed to any I/O in group 3:
-  *          - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
-  *          - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
-  *          - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
-  *            CH1b (PF11) or CH2b (PF12).
-  *         Note: Comparator peripheral clock must be preliminarily enabled.
-  *               Refer to function "LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_COMP)".
-  *         Note: In addition with this macro, VrefInt output buffer must be
-  *               connected to the selected I/O pin. Refer to functions
-  *               "LL_RI_EnableSwitchControlMode()" and "LL_RI_CloseIOSwitchLinkedToADC()".
-  * @note  VrefInt output enable: Internal reference voltage connected to I/O group 3
-  *        VrefInt output disable: Internal reference voltage disconnected from I/O group 3
-  * @rmtoll COMP_CSR     VREFOUTEN     LL_VREFOUT_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFOUT_Enable(void)
-{
-  SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN);
-}
-
-/**
-  * @brief  Disable the output of internal reference voltage (VrefInt) on I/O pin.
-  * @rmtoll COMP_CSR     VREFOUTEN     LL_VREFOUT_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFOUT_Disable(void)
-{
-  CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN);
-}
-
-/**
-  * @brief  Check if output of internal reference voltage (VrefInt) is connected to I/O pin.
-  * @rmtoll COMP_CSR     VREFOUTEN     LL_VREFOUT_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_VREFOUT_IsEnabled(void)
-{
-  return ((READ_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) == COMP_CSR_VREFOUTEN) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-#endif /* COMP_CSR_VREFOUTEN */
-
-/** @defgroup SYSTEM_LL_EF_RI RI
-  * @{
-  */
-
-/**
-  * @brief  Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin.
-  * @rmtoll RI_ICR       IC1OS         LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC2OS         LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC3OS         LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC4OS         LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       TIM           LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC1           LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC2           LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC3           LL_RI_SetRemapInputCapture_TIM\n
-  *         RI_ICR       IC4           LL_RI_SetRemapInputCapture_TIM
-  * @param  TIM_Select This parameter can be one of the following values:
-  *         @arg @ref LL_RI_TIM_SELECT_NONE
-  *         @arg @ref LL_RI_TIM_SELECT_TIM2
-  *         @arg @ref LL_RI_TIM_SELECT_TIM3
-  *         @arg @ref LL_RI_TIM_SELECT_TIM4
-  * @param  InputCaptureChannel This parameter can be one of the following values:
-  *         @arg @ref LL_RI_INPUTCAPTURE_1
-  *         @arg @ref LL_RI_INPUTCAPTURE_2
-  *         @arg @ref LL_RI_INPUTCAPTURE_3
-  *         @arg @ref LL_RI_INPUTCAPTURE_4
-  * @param  Input This parameter can be one of the following values:
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_0
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_1
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_2
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_3
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_4
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_5
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_6
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_7
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_8
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_9
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_10
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_11
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*)
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*)
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*)
-  *         @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input)
-{
-  MODIFY_REG(RI->ICR,
-             RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)),
-             TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel)));
-}
-
-/**
-  * @brief  Disable the TIM Input capture remap (select the standard AF)
-  * @rmtoll RI_ICR       IC1           LL_RI_DisableRemapInputCapture_TIM\n
-  *         RI_ICR       IC2           LL_RI_DisableRemapInputCapture_TIM\n
-  *         RI_ICR       IC3           LL_RI_DisableRemapInputCapture_TIM\n
-  *         RI_ICR       IC4           LL_RI_DisableRemapInputCapture_TIM
-  * @param  InputCaptureChannel This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_INPUTCAPTURE_1
-  *         @arg @ref LL_RI_INPUTCAPTURE_2
-  *         @arg @ref LL_RI_INPUTCAPTURE_3
-  *         @arg @ref LL_RI_INPUTCAPTURE_4
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel)
-{
-  CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)));
-}
-
-/**
-  * @brief  Close the routing interface Input Output switches linked to ADC.
-  * @rmtoll RI_ASCR1     CH            LL_RI_CloseIOSwitchLinkedToADC\n
-  *         RI_ASCR1     VCOMP         LL_RI_CloseIOSwitchLinkedToADC
-  * @param  IOSwitch This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_IOSWITCH_CH0
-  *         @arg @ref LL_RI_IOSWITCH_CH1
-  *         @arg @ref LL_RI_IOSWITCH_CH2
-  *         @arg @ref LL_RI_IOSWITCH_CH3
-  *         @arg @ref LL_RI_IOSWITCH_CH4
-  *         @arg @ref LL_RI_IOSWITCH_CH5
-  *         @arg @ref LL_RI_IOSWITCH_CH6
-  *         @arg @ref LL_RI_IOSWITCH_CH7
-  *         @arg @ref LL_RI_IOSWITCH_CH8
-  *         @arg @ref LL_RI_IOSWITCH_CH9
-  *         @arg @ref LL_RI_IOSWITCH_CH10
-  *         @arg @ref LL_RI_IOSWITCH_CH11
-  *         @arg @ref LL_RI_IOSWITCH_CH12
-  *         @arg @ref LL_RI_IOSWITCH_CH13
-  *         @arg @ref LL_RI_IOSWITCH_CH14
-  *         @arg @ref LL_RI_IOSWITCH_CH15
-  *         @arg @ref LL_RI_IOSWITCH_CH18
-  *         @arg @ref LL_RI_IOSWITCH_CH19
-  *         @arg @ref LL_RI_IOSWITCH_CH20
-  *         @arg @ref LL_RI_IOSWITCH_CH21
-  *         @arg @ref LL_RI_IOSWITCH_CH22
-  *         @arg @ref LL_RI_IOSWITCH_CH23
-  *         @arg @ref LL_RI_IOSWITCH_CH24
-  *         @arg @ref LL_RI_IOSWITCH_CH25
-  *         @arg @ref LL_RI_IOSWITCH_VCOMP
-  *         @arg @ref LL_RI_IOSWITCH_CH27 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH28 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH29 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH30 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch)
-{
-  SET_BIT(RI->ASCR1, IOSwitch);
-}
-
-/**
-  * @brief  Open the routing interface Input Output switches linked to ADC.
-  * @rmtoll RI_ASCR1     CH            LL_RI_OpenIOSwitchLinkedToADC\n
-  *         RI_ASCR1     VCOMP         LL_RI_OpenIOSwitchLinkedToADC
-  * @param  IOSwitch This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_IOSWITCH_CH0
-  *         @arg @ref LL_RI_IOSWITCH_CH1
-  *         @arg @ref LL_RI_IOSWITCH_CH2
-  *         @arg @ref LL_RI_IOSWITCH_CH3
-  *         @arg @ref LL_RI_IOSWITCH_CH4
-  *         @arg @ref LL_RI_IOSWITCH_CH5
-  *         @arg @ref LL_RI_IOSWITCH_CH6
-  *         @arg @ref LL_RI_IOSWITCH_CH7
-  *         @arg @ref LL_RI_IOSWITCH_CH8
-  *         @arg @ref LL_RI_IOSWITCH_CH9
-  *         @arg @ref LL_RI_IOSWITCH_CH10
-  *         @arg @ref LL_RI_IOSWITCH_CH11
-  *         @arg @ref LL_RI_IOSWITCH_CH12
-  *         @arg @ref LL_RI_IOSWITCH_CH13
-  *         @arg @ref LL_RI_IOSWITCH_CH14
-  *         @arg @ref LL_RI_IOSWITCH_CH15
-  *         @arg @ref LL_RI_IOSWITCH_CH18
-  *         @arg @ref LL_RI_IOSWITCH_CH19
-  *         @arg @ref LL_RI_IOSWITCH_CH20
-  *         @arg @ref LL_RI_IOSWITCH_CH21
-  *         @arg @ref LL_RI_IOSWITCH_CH22
-  *         @arg @ref LL_RI_IOSWITCH_CH23
-  *         @arg @ref LL_RI_IOSWITCH_CH24
-  *         @arg @ref LL_RI_IOSWITCH_CH25
-  *         @arg @ref LL_RI_IOSWITCH_VCOMP
-  *         @arg @ref LL_RI_IOSWITCH_CH27 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH28 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH29 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH30 (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch)
-{
-  CLEAR_BIT(RI->ASCR1, IOSwitch);
-}
-
-/**
-  * @brief  Enable the switch control mode.
-  * @rmtoll RI_ASCR1     SCM           LL_RI_EnableSwitchControlMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_EnableSwitchControlMode(void)
-{
-  SET_BIT(RI->ASCR1, RI_ASCR1_SCM);
-}
-
-/**
-  * @brief  Disable the switch control mode.
-  * @rmtoll RI_ASCR1     SCM           LL_RI_DisableSwitchControlMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_DisableSwitchControlMode(void)
-{
-  CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM);
-}
-
-/**
-  * @brief  Close the routing interface Input Output switches not linked to ADC.
-  * @rmtoll RI_ASCR2     GR10_1        LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_2        LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_3        LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_4        LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_1         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_2         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_1         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_2         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_3         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_1         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_2         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_3         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_4         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH0b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH1b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH2b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH3b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH6b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH7b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH8b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH9b          LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH10b         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH11b         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH12b         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_3         LL_RI_CloseIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_4         LL_RI_CloseIOSwitchNotLinkedToADC
-  * @param  IOSwitch This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_IOSWITCH_GR10_1
-  *         @arg @ref LL_RI_IOSWITCH_GR10_2
-  *         @arg @ref LL_RI_IOSWITCH_GR10_3
-  *         @arg @ref LL_RI_IOSWITCH_GR10_4
-  *         @arg @ref LL_RI_IOSWITCH_GR6_1
-  *         @arg @ref LL_RI_IOSWITCH_GR6_2
-  *         @arg @ref LL_RI_IOSWITCH_GR5_1
-  *         @arg @ref LL_RI_IOSWITCH_GR5_2
-  *         @arg @ref LL_RI_IOSWITCH_GR5_3
-  *         @arg @ref LL_RI_IOSWITCH_GR4_1
-  *         @arg @ref LL_RI_IOSWITCH_GR4_2
-  *         @arg @ref LL_RI_IOSWITCH_GR4_3
-  *         @arg @ref LL_RI_IOSWITCH_CH0b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH1b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH2b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH3b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH6b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH7b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH8b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH9b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH10b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH11b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH12b (*)
-  *         @arg @ref LL_RI_IOSWITCH_GR6_3
-  *         @arg @ref LL_RI_IOSWITCH_GR6_4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch)
-{
-  SET_BIT(RI->ASCR2, IOSwitch);
-}
-
-/**
-  * @brief  Open the routing interface Input Output switches not linked to ADC.
-  * @rmtoll RI_ASCR2     GR10_1        LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_2        LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_3        LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR10_4        LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_1         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_2         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_1         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_2         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR5_3         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_1         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_2         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_3         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR4_4         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH0b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH1b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH2b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH3b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH6b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH7b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH8b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH9b          LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH10b         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH11b         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     CH12b         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_3         LL_RI_OpenIOSwitchNotLinkedToADC\n
-  *         RI_ASCR2     GR6_4         LL_RI_OpenIOSwitchNotLinkedToADC
-  * @param  IOSwitch This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_IOSWITCH_GR10_1
-  *         @arg @ref LL_RI_IOSWITCH_GR10_2
-  *         @arg @ref LL_RI_IOSWITCH_GR10_3
-  *         @arg @ref LL_RI_IOSWITCH_GR10_4
-  *         @arg @ref LL_RI_IOSWITCH_GR6_1
-  *         @arg @ref LL_RI_IOSWITCH_GR6_2
-  *         @arg @ref LL_RI_IOSWITCH_GR5_1
-  *         @arg @ref LL_RI_IOSWITCH_GR5_2
-  *         @arg @ref LL_RI_IOSWITCH_GR5_3
-  *         @arg @ref LL_RI_IOSWITCH_GR4_1
-  *         @arg @ref LL_RI_IOSWITCH_GR4_2
-  *         @arg @ref LL_RI_IOSWITCH_GR4_3
-  *         @arg @ref LL_RI_IOSWITCH_CH0b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH1b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH2b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH3b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH6b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH7b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH8b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH9b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH10b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH11b (*)
-  *         @arg @ref LL_RI_IOSWITCH_CH12b (*)
-  *         @arg @ref LL_RI_IOSWITCH_GR6_3
-  *         @arg @ref LL_RI_IOSWITCH_GR6_4
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch)
-{
-  CLEAR_BIT(RI->ASCR2, IOSwitch);
-}
-
-/**
-  * @brief  Enable Hysteresis of the input schmitt triger of the port X
-  * @rmtoll RI_HYSCR1    PA            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PB            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PC            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PD            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PE            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PF            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR1    PG            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PA            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PB            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PC            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PD            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PE            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PF            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR2    PG            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PA            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PB            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PC            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PD            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PE            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PF            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR3    PG            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PA            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PB            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PC            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PD            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PE            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PF            LL_RI_EnableHysteresis\n
-  *         RI_HYSCR4    PG            LL_RI_EnableHysteresis
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_A
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_B
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_C
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_D
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1U));
-  CLEAR_BIT(*reg, Pin << (16U * (Port & 1U)));
-}
-
-/**
-  * @brief  Disable Hysteresis of the input schmitt triger of the port X
-  * @rmtoll RI_HYSCR1    PA            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PB            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PC            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PD            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PE            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PF            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR1    PG            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PA            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PB            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PC            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PD            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PE            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PF            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR2    PG            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PA            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PB            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PC            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PD            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PE            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PF            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR3    PG            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PA            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PB            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PC            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PD            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PE            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PF            LL_RI_DisableHysteresis\n
-  *         RI_HYSCR4    PG            LL_RI_DisableHysteresis
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_A
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_B
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_C
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_D
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
-  *         @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1U) << 2U));
-  SET_BIT(*reg, Pin << (16U * (Port & 1U)));
-}
-
-#if defined(RI_ASMR1_PA)
-/**
-  * @brief  Control analog switches of port X through the ADC interface or RI_ASCRx registers.
-  * @rmtoll RI_ASMR1     PA            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR1     PB            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR1     PC            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR1     PF            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR1     PG            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR2     PA            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR2     PB            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR2     PC            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR2     PF            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR2     PG            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR3     PA            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR3     PB            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR3     PC            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR3     PF            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR3     PG            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR4     PA            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR4     PB            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR4     PC            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR4     PF            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR4     PG            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR5     PA            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR5     PB            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR5     PC            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR5     PF            LL_RI_ControlSwitchByADC\n
-  *         RI_ASMR5     PG            LL_RI_ControlSwitchByADC
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
-  CLEAR_BIT(*reg, Pin);
-}
-#endif /* RI_ASMR1_PA */
-
-#if defined(RI_ASMR1_PA)
-/**
-  * @brief  Control analog switches of port X by the timer OC.
-  * @rmtoll RI_ASMR1     PA            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR1     PB            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR1     PC            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR1     PF            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR1     PG            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR2     PA            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR2     PB            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR2     PC            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR2     PF            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR2     PG            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR3     PA            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR3     PB            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR3     PC            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR3     PF            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR3     PG            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR4     PA            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR4     PB            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR4     PC            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR4     PF            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR4     PG            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR5     PA            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR5     PB            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR5     PC            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR5     PF            LL_RI_ControlSwitchByTIM\n
-  *         RI_ASMR5     PG            LL_RI_ControlSwitchByTIM
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
-  SET_BIT(*reg, Pin);
-}
-#endif /* RI_ASMR1_PA */
-
-#if defined(RI_CMR1_PA)
-/**
-  * @brief  Mask the input of port X during the capacitive sensing acquisition.
-  * @rmtoll RI_CMR1      PA            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR1      PB            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR1      PC            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR1      PF            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR1      PG            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR2      PA            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR2      PB            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR2      PC            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR2      PF            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR2      PG            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR3      PA            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR3      PB            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR3      PC            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR3      PF            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR3      PG            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR4      PA            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR4      PB            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR4      PC            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR4      PF            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR4      PG            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR5      PA            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR5      PB            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR5      PC            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR5      PF            LL_RI_MaskChannelDuringAcquisition\n
-  *         RI_CMR5      PG            LL_RI_MaskChannelDuringAcquisition
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
-  CLEAR_BIT(*reg, Pin);
-}
-#endif /* RI_CMR1_PA */
-
-#if defined(RI_CMR1_PA)
-/**
-  * @brief  Unmask the input of port X during the capacitive sensing acquisition.
-  * @rmtoll RI_CMR1      PA            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR1      PB            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR1      PC            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR1      PF            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR1      PG            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR2      PA            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR2      PB            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR2      PC            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR2      PF            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR2      PG            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR3      PA            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR3      PB            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR3      PC            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR3      PF            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR3      PG            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR4      PA            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR4      PB            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR4      PC            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR4      PF            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR4      PG            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR5      PA            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR5      PB            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR5      PC            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR5      PF            LL_RI_UnmaskChannelDuringAcquisition\n
-  *         RI_CMR5      PG            LL_RI_UnmaskChannelDuringAcquisition
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
-  SET_BIT(*reg, Pin);
-}
-#endif /* RI_CMR1_PA */
-
-#if defined(RI_CICR1_PA)
-/**
-  * @brief  Identify channel for timer input capture
-  * @rmtoll RI_CICR1     PA            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR1     PB            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR1     PC            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR1     PF            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR1     PG            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR2     PA            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR2     PB            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR2     PC            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR2     PF            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR2     PG            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR3     PA            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR3     PB            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR3     PC            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR3     PF            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR3     PG            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR4     PA            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR4     PB            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR4     PC            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR4     PF            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR4     PG            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR5     PA            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR5     PB            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR5     PC            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR5     PF            LL_RI_IdentifyChannelIO\n
-  *         RI_CICR5     PG            LL_RI_IdentifyChannelIO
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
-  CLEAR_BIT(*reg, Pin);
-}
-#endif /* RI_CICR1_PA */
-
-#if defined(RI_CICR1_PA)
-/**
-  * @brief  Identify sampling capacitor for timer input capture
-  * @rmtoll RI_CICR1     PA            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR1     PB            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR1     PC            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR1     PF            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR1     PG            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR2     PA            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR2     PB            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR2     PC            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR2     PF            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR2     PG            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR3     PA            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR3     PB            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR3     PC            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR3     PF            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR3     PG            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR4     PA            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR4     PB            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR4     PC            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR4     PF            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR4     PG            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR5     PA            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR5     PB            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR5     PC            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR5     PF            LL_RI_IdentifySamplingCapacitorIO\n
-  *         RI_CICR5     PG            LL_RI_IdentifySamplingCapacitorIO
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_RI_PORT_A
-  *         @arg @ref LL_RI_PORT_B
-  *         @arg @ref LL_RI_PORT_C
-  *         @arg @ref LL_RI_PORT_F (*)
-  *         @arg @ref LL_RI_PORT_G (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  Pin This parameter can be a combination of the following values:
-  *         @arg @ref LL_RI_PIN_0
-  *         @arg @ref LL_RI_PIN_1
-  *         @arg @ref LL_RI_PIN_2
-  *         @arg @ref LL_RI_PIN_3
-  *         @arg @ref LL_RI_PIN_4
-  *         @arg @ref LL_RI_PIN_5
-  *         @arg @ref LL_RI_PIN_6
-  *         @arg @ref LL_RI_PIN_7
-  *         @arg @ref LL_RI_PIN_8
-  *         @arg @ref LL_RI_PIN_9
-  *         @arg @ref LL_RI_PIN_10
-  *         @arg @ref LL_RI_PIN_11
-  *         @arg @ref LL_RI_PIN_12
-  *         @arg @ref LL_RI_PIN_13
-  *         @arg @ref LL_RI_PIN_14
-  *         @arg @ref LL_RI_PIN_15
-  *         @arg @ref LL_RI_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin)
-{
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
-  SET_BIT(*reg, Pin);
-}
-#endif /* RI_CICR1_PA */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
-  * @{
-  */
-
-/**
-  * @brief  Set FLASH Latency
-  * @note   Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
-  * @param  Latency This parameter can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
-  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
-  * @brief  Get FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
-  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
-  * @brief  Enable Prefetch
-  * @note   Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Disable Prefetch
-  * @note   Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Check if Prefetch buffer is enabled
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
-  return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == FLASH_ACR_PRFTEN) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable 64-bit access
-  * @rmtoll FLASH_ACR    ACC64         LL_FLASH_Enable64bitAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_Enable64bitAccess(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_ACC64);
-}
-
-/**
-  * @brief  Disable 64-bit access
-  * @rmtoll FLASH_ACR    ACC64         LL_FLASH_Disable64bitAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_Disable64bitAccess(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64);
-}
-
-/**
-  * @brief  Check if 64-bit access is enabled
-  * @rmtoll FLASH_ACR    ACC64         LL_FLASH_Is64bitAccessEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void)
-{
-  return ((READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == FLASH_ACR_ACC64) ? 1UL : 0UL);
-}
-
-
-/**
-  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
-  * @note Flash memory can be put in power-down mode only when the code is executed
-  *       from RAM
-  * @note Flash must not be accessed when power down is enabled
-  * @note Flash must not be put in power-down while a program or an erase operation
-  *       is on-going
-  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
-{
-  /* Following values must be written consecutively to unlock the RUN_PD bit in
-     FLASH_ACR */
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
-  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
-  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
-  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
-{
-  /* Following values must be written consecutively to unlock the RUN_PD bit in
-     FLASH_ACR */
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
-  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
-}
-
-/**
-  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
-  * @note Flash must not be put in power-down while a program or an erase operation
-  *       is on-going
-  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
-  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h
deleted file mode 100644
index bdb1af6e273..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h
+++ /dev/null
@@ -1,3352 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_TIM_H
-#define __STM32L1xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
-
-/** @defgroup TIM_LL TIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
-  * @{
-  */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
-  0x00U,   /* 0: TIMx_CH1  */
-  0x00U,   /* 1: NA */
-  0x00U,   /* 2: TIMx_CH2  */
-  0x00U,   /* 3: NA */
-  0x04U,   /* 4: TIMx_CH3  */
-  0x00U,   /* 5: NA */
-  0x04U    /* 6: TIMx_CH4  */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
-  0U,            /* 0: OC1M, OC1FE, OC1PE */
-  0U,            /* 1: - NA */
-  8U,            /* 2: OC2M, OC2FE, OC2PE */
-  0U,            /* 3: - NA */
-  0U,            /* 4: OC3M, OC3FE, OC3PE */
-  0U,            /* 5: - NA */
-  8U             /* 6: OC4M, OC4FE, OC4PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
-  0U,            /* 0: CC1S, IC1PSC, IC1F */
-  0U,            /* 1: - NA */
-  8U,            /* 2: CC2S, IC2PSC, IC2F */
-  0U,            /* 3: - NA */
-  0U,            /* 4: CC3S, IC3PSC, IC3F */
-  0U,            /* 5: - NA */
-  8U             /* 6: CC4S, IC4PSC, IC4F */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
-  0U,            /* 0: CC1P */
-  0U,            /* 1: NA */
-  4U,            /* 2: CC2P */
-  0U,            /* 3: NA */
-  8U,            /* 4: CC3P */
-  0U,            /* 5: NA */
-  12U            /* 6: CC4P */
-};
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
-  * @{
-  */
-
-
-#define TIMx_OR_RMP_SHIFT  16U
-#define TIMx_OR_RMP_MASK   0x0000FFFFU
-#define TIM_OR_RMP_MASK    ((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
-#define TIM9_OR_RMP_MASK   ((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
-#define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
-#define TIM3_OR_RMP_MASK   (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
-
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
-  * @{
-  */
-/** @brief  Convert channel id into channel index.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval none
-  */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
-
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  TIM Time Base configuration structure definition.
-  */
-typedef struct
-{
-  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetPrescaler().*/
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetCounterMode().*/
-
-  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must
-                                   be a number between 0x0000 and 0xFFFFFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetAutoReload().*/
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetClockDivision().*/
-} LL_TIM_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the output mode.
-                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetMode().*/
-
-  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                               This feature can be modified afterwards using unitary function
-                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-
-} LL_TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture configuration structure definition.
-  */
-
-typedef struct
-{
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t ICActiveInput; /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
-  * @brief  TIM Encoder interface configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
-                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_SetEncoderMode().*/
-
-  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
-  * @{
-  */
-#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
-#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
-  * @{
-  */
-#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
-  * @{
-  */
-#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
-  * @{
-  */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
-  * @{
-  */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
-  * @{
-  */
-#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
-  * @{
-  */
-#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
-  * @{
-  */
-#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
-  * @{
-  */
-#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
-  * @{
-  */
-#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
-  * @{
-  */
-#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
-  * @{
-  */
-#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
-/**
-  * @}
-  */
-
-
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
-  * @{
-  */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
-  * @{
-  */
-#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
-  * @{
-  */
-#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
-  * @{
-  */
-#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
-  * @{
-  */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
-  * @{
-  */
-#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
-  * @{
-  */
-#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
-  * @{
-  */
-#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
-  * @{
-  */
-#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
-  * @{
-  */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
-  * @{
-  */
-#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
-  * @{
-  */
-#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-
-
-
-
-
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
-  * @{
-  */
-#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR register is the DMA base address for DMA burst */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
-  * @{
-  */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM10_TI1_RMP  TIM10 input 1 remapping capability
-  * @{
-  */
-#define LL_TIM_TIM10_TI1_RMP_GPIO   TIM_OR_RMP_MASK                                         /*!< TIM10 channel1 is connected to GPIO */
-#define LL_TIM_TIM10_TI1_RMP_LSI    (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSI internal clock */
-#define LL_TIM_TIM10_TI1_RMP_LSE    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSE internal clock */
-#define LL_TIM_TIM10_TI1_RMP_RTC    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)   /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM10_ETR_RMP  TIM10 ETR remap
-  * @{
-  */
-#define LL_TIM_TIM10_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM10 ETR input is connected to LSE */
-#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM10 ETR input is connected to TIM9 TGO */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
-  * @{
-  */
-#define LL_TIM_TIM10_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
-#define LL_TIM_TIM10_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM10 channel1 is connected to RI */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM11_TI1_RMP  TIM11 input 1 remapping capability
-  * @{
-  */
-#define LL_TIM_TIM11_TI1_RMP_GPIO       TIM_OR_RMP_MASK                                       /*!< TIM11 channel1 is connected to GPIO */
-#define LL_TIM_TIM11_TI1_RMP_MSI        (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to MSI internal clock */
-#define LL_TIM_TIM11_TI1_RMP_HSE_RTC    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to HSE RTC clock */
-#define LL_TIM_TIM11_TI1_RMP_GPIO1      (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM11_ETR_RMP  TIM11 ETR remap
-  * @{
-  */
-#define LL_TIM_TIM11_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM11 ETR input is connected to LSE */
-#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM11 ETR input is connected to TIM9 TGO clock */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
-  * @{
-  */
-#define LL_TIM_TIM11_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
-#define LL_TIM_TIM11_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to RI */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
-  * @{
-  */
-#define LL_TIM_TIM9_TI1_RMP_GPIO     TIM9_OR_RMP_MASK                                          /*!< TIM9 channel1 is connected to GPIO */
-#define LL_TIM_TIM9_TI1_RMP_LSE      (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to LSE internal clock */
-#define LL_TIM_TIM9_TI1_RMP_GPIO1    (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to GPIO */
-#define LL_TIM_TIM9_TI1_RMP_GPIO2    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)    /*!< TIM9 channel1 is connected to GPIO */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP  TIM9 ITR1 remap
-  * @{
-  */
-#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO   TIM9_OR_RMP_MASK                                     /*!< TIM9 channel1 is connected to TIM3 TGO signal */
-#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO   (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM9 channel1 is connected to touch sensing I/O */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP  TIM2 internal trigger 1 remap
-  * @{
-  */
-#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC    TIM9_OR_RMP_MASK                                     /*!< TIM2 ITR1 input is connected to TIM10 OC*/
-#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO    (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM2 ITR1 input is connected to TIM5 TGO */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP  TIM3 internal trigger 2 remap
-  * @{
-  */
-#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC    TIM9_OR_RMP_MASK                                     /*!< TIM3 ITR2 input is connected to TIM11 OC */
-#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO    (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK)                /*!< TIM3 ITR2 input is connected to TIM5 TGO */
-/**
-  * @}
-  */
-
-
-/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
-  * @{
-  */
-#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
-#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-/**
-  * @brief  Write a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
-  * @{
-  */
-
-/**
-  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
-  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CNTCLK__ counter clock frequency (in Hz)
-  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
-  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __FREQ__ output signal frequency (in Hz)
-  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
-  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
-  *         active/inactive delay.
-  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
-  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
-              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
-  *         (when the timer operates in one pulse mode).
-  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @param  __PULSE__ pulse duration (in us)
-  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
-  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
-              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
-  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
-  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
-  * @param  __ICPSC__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
-  */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
-  * @{
-  */
-/**
-  * @brief  Enable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Disable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Indicates whether the timer counter is enabled.
-  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Disable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Indicates whether update event generation is enabled.
-  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval Inverted state of bit (0 or 1).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set update event source
-  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
-  *       generate an update interrupt or DMA request if enabled:
-  *        - Counter overflow/underflow
-  *        - Setting the UG bit
-  *        - Update generation through the slave mode controller
-  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
-  *       overflow/underflow generates an update interrupt or DMA request if enabled.
-  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
-  * @param  TIMx Timer instance
-  * @param  UpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
-  * @brief  Get actual event update source
-  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
-  * @brief  Set one pulse mode (one shot v.s. repetitive).
-  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
-  * @param  TIMx Timer instance
-  * @param  OnePulseMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
-  * @brief  Get actual one pulse mode.
-  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
-  * @brief  Set the timer counter counting mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *       requires a timer reset to avoid unexpected direction
-  *       due to DIR bit readonly in center aligned mode.
-  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
-  *         CR1          CMS           LL_TIM_SetCounterMode
-  * @param  TIMx Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
-  * @brief  Get actual counter mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
-  *         CR1          CMS           LL_TIM_GetCounterMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
-  uint32_t counter_mode;
-
-  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
-  if (counter_mode == 0U)
-  {
-    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-  }
-
-  return counter_mode;
-}
-
-/**
-  * @brief  Enable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Disable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
-  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
-  *         (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
-  * @param  TIMx Timer instance
-  * @param  ClockDivision This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
-  *         generators (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
-  * @brief  Set the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_SetCounter
-  * @param  TIMx Timer instance
-  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
-  WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
-  * @brief  Get the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_GetCounter
-  * @param  TIMx Timer instance
-  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
-  * @brief  Get the current direction of the counter
-  * @rmtoll CR1          DIR           LL_TIM_GetDirection
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
-  * @brief  Set the prescaler value.
-  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
-  * @note The prescaler can be changed on the fly as this control register is buffered. The new
-  *       prescaler ratio is taken into account at the next update event.
-  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
-  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Prescaler between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
-  WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
-  * @brief  Get the prescaler value.
-  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
-  * @param  TIMx Timer instance
-  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
-  * @brief  Set the auto-reload value.
-  * @note The counter is blocked while the auto-reload value is null.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
-  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
-  * @param  TIMx Timer instance
-  * @param  AutoReload between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
-  WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
-  * @brief  Get the auto-reload value.
-  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @param  TIMx Timer instance
-  * @retval Auto-reload value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @param  DMAReqTrigger This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
-  * @brief  Get actual trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
-  * @brief  Enable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_EnableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Disable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_DisableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Indicate whether channel(s) is(are) enabled.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure an output channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Define the behavior of the output reference signal OCxREF from which
-  *         OCx and OCxN (when relevant) are derived.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_SetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Get the output compare mode of an output channel.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_GetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Set the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Enable fast mode for the output channel.
-  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Disable fast mode for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Indicates whether fast mode is enabled for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable clearing the output channel on an external event.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
-  * @note This function enables clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure input channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
-  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC1F          LL_TIM_IC_Config\n
-  *         CCMR1        CC2S          LL_TIM_IC_Config\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC2F          LL_TIM_IC_Config\n
-  *         CCMR2        CC3S          LL_TIM_IC_Config\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC3F          LL_TIM_IC_Config\n
-  *         CCMR2        CC4S          LL_TIM_IC_Config\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC4F          LL_TIM_IC_Config\n
-  *         CCER         CC1P          LL_TIM_IC_Config\n
-  *         CCER         CC1NP         LL_TIM_IC_Config\n
-  *         CCER         CC2P          LL_TIM_IC_Config\n
-  *         CCER         CC2NP         LL_TIM_IC_Config\n
-  *         CCER         CC3P          LL_TIM_IC_Config\n
-  *         CCER         CC3NP         LL_TIM_IC_Config\n
-  *         CCER         CC4P          LL_TIM_IC_Config\n
-  *         CCER         CC4NP         LL_TIM_IC_Config
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
-  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
-             << SHIFT_TAB_ICxx[iChannel]);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICActiveInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the prescaler of input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current prescaler value acting on an  input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the current input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
-          SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get captured value for input channel 1.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get captured value for input channel 2.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get captured value for input channel 3.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get captured value for input channel 4.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
-  * @{
-  */
-/**
-  * @brief  Enable external clock mode 2.
-  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Disable external clock mode 2.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Indicate whether external clock mode 2 is enabled.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the clock source of the counter clock.
-  * @note when selected clock source is external clock mode 1, the timer input
-  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
-  *       function. This timer input must be configured by calling
-  *       the @ref LL_TIM_IC_Config() function.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode1.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
-  *         SMCR         ECE           LL_TIM_SetClockSource
-  * @param  TIMx Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
-  * @brief  Set the encoder interface mode.
-  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the encoder mode.
-  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
-  * @param  TIMx Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
-  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger output (TRGO) used for timer synchronization .
-  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can operate as a master timer.
-  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
-  * @param  TIMx Timer instance
-  * @param  TimerSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO_RESET
-  *         @arg @ref LL_TIM_TRGO_ENABLE
-  *         @arg @ref LL_TIM_TRGO_UPDATE
-  *         @arg @ref LL_TIM_TRGO_CC1IF
-  *         @arg @ref LL_TIM_TRGO_OC1REF
-  *         @arg @ref LL_TIM_TRGO_OC2REF
-  *         @arg @ref LL_TIM_TRGO_OC3REF
-  *         @arg @ref LL_TIM_TRGO_OC4REF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
-  * @brief  Set the synchronization mode of a slave timer.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
-  * @param  TIMx Timer instance
-  * @param  SlaveMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
-  *         @arg @ref LL_TIM_SLAVEMODE_RESET
-  *         @arg @ref LL_TIM_SLAVEMODE_GATED
-  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
-  * @brief  Set the selects the trigger input to be used to synchronize the counter.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
-  * @param  TIMx Timer instance
-  * @param  TriggerInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TS_ITR0
-  *         @arg @ref LL_TIM_TS_ITR1
-  *         @arg @ref LL_TIM_TS_ITR2
-  *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
-  * @brief  Enable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief  Disable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief Indicates whether the Master/Slave mode is enabled.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the external trigger (ETR) input.
-  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an external trigger input.
-  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
-  *         SMCR         ETPS          LL_TIM_ConfigETR\n
-  *         SMCR         ETF           LL_TIM_ConfigETR
-  * @param  TIMx Timer instance
-  * @param  ETRPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
-  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
-  * @param  ETRPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
-  * @param  ETRFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
-                                      uint32_t ETRFilter)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
-  * @{
-  */
-/**
-  * @brief  Configures the timer DMA burst feature.
-  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports the DMA burst mode.
-  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
-  *         DCR          DBA           LL_TIM_ConfigDMABurst
-  * @param  TIMx Timer instance
-  * @param  DMABurstBaseAddress This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
-  * @param  DMABurstLength This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
-  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
-  * @{
-  */
-/**
-  * @brief  Remap TIM inputs (input channel, internal/external triggers).
-  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
-  *       a some timer inputs can be remapped.
-  * @rmtoll  TIM2_OR     ITR1_RMP      LL_TIM_SetRemap\n
-  *         TIM3_OR     ITR2_RMP      LL_TIM_SetRemap\n
-  *         TIM9_OR     TI1_RMP       LL_TIM_SetRemap\n
-  *         TIM9_OR     ITR1_RMP      LL_TIM_SetRemap\n
-  *         TIM10_OR    TI1_RMP       LL_TIM_SetRemap\n
-  *         TIM10_OR    ETR_RMP       LL_TIM_SetRemap\n
-  *         TIM10_OR    TI1_RMP_RI    LL_TIM_SetRemap\n
-  *         TIM11_OR    TI1_RMP       LL_TIM_SetRemap\n
-  *         TIM11_OR    ETR_RMP       LL_TIM_SetRemap\n
-  *         TIM11_OR    TI1_RMP_RI    LL_TIM_SetRemap
-  * @param  TIMx Timer instance
-  * @param  Remap Remap params depends on the TIMx. Description available only
-  *         in CHM version of the User Manual (not in .pdf).
-  *         Otherwise see Reference Manual description of OR registers.
-  *
-  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
-  *
-  *         TIM2: any combination of ITR1_RMP where
-  *
-  *            . . ITR1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC  (**)
-  *            @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO  (**)
-  *
-  *         TIM3: any combination of ITR2_RMP where
-  *
-  *            . . ITR2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC  (**)
-  *            @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO  (**)
-  *
-  *         TIM9: any combination of TI1_RMP, ITR1_RMP where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
-  *            @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
-  *
-  *            . . ITR1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO  (*)
-  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO  (*)
-  *
-  *
-  *         TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI   where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
-  *            @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
-  *            @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
-  *
-  *            . . ETR_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO  (*)
-  *
-  *            . . TI1_RMP_RI can be one of the following values
-  *            @arg @ref LL_TIM_TIM10_TI1_RMP_RI        (*)
-  *
-  *
-  *         TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI   where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
-  *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
-  *            @arg @ref LL_TIM_TIM11_TI1_RMP
-  *
-  *            . . ETR_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO  (*)
-  *
-  *            . . TI1_RMP_RI can be one of the following values
-  *            @arg @ref LL_TIM_TIM11_TI1_RMP_RI        (*)
-  *
-  *           (*) value not available in all devices categories
-  *           (**) register not available in all devices categories
-  *
-  * @note Option registers are available only for cat.3, cat.4 and cat.5  devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
-{
-  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
-  * @{
-  */
-/**
-  * @brief  Set the OCREF clear input source
-  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
-  * @note This function can only be used in Output compare and PWM modes.
-  * @note the ETR signal can be connected to the output of a comparator to be used for current handling
-  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
-  * @param  TIMx Timer instance
-  * @param  OCRefClearInputSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
-  * @{
-  */
-/**
-  * @brief  Clear the update interrupt flag (UIF).
-  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
-  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
-  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
-  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
-  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
-  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
-  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
-  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
-  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the trigger interrupt flag (TIF).
-  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
-  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
-  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
-  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
-  *         (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
-  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
-  *         (Capture/Compare 2 over-capture interrupt is pending).
-  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
-  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
-  *         (Capture/Compare 3 over-capture interrupt is pending).
-  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
-  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
-  *         (Capture/Compare 4 over-capture interrupt is pending).
-  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
-  * @{
-  */
-/**
-  * @brief  Enable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Disable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Indicates whether the update interrupt (UIE) is enabled.
-  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
-  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
-  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
-  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
-  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
-  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
-  * @{
-  */
-/**
-  * @brief  Enable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Disable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
-  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
-  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
-  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
-  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
-  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
-  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
-  * @{
-  */
-/**
-  * @brief  Generate an update event.
-  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
-  * @brief  Generate Capture/Compare 1 event.
-  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 2 event.
-  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 3 event.
-  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 4 event.
-  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
-  * @brief  Generate trigger event.
-  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h
deleted file mode 100644
index 66f12218683..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h
+++ /dev/null
@@ -1,2521 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_USART_H
-#define __STM32L1xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @defgroup USART_LL USART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
-  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
-                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
-  * @brief LL USART Clock Init Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
-                                           USART HW configuration can be modified afterwards using unitary functions
-                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
-                                           For more details, refer to description of this function. */
-
-  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
-                                           For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_ReadReg function
-  * @{
-  */
-#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */
-#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */
-#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */
-#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */
-#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */
-#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */
-#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */
-#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */
-#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */
-#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
-  * @{
-  */
-#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
-#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
-  * @{
-  */
-#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
-  * @{
-  */
-#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
-  * @{
-  */
-
-#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
-  * @{
-  */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
-  * @{
-  */
-#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
-  * @{
-  */
-#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
-  */
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
-                                                                           ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
-                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
-  */
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
-/* USART BRR = mantissa + overflow + fraction
-            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
-                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
-                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  USART Enable
-  * @rmtoll CR1          UE            LL_USART_Enable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  USART Disable (all USART prescalers and outputs are disabled)
-  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the USART is kept, but all the status
-  *         flags, in the USARTx_SR are set to their default values.
-  * @rmtoll CR1          UE            LL_USART_Disable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if USART is enabled
-  * @rmtoll CR1          UE            LL_USART_IsEnabled
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
-  *         CR1          TE            LL_USART_SetTransferDirection
-  * @param  USARTx USART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
-  *         CR1          TE            LL_USART_GetTransferDirection
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_USART_SetParity\n
-  *         CR1          PCE           LL_USART_SetParity
-  * @param  USARTx USART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_USART_GetParity\n
-  *         CR1          PCE           LL_USART_GetParity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_USART_SetDataWidth
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_USART_GetDataWidth
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Set Oversampling to 8-bit or 16-bit mode
-  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
-  * @param  USARTx USART Instance
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
-  * @brief  Return Oversampling mode
-  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
-  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @param  LastBitClockPulse This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
-  * @brief  Retrieve Clock pulse of the last data bit output configuration
-  *         (Last bit Clock pulse output to the SCLK pin or not)
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
-  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
-  * @param  USARTx USART Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
-  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
-  * @param  USARTx USART Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
-  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
-  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
-  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
-  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
-  *         CR2          CPOL          LL_USART_ConfigClock\n
-  *         CR2          LBCL          LL_USART_ConfigClock
-  * @param  USARTx USART Instance
-  * @param  Phase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @param  LBCPOutput This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
-  * @brief  Enable Clock output on SCLK pin
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Disable Clock output on SCLK pin
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Indicate if Clock output on SCLK pin is enabled
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
-  * @param  USARTx USART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
-  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
-  *         CR1          PCE           LL_USART_ConfigCharacter\n
-  *         CR1          M             LL_USART_ConfigCharacter\n
-  *         CR2          STOP          LL_USART_ConfigCharacter
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
-                                              uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Set Address of the USART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress
-  * @param  USARTx USART Instance
-  * @param  NodeAddress 4 bit Address of the USART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
-}
-
-/**
-  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.
-  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
-  * @param  USARTx USART Instance
-  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Disable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Indicate if One bit sampling method is enabled
-  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
-}
-
-/**
-  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
-  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
-  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
-  *         (Baud rate value != 0)
-  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
-                                          uint32_t BaudRate)
-{
-  if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
-  }
-  else
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
-  uint32_t usartdiv = 0x0U;
-  uint32_t brrresult = 0x0U;
-
-  usartdiv = USARTx->BRR;
-
-  if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    if ((usartdiv & 0xFFF7U) != 0U)
-    {
-      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
-      brrresult = (PeriphClk * 2U) / usartdiv;
-    }
-  }
-  else
-  {
-    if ((usartdiv & 0xFFFFU) != 0U)
-    {
-      brrresult = PeriphClk / usartdiv;
-    }
-  }
-  return (brrresult);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
-  * @{
-  */
-
-/**
-  * @brief  Enable IrDA mode
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_EnableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Disable IrDA mode
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_DisableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Indicate if IrDA mode is enabled
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
-}
-
-/**
-  * @brief  Configure IrDA Power Mode (Normal or Low Power)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_IRDA_POWER_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
-  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
-  * @brief  Set Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
-  * @brief  Return Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Smartcard NACK transmission
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Disable Smartcard NACK transmission
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Indicate if Smartcard NACK transmission is enabled
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
-}
-
-/**
-  * @brief  Enable Smartcard mode
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Disable Smartcard mode
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Indicate if Smartcard mode is enabled
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
-}
-
-/**
-  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
-  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
-}
-
-/**
-  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
-  * @{
-  */
-
-/**
-  * @brief  Set LIN Break Detection Length
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @param  LINBDLength This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
-  * @brief  Return LIN Break Detection Length
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
-  * @brief  Enable LIN mode
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Disable LIN mode
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Indicate if LIN mode is enabled
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
-  * @{
-  */
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
-  * @note   In UART mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Asynchronous Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
-  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
-  /* In Asynchronous mode, the following bits must be kept cleared:
-  - LINEN, CLKEN bits in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
-  * @note   In Synchronous mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the USART in Synchronous mode.
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  * @note   Other remaining configurations items related to Synchronous Mode
-  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
-  *         CR3          IREN          LL_USART_ConfigSyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-  /* set the UART/USART in Synchronous mode */
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
-  * @note   In LIN mode, the following bits must be kept cleared:
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also set the UART/USART in LIN mode.
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
-  * @note   Other remaining configurations items related to LIN Mode
-  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
-  *         CR2          STOP          LL_USART_ConfigLINMode\n
-  *         CR2          LINEN         LL_USART_ConfigLINMode\n
-  *         CR3          IREN          LL_USART_ConfigLINMode\n
-  *         CR3          SCEN          LL_USART_ConfigLINMode\n
-  *         CR3          HDSEL         LL_USART_ConfigLINMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
-  /* In LIN mode, the following bits must be kept cleared:
-  - STOP and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* Set the UART/USART in LIN mode */
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
-  * @note   In Half Duplex mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *         This function also sets the UART/USART in Half Duplex mode.
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
-  * @note   Other remaining configurations items related to Half Duplex Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
-  /* In Half Duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
-  /* set the UART/USART in Half Duplex mode */
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
-  * @note   In Smartcard mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also configures Stop bits to 1.5 bits and
-  *         sets the USART in Smartcard mode (SCEN bit).
-  *         Clock Output is also enabled (CLKEN).
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
-  * @note   Other remaining configurations items related to Smartcard Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
-  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
-  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
-  /* In Smartcard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-  /* Configure Stop bits to 1.5 bits */
-  /* Synchronous mode is activated by default */
-  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
-  /* set the UART/USART in Smartcard mode */
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
-  * @note   In IRDA mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the UART/USART in IRDA mode (IREN bit).
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
-  * @note   Other remaining configurations items related to Irda Mode
-  *         (as Baud Rate, Word length, Power mode, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
-  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
-  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
-  *         CR3          IREN          LL_USART_ConfigIrdaMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* set the UART/USART in IRDA mode */
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
-  *         (several USARTs connected in a network, one of the USARTs can be the master,
-  *         its TX output connected to the RX inputs of the other slaves USARTs).
-  * @note   In MultiProcessor mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Multi processor Mode
-  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
-  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
-  /* In Multi Processor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the USART Parity Error Flag is set or not
-  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
-}
-
-/**
-  * @brief  Check if the USART Framing Error Flag is set or not
-  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
-}
-
-/**
-  * @brief  Check if the USART Noise error detected Flag is set or not
-  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
-}
-
-/**
-  * @brief  Check if the USART OverRun Error Flag is set or not
-  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
-}
-
-/**
-  * @brief  Check if the USART IDLE line detected Flag is set or not
-  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
-}
-
-/**
-  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
-  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Flag is set or not
-  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
-}
-
-/**
-  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
-  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Flag is set or not
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
-}
-
-/**
-  * @brief  Check if the USART CTS Flag is set or not
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
-}
-
-/**
-  * @brief  Check if the USART Send Break Flag is set or not
-  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
-}
-
-/**
-  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
-}
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         NE, FE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           PE            LL_USART_ClearFlag_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           FE            LL_USART_ClearFlag_FE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Noise detected Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, FE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           NF            LL_USART_ClearFlag_NE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, FE, IDLE would also be cleared.
-  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, FE, ORE would also be cleared.
-  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll SR           TC            LL_USART_ClearFlag_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_TC));
-}
-
-/**
-  * @brief  Clear RX Not Empty Flag
-  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
-}
-
-/**
-  * @brief  Clear LIN Break Detection Flag
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Enable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Enable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable LIN Break Detection Interrupt
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
-  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Disable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable LIN Break Detection Interrupt
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
-  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
-}
-
-/**
-  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
-}
-
-/**
-  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
-}
-
-/**
-  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
-}
-
-/**
-  * @brief  Check if the USART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
-}
-
-/**
-  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr
-  * @note   Address of Data Register is valid for both Transmit and Receive transfers.
-  * @param  USARTx USART Instance
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
-{
-  /* return address of DR register */
-  return ((uint32_t) & (USARTx->DR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll DR           DR            LL_USART_ReceiveData8
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
-  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll DR           DR            LL_USART_ReceiveData9
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
-  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll DR           DR            LL_USART_TransmitData8
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
-  USARTx->DR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll DR           DR            LL_USART_TransmitData9
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
-  USARTx->DR = Value & 0x1FFU;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_SBK);
-}
-
-/**
-  * @brief  Put USART in Mute mode
-  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
-  * @brief  Put USART in Active mode
-  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usb.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usb.h
deleted file mode 100644
index c817492a341..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usb.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_usb.h
-  * @author  MCD Application Team
-  * @brief   Header file of USB Low Layer HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_USB_H
-#define STM32L1xx_LL_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-#if defined (USB)
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USB_LL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  USB Mode definition
-  */
-
-
-
-typedef enum
-{
-  USB_DEVICE_MODE  = 0
-} USB_ModeTypeDef;
-
-/**
-  * @brief  USB Initialization Structure definition
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.
-                                         This parameter depends on the used USB core.
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t speed;                   /*!< USB Core speed.
-                                         This parameter can be any value of @ref PCD_Speed/HCD_Speed
-                                                                                 (HCD_SPEED_xxx, HCD_SPEED_xxx) */
-
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
-
-  uint32_t phy_itface;              /*!< Select the used PHY interface.
-                                         This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
-
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
-
-  uint32_t low_power_enable;        /*!< Enable or disable Low Power mode                                       */
-
-  uint32_t lpm_enable;              /*!< Enable or disable Battery charging.                                    */
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
-} USB_CfgTypeDef;
-
-typedef struct
-{
-  uint8_t   num;             /*!< Endpoint number
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 15    */
-
-  uint8_t   is_in;           /*!< Endpoint direction
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   is_stall;        /*!< Endpoint stall condition
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint8_t   type;            /*!< Endpoint type
-                                  This parameter can be any value of @ref USB_EP_Type                       */
-
-  uint8_t   data_pid_start;  /*!< Initial data PID
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-
-  uint16_t  pmaadress;       /*!< PMA Address
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint16_t  pmaaddr0;        /*!< PMA Address0
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint16_t  pmaaddr1;        /*!< PMA Address1
-                                  This parameter can be any value between Min_addr = 0 and Max_addr = 1K    */
-
-  uint8_t   doublebuffer;    /*!< Double buffer enable
-                                  This parameter can be 0 or 1                                              */
-
-  uint16_t  tx_fifo_num;     /*!< This parameter is not required by USB Device FS peripheral, it is used
-                                  only by USB OTG FS peripheral
-                                  This parameter is added to ensure compatibility across USB peripherals    */
-
-  uint32_t  maxpacket;       /*!< Endpoint Max packet size
-                                  This parameter must be a number between Min_Data = 0 and Max_Data = 64KB  */
-
-  uint8_t   *xfer_buff;      /*!< Pointer to transfer buffer                                                */
-
-  uint32_t  xfer_len;        /*!< Current transfer length                                                   */
-
-  uint32_t  xfer_count;      /*!< Partial transfer length in case of multi packet transfer                  */
-
-  uint32_t  xfer_len_db;      /*!< double buffer transfer length used with bulk double buffer in           */
-
-  uint8_t   xfer_fill_db;     /*!< double buffer Need to Fill new buffer  used with bulk_in                */
-
-} USB_EPTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
-  * @{
-  */
-#define EP_MPS_64                              0U
-#define EP_MPS_32                              1U
-#define EP_MPS_16                              2U
-#define EP_MPS_8                               3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
-  * @{
-  */
-#define EP_TYPE_CTRL                           0U
-#define EP_TYPE_ISOC                           1U
-#define EP_TYPE_BULK                           2U
-#define EP_TYPE_INTR                           3U
-#define EP_TYPE_MSK                            3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL Device Speed
-  * @{
-  */
-#define USBD_FS_SPEED                          2U
-/**
-  * @}
-  */
-
-#define BTABLE_ADDRESS                         0x000U
-#define PMA_ACCESS                             2U
-
-#define EP_ADDR_MSK                            0x7U
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-
-
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
-
-#if defined (HAL_PCD_MODULE_ENABLED)
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-#endif
-
-HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-
-void              USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
-                               uint16_t wPMABufAddr, uint16_t wNBytes);
-
-void              USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
-                              uint16_t wPMABufAddr, uint16_t wNBytes);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32L1xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h
deleted file mode 100644
index 89d6b5329d1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_utils.h
-  * @author  MCD Application Team
-  * @brief   Header file of UTILS LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL UTILS driver contains a set of generic APIs that can be
-    used by user:
-      (+) Device electronic signature
-      (+) Timing functions
-      (+) PLL configuration functions
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_UTILS_H
-#define __STM32L1xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup UTILS_LL UTILS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
-  * @{
-  */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS              UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
-  * @{
-  */
-/**
-  * @brief  UTILS PLL structure definition
-  */
-typedef struct
-{
-  uint32_t PLLMul;   /*!< Multiplication factor for PLL VCO input clock.
-                          This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
-
-                          This feature can be modified afterwards using unitary function
-                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLDiv;   /*!< Division factor for PLL VCO output clock.
-                          This parameter can be a value of @ref RCC_LL_EC_PLL_DIV
-
-                          This feature can be modified afterwards using unitary function
-                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
-  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAHBPrescaler(). */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB1Prescaler(). */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
-  * @{
-  */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
-  * @{
-  */
-#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
-  * @{
-  */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
-  * @{
-  */
-
-/**
-  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[31:0]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[63:32]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U))));
-}
-
-/**
-  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[95:64]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U))));
-}
-
-/**
-  * @brief  Get Flash memory size
-  * @note   For DEV_ID = 0x416 or 0x427 or 0x429 or 0x437, this field value indicates the Flash memory
-  *         size of the device in Kbytes.\n
-  *         Example: 0x0080 = 128 Kbytes.\n
-  *         For DEV_ID = 0x436, the field value can be '0' or '1', with '0' for 384 Kbytes and '1' for 256 Kbytes.
-  * @note   For DEV_ID = 0x429, only LSB part of F_SIZE: F_SIZE[7:0] is valid. The MSB part
-  *         F_SIZE[15:8] is reserved and must be ignored.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source of the time base.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
-  * @retval None
-  */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
-  /* Configure the SysTick to have interrupt in 1ms time base */
-  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
-  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
-}
-
-void        LL_Init1msTick(uint32_t HCLKFrequency);
-void        LL_mDelay(uint32_t Delay);
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
-  * @{
-  */
-
-void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-#if defined(FLASH_ACR_LATENCY)
-ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
-#endif /* FLASH_ACR_LATENCY */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_wwdg.h b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_wwdg.h
deleted file mode 100644
index bdfb142f091..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_wwdg.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_wwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of WWDG LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32L1xx_LL_WWDG_H
-#define STM32L1xx_LL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (WWDG)
-
-/** @defgroup WWDG_LL WWDG
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
-  * @{
-  */
-#define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
-  * @{
-  */
-#define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in WWDG register
-  * @param  __INSTANCE__ WWDG Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in WWDG register
-  * @param  __INSTANCE__ WWDG Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup WWDG_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
-  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
-  *         then it cannot be disabled again except by a reset.
-  *         This bit is set by software and only cleared by hardware after a reset.
-  *         When WDGA = 1, the watchdog can generate a reset.
-  * @rmtoll CR           WDGA          LL_WWDG_Enable
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
-{
-  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
-}
-
-/**
-  * @brief  Checks if Window Watchdog is enabled
-  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
-  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
-  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
-  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
-  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
-  * @rmtoll CR           T             LL_WWDG_SetCounter
-  * @param  WWDGx WWDG Instance
-  * @param  Counter 0..0x7F (7 bit counter value)
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
-{
-  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
-}
-
-/**
-  * @brief  Return current Watchdog Counter Value (7 bits counter value)
-  * @rmtoll CR           T             LL_WWDG_GetCounter
-  * @param  WWDGx WWDG Instance
-  * @retval 7 bit Watchdog Counter value
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CR, WWDG_CR_T));
-}
-
-/**
-  * @brief  Set the time base of the prescaler (WDGTB).
-  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
-  *         is decremented every (4096 x 2expWDGTB) PCLK cycles
-  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
-  * @param  WWDGx WWDG Instance
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_WWDG_PRESCALER_1
-  *         @arg @ref LL_WWDG_PRESCALER_2
-  *         @arg @ref LL_WWDG_PRESCALER_4
-  *         @arg @ref LL_WWDG_PRESCALER_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
-{
-  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
-}
-
-/**
-  * @brief  Return current Watchdog Prescaler Value
-  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
-  * @param  WWDGx WWDG Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_WWDG_PRESCALER_1
-  *         @arg @ref LL_WWDG_PRESCALER_2
-  *         @arg @ref LL_WWDG_PRESCALER_4
-  *         @arg @ref LL_WWDG_PRESCALER_8
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
-}
-
-/**
-  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
-  * @note   This window value defines when write in the WWDG_CR register
-  *         to program Watchdog counter is allowed.
-  *         Watchdog counter value update must occur only when the counter value
-  *         is lower than the Watchdog window register value.
-  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
-  *         (in the control register) is refreshed before the downcounter has reached
-  *         the watchdog window register value.
-  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
-  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
-  * @rmtoll CFR          W             LL_WWDG_SetWindow
-  * @param  WWDGx WWDG Instance
-  * @param  Window 0x00..0x7F (7 bit Window value)
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
-{
-  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
-}
-
-/**
-  * @brief  Return current Watchdog Window Value (7 bits value)
-  * @rmtoll CFR          W             LL_WWDG_GetWindow
-  * @param  WWDGx WWDG Instance
-  * @retval 7 bit Watchdog Window value
-  */
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
-{
-  return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-/**
-  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
-  * @note   This bit is set by hardware when the counter has reached the value 0x40.
-  *         It must be cleared by software by writing 0.
-  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
-  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
-  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_LL_EF_IT_Management IT_Management
-  * @{
-  */
-/**
-  * @brief  Enable the Early Wakeup Interrupt.
-  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
-  *         This interrupt is only cleared by hardware after a reset
-  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
-}
-
-/**
-  * @brief  Check if Early Wakeup Interrupt is enabled
-  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
-  * @param  WWDGx WWDG Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
-  return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* WWDG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L1xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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-<h1 id="release-notes-for-stm32l1xx-hal-drivers"><small>Release Notes for</small> <mark>STM32L1xx HAL Drivers</mark></h1>
-<p>Copyright © 2017 STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
-</center>
-</div>
-</div>
-<h1 id="license">License</h1>
-<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
-<h1 id="purpose">Purpose</h1>
-<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
-<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
-<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
-<ul>
-<li>New set of inline functions for direct and atomic register access</li>
-<li>One-shot operations that can be used by the HAL drivers or from application level</li>
-<li>Full independence from HAL and standalone usage (without HAL drivers)</li>
-<li>Full features coverage of all the supported peripherals</li>
-</ul>
-</div>
-<section id="update-history" class="col-sm-12 col-lg-8">
-<h1>Update History</h1>
-<div class="collapse">
-<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.4.4 / 21-May-2021</label>
-<div>
-<h2 id="main-changes">Main Changes</h2>
-<h3 id="maintenance-release">Maintenance release</h3>
-<ul>
-<li>Patch release to to fix known defects and enhancements implementation.</li>
-</ul>
-<h2 id="contents">Contents</h2>
-<ul>
-<li><strong>HAL Generic</strong> update
-<ul>
-<li>Update HAL TimeBase TIM template for more robustness
-<ul>
-<li>Update Hal_Init_Tick() API to propoerty store the priority when using the non-default time base.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong> update
-<ul>
-<li>Previous release note corrected by removing reference to ChannelNState.</li>
-<li>Made TIM_DMADelayPulseCplt callback as a private function.</li>
-<li>Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters.</li>
-<li>Update input capture measurement in DMA mode to avoid zero return values at high frequencies.</li>
-<li>Update LL_TIM_GetCounterMode() API to return the correct counter mode.</li>
-<li>Correct reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.</li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong> update
-<ul>
-<li>Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.</li>
-<li>Update to fix MISRA-C 2012 Rule-13.2.</li>
-</ul></li>
-<li><strong>HAL/LL USART</strong> update
-<ul>
-<li>Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.</li>
-</ul></li>
-<li><strong>HAL UART</strong> update
-<ul>
-<li>Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback. Update UART polling and interruption processes to fix issues related to access out of user’s specified buffer. Fix wrong comment related to RX pin configuration within the description section. Enhance reception for idle services (ReceptionToIdle):
-<ul>
-<li>Add a new field (HAL_UART_RxTypeTypeDef) to the UART_HandleTypeDef structure to identify the type of ongoing reception.</li>
-<li>Add UART Reception Event Callback registration.</li>
-<li>Add reception specific APIs specific to reception for Idle transfer in different modes:</li>
-<li>HAL_UARTEx_ReceiveToIdle(): Receive an amount of data in blocking mode until either the expected number of data is received or an IDLE event occurs.</li>
-<li>HAL_UARTEx_ReceiveToIdle_IT(): Receive an amount of data in interrupt mode until either the expected number of data is received or an IDLE event occurs.</li>
-<li>HAL_UARTEx_ReceiveToIdle_DMA(): Receive an amount of data in DMA mode until either the expected number of data is received or an IDLE event occurs.</li>
-<li>Update HAL_UART_Receive(), HAL_UART_Receive_IT() and HAL_UART_Receive_DMA() APIs to support the new enhancement of ReceptionToIdle.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMARTCARD</strong> update
-<ul>
-<li>Fix typos in the SMARTCARD State definition description.</li>
-</ul></li>
-<li><strong>HAL IRDA</strong> update
-<ul>
-<li>Fix typos in the IRDA State definition description.</li>
-</ul></li>
-<li><strong>HAL RTC</strong> update
-<ul>
-<li>New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
-<ul>
-<li>HAL_RTC_DST_Add1Hour()</li>
-<li>HAL_RTC_DST_Sub1Hour()</li>
-<li>HAL_RTC_DST_SetStoreOperation()</li>
-<li>HAL_RTC_DST_ClearStoreOperation()</li>
-<li>HAL_RTC_DST_ReadStoreOperation()</li>
-<li>DayLightSaving and StoreOperation interfaces from RTC_TimeTypeDef type and HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H() and HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H() macros are now deprecated.</li>
-</ul></li>
-<li>Fix the wait for the RSF bit to be cleared in the LL_RTC_WaitForSynchro function.</li>
-<li>Correct month management in IS_LL_RTC_MONTH() macro.</li>
-<li>Update __HAL_RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)-&gt;Instance pointer and avoid “unused variable” warnings.</li>
-</ul></li>
-<li><strong>LL FMC_LL</strong> update
-<ul>
-<li>Fix compilation warning with gcc -Wpedantic compiler option</li>
-</ul></li>
-<li><strong>HAL SDMMC</strong> update
-<ul>
-<li>Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.</li>
-<li>SD_FindSCR() updated to resolve an issue with FIFO blocking when reading.</li>
-<li>Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application.</li>
-<li>Add the block size settings in the initialization functions and remove it from read/write transactions to avoid repeated and inefficient reconfiguration.</li>
-<li>Update read/write functions in DMA mode in order to force the DMA direction.</li>
-<li>Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> update
-<ul>
-<li>Update FLASH_SetErrorCode() to correctly handle the SIZERR flag.</li>
-</ul></li>
-<li><strong>HAL USB_FS</strong> update
-<ul>
-<li>HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode.</li>
-</ul></li>
-<li><strong>HAL OPAMP</strong> update
-<ul>
-<li>Fix CodeSonar error.</li>
-<li>Update HAL_OPAMP_SelfCalibrate() API to avoid wrong configuration of trimming value “n” and “p”.</li>
-</ul></li>
-<li><strong>HAL I2C</strong> update
-<ul>
-<li>Update to avoid I2C interrupt in endless loop:
-<ul>
-<li>Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA() and HAL_I2C_Master_Receive_DMA() APIs to unlock the I2C peripheral before generating the start.</li>
-</ul></li>
-<li>Update the management of (hi2c-&gt;hdmatx!=NULL) &amp; (hi2c-&gt;hdmarx!=NULL) check.</li>
-<li>Update to prevent several calls of Start bit:
-<ul>
-<li>Update I2C_MemoryTransmit_TXE_BTF() API to increment EventCount.</li>
-</ul></li>
-<li>Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it’s indicated in the reference manual.</li>
-<li>Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to fix an issue where the transfer of the first few bytes to an I2C memory fails.</li>
-</ul></li>
-<li><strong>HAL/LL ADC</strong> update
-<ul>
-<li>Update HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.</li>
-<li>Update HAL ADC driver to add include of the LL ADC driver.</li>
-<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
-<li>Update LL_ADC_REG_Init() API to avoid enabling continuous mode and discontinuous mode simultaneously.</li>
-</ul></li>
-<li><strong>HAL WWDG</strong> update
-<ul>
-<li>Update HAL driver description.</li>
-</ul></li>
-<li><strong>HAL IWDG</strong> update
-<ul>
-<li>Update HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue.</li>
-<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
-</ul></li>
-<li><strong>HAL EXTI</strong> update
-<ul>
-<li>Update macros using LINE as a macro parameter to use EXTI_LINE instead to resolve parameter conflicts with standard C usage.</li>
-<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.4.3 / 22-October-2020</label>
-<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
-<ul>
-<li>General updates to fix known defect.</li>
-</ul>
-<h2 id="contents-1">Contents</h2>
-<ul>
-<li><strong>HAL/LL I2C</strong> driver
-<ul>
-<li>Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API:
-<ul>
-<li>Abort the right ongoing DMA transfer when memory write access request operation failed: fix typo “hdmarx” replaced by “hdmatx”</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.4.2 / 28-August-2020</label>
-<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
-<ul>
-<li>Patch release to fix issue in I2C HAL driver</li>
-</ul>
-<h2 id="contents-2">Contents</h2>
-<ul>
-<li><strong>HAL I2C</strong> driver
-<ul>
-<li>Update I2C_MasterReceiveRXNE() static API to avoid set the STOP bit again after the bit clearing by Hardware during the masking operation.
-<ul>
-<li>Add new API I2C_WaitOnSTOPRequestThroughIT() to wait for stop bit.</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.4.1 / 24-June-2020</label>
-<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
-<ul>
-<li>Add new HAL EXTI driver</li>
-<li>General updates to fix known defects and enhancements implementation</li>
-</ul>
-<h2 id="contents-3">Contents</h2>
-<ul>
-<li><strong>HAL</strong> driver
-<ul>
-<li>Enhance HAL_SetTickFreq() API robustness
-<ul>
-<li>Restore previous tick frequency when a wrong tick initialization occurs.</li>
-</ul></li>
-</ul></li>
-<li><strong>LL ADC</strong> driver
-<ul>
-<li>Fix ADC TEMPSENSOR/VREFINT calibration addresses</li>
-</ul></li>
-<li><strong>HAL/LL GPIO</strong> driver
-<ul>
-<li>Update HAL_GPIO_TogglePin() API to allow the toggling of many pins</li>
-<li>Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s</li>
-</ul></li>
-<li><strong>HAL EXTI</strong> driver
-<ul>
-<li>Add new HAL_EXTI driver.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> driver
-<ul>
-<li>Fix assert compilation error with HAL_FLASHEx_DATAEEPROM_Erase() API.</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong> driver
-<ul>
-<li>Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes
-<ul>
-<li>Add stop condition generation when NACK occurs.</li>
-</ul></li>
-<li>Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).</li>
-<li>Update HAL_I2C_Init() API to force software reset before setting new I2C configuration</li>
-<li>Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs
-<ul>
-<li>Add new ErrorCode define: HAL_I2C_WRONG_START</li>
-<li>Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START</li>
-</ul></li>
-<li>Update sequential APIs to avoid requesting a START when a STOP condition is not fully treated
-<ul>
-<li>Wait the end of STOP treatment by polling (with a timeout) the STOP bit on Control register CR1</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL I2S</strong> driver
-<ul>
-<li>Update HAL_I2S_DMAStop() API to be more safe
-<ul>
-<li>Add a check on BSY, TXE and RXNE flags before disabling the I2S</li>
-</ul></li>
-<li>Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).
-<ul>
-<li>Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.</li>
-<li>Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL IRDA</strong> driver
-<ul>
-<li>Update IRDA interruption handler to manage correctly the overrun interrupt
-<ul>
-<li>Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMARTCARD</strong> driver
-<ul>
-<li>Update SMARTCARD interruption handler to manage correctly the overrun interrupt
-<ul>
-<li>Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.</li>
-</ul></li>
-<li>Update SMARTCARD transmission and reception API to handle memory corruption
-<ul>
-<li>HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Receive()</li>
-<li>SMARTCARD_Transmit_IT(), SMARTCARD_Receive_IT()</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong> driver
-<ul>
-<li>Update to implement Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode.</li>
-<li>Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers.
-<ul>
-<li>To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode</li>
-<li>Use the bit-mask for SPI configuration</li>
-</ul></li>
-<li>Update Transmit/Receive processes in half-duplex mode
-<ul>
-<li>Disable the SPI instance before setting BDIOE bit</li>
-</ul></li>
-<li>Fix wrong timeout management
-<ul>
-<li>Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong> driver
-<ul>
-<li>Align HAL/LL TIM driver with latest updates and enhancements</li>
-<li>Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay
-<ul>
-<li>__HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().</li>
-</ul></li>
-<li>Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
-<ul>
-<li>Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.</li>
-<li>Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.</li>
-<li>Update HAL_TIM_Encoder_Init() API</li>
-<li>Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</li>
-</ul></li>
-<li>Fix bug when using multiple DMA request to different channels of same timer
-<ul>
-<li>Introduce DMA burst state management mechanism
-<ul>
-<li>Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef</li>
-<li>Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState</li>
-<li>Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation</li>
-<li>Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure</li>
-<li>Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel)</li>
-<li>Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel)</li>
-</ul></li>
-</ul></li>
-<li>Implement TIM channel state management mechanism
-<ul>
-<li>Add new macro
-<ul>
-<li>TIM_CHANNEL_STATE_SET_ALL</li>
-<li>TIM_CHANNEL_STATE_SET</li>
-<li>TIM_CHANNEL_STATE_GET</li>
-</ul></li>
-<li>Add new API HAL_TIM_GetActiveChannel()</li>
-<li>Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel</li>
-<li>Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef</li>
-<li>Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState</li>
-<li>Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation state</li>
-</ul></li>
-<li>Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger.
-<ul>
-<li>Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.</li>
-<li>Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.</li>
-</ul></li>
-<li>Remove ‘register’ storage class specifier from LL TIM driver.</li>
-<li>Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral</li>
-<li>Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory</li>
-</ul></li>
-<li><strong>HAL RCC</strong> driver
-<ul>
-<li>Fix extra parentheses compilation warnings with clang compiler</li>
-<li>Update HAL_RCC_GetSysClockFreq() API to avoid the risk of rounding overflow.</li>
-</ul></li>
-<li><strong>HAL/LL UART</strong> driver
-<ul>
-<li>Update UART polling processes to handle efficiently the Lock mechanism
-<ul>
-<li>Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.</li>
-</ul></li>
-<li>Update UART interruption handler to manage correctly the overrun interrupt
-<ul>
-<li>Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.</li>
-</ul></li>
-<li>Update UART BRR calculation for ROM size gain</li>
-</ul></li>
-<li><strong>HAL/LL USART</strong> driver
-<ul>
-<li>Update some API description
-<ul>
-<li>HAL_USART_Transmit() / HAL_USART_Transmit_IT()
-<ul>
-<li>HAL_USART_Receive() / HAL_USART_Receive_IT()</li>
-<li>HAL_USART_TransmitReceive() / HAL_USART_TransmitReceive_IT()</li>
-<li>HAL_USART_Transmit_DMA() / HAL_USART_Receive_DMA() / HAL_USART_TransmitReceive_DMA()</li>
-</ul></li>
-</ul></li>
-<li>Update USART interruption handler to manage correctly the overrun interrupt
-<ul>
-<li>Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL USB</strong> driver
-<ul>
-<li>Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory</li>
-<li>Bug fix: correct USB RX count calculation</li>
-<li>Fix USB Bulk transfer double buffer mode</li>
-<li>Remove register keyword from USB defined macros as no more supported by C++ compiler</li>
-<li>Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API.</li>
-</ul></li>
-<li><strong>LL UTILS</strong> driver
-<ul>
-<li>Add new LL API LL_SetFlashLatency() to set Flash latency.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.4.0 / 05-April-2019</label>
-<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance release</h3>
-<ul>
-<li>Add support of <strong>HAL callback registration</strong> feature</li>
-<li>Add several enhancements implementation</li>
-<li>Fix known defects to be aligned with others STM32 series</li>
-</ul>
-<h2 id="contents-4">Contents</h2>
-<ul>
-<li><strong>HAL/LL</strong> generic
-<ul>
-<li><p>Add support of <strong>HAL callback registration</strong> feature</p></li>
-<li><p>The feature <strong>disabled by default</strong> is available for the following HAL drivers:</p>
-<ul>
-<li><strong>ADC, COMP, DAC, I2C, I2S, IRDA, LPTIM, PCD, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART</strong> and <strong>WWDG</strong></li>
-</ul></li>
-<li><p>The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32l1xx_hal_conf.h project configuration file (template file stm32l1xx_hal_conf_template.h available from Drivers/STM32L1xx_HAL_Driver/Inc)</p></li>
-<li><p>Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().</p></li>
-<li><p>Update HAL/LL Driver compliancy with MISRA C 2012 rules</p></li>
-<li><p>stm32l1xx_hal_def.h</p>
-<ul>
-<li>Update file to avoid compiler warnings from __packed definitions</li>
-<li>Update UNUSED() macro to fix compilation warning with g++ compiler</li>
-<li>Replace include stdio.h by stddef.h</li>
-<li>Update __RAM_FUNC define to not impose function type</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL</strong> driver
-<ul>
-<li>Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() for 96-bit UID</li>
-<li>Modify default HAL_Delay implementation to guarantee minimum delay</li>
-<li>Update Doxygen tags in macros description to have generate correct CHM format</li>
-<li>Update implementation of HAL_SetTickFreq() function</li>
-</ul></li>
-<li><strong>HAL ADC</strong> driver
-<ul>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_ADC_RegisterCallback() and HAL_ADC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_ADC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Remove unused code in HAL_ADC_Stop_DMA() function.</li>
-</ul></li>
-<li><strong>HAL/LL COMP</strong> driver
-<ul>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_COMP_RegisterCallback() and HAL_COMP_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_COMP_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Update define for COMP_NONINVERTINGINPUT_PA6</li>
-<li>Update define for LL_COMP_INPUT_PLUS_IO11</li>
-<li>Correct issue with input plus COMP1 in windowmode</li>
-<li>Add missing LL function for COMP_CSR-&gt;VREFOUTEN bit</li>
-</ul></li>
-<li><strong>HAL CRC</strong> driver
-<ul>
-<li>Align HAL/LL CRC driver with latest updates and enhancements</li>
-<li>Update CRC driver to remove not applicable InputDataFormat</li>
-</ul></li>
-<li><strong>HAL DAC</strong> driver
-<ul>
-<li>Align HAL/LL DAC driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_DAC_RegisterCallback() and HAL_DAC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_DAC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL DMA</strong> driver
-<ul>
-<li>Align HAL/LL DMA drivers with latest updates and enhancements</li>
-<li>Add missing APIs to register/unregister DMA callbacks</li>
-</ul></li>
-<li><strong>HAL FLASH</strong> driver
-<ul>
-<li>Update HAL_FLASH_Unlock() and HAL_FLASH_OB_Unlock() in order the functions do not return an error when already unlocked</li>
-<li>Update HAL_FLASHEx_ProgramParallelHalfPage(), HAL_FLASHEx_HalfPageProgram(), HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(), HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord() so that the functions should not be restricted to privilege mode</li>
-<li>Update FLASH_OB_GetRDP() function to return the correct RDP level</li>
-<li>Update FLASH_OB_GetUser() and FLASH_OB_UserConfig() to use the combination of specific masks FLASH_OBR_IWDG_SW, FLASH_OBR_nRST_STOP and FLASH_OBR_nRST_STDBY</li>
-</ul></li>
-<li><strong>HAL GPIO</strong> driver
-<ul>
-<li>Update HAL_GPIO_DeInit() function to perform EXTI configuration reset before GPIO configuration</li>
-<li>Improve robustness of HAL_GPIO_TogglePin() function</li>
-<li>Update definition of IS_GPIO_PIN to remove compilation warning with IAR tool chain</li>
-<li>Update usage description for HAL_GPIO_LockPin() to justify an unused read of a register</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong> driver
-<ul>
-<li>Align HAL/LL I2C driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_I2C_RegisterCallback(), HAL_I2C_UnRegisterCallback(), HAL_I2C_RegisterAddrCallback() and HAL_I2C_UnRegisterAddrCallback() APIs</li>
-<li>Add callback identifiers in HAL_I2C_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Add I2C_FIRST_AND_NEXT_FRAME for I2C Sequential transfer options: allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call to the same master sequential interface several times.</li>
-<li>Add reset on slave LISTEN_TX state in case of direction change</li>
-<li>Remove unused variable in HAL_I2C_Slave_Transmit_IT/DMA() and HAL_I2C_Slave_Receive_IT/DMA() functions to avoid warning compilation with linux tool chain</li>
-<li>Add I2C slave enhancement with the functions: HAL_I2C_Master_Sequential_Transmit_DMA(), HAL_I2C_Master_Sequential_Receive_DMA(), HAL_I2C_Slave_Sequential_Transmit_DMA(), HAL_I2C_Slave_Sequential_Receive_DMA() functions</li>
-<li>Update HAL_I2C_Master_Seq_Transmit_IT(DMA), HAL_I2C_Master_Seq_Receive_IT(DMA) functions.
-<ul>
-<li>Update comments about Device Address parameter (DevAddress) description in I2C functions header</li>
-<li>Add restart condition for each call of HAL_I2C_Master_Seq_xxxx_IT</li>
-<li>Fix MISRAC2012 issue
-<ul>
-<li>Renamed HAL_I2C_Master_Sequential_Transmit_IT(DMA) to HAL_I2C_Master_Seq_Transmit_IT(DMA)</li>
-<li>Renamed HAL_I2C_Master_Sequential_Receive_IT(DMA) to HAL_I2C_Master_Seq_Receive_IT(DMA)</li>
-<li>Renamed HAL_I2C_Slave_Sequential_Transmit_IT(DMA) to HAL_I2C_Slave_Seq_Transmit_IT(DMA)</li>
-<li>Renamed HAL_I2C_Slave_Sequential_Receive_IT(DMA) to HAL_I2C_Slave_Seq_Receive_IT(DMA)</li>
-</ul></li>
-</ul></li>
-<li>Update ErrorCode to correct wrong returned value after waiting until BUSY flag is reset</li>
-</ul></li>
-<li><strong>HAL I2S</strong> driver
-<ul>
-<li>Align HAL I2S driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_I2S_RegisterCallback() and HAL_I2S_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_I2S_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL IRDA</strong> driver
-<ul>
-<li>Align HAL IRDA driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_IRDA_RegisterCallback() and HAL_IRDA_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_IRDA_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Review IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ</li>
-<li>Implement new APIs for HAL IRDA Abort management:
-<ul>
-<li>HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()</li>
-</ul></li>
-<li>Optimize WaitOnFlag management in IRDA_Transmit() function</li>
-<li>Optimize all HAL IRQ Handler routines</li>
-<li>Optimize HAL IRDA to avoid using macros as argument of function calls</li>
-</ul></li>
-<li><strong>HAL OPAMP</strong> driver
-<ul>
-<li>Align HAL OPAMP driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_OPAMP_RegisterCallback() and HAL_OPAMP_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_OPAMP_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL RCC</strong> driver
-<ul>
-<li>Replace __HAL_RCC_CRYP_CLK_ENABLE by __HAL_RCC_AES_CLK_ENABLE</li>
-<li>Change HAL_RCC_DeInit() to HAL_StatusTypeDef</li>
-<li>Update HAL_RCC_DeInit() and LL_RCC_DeInit() to also clear interrupts and reset flags</li>
-<li>Update HAL_RCC_DeInit() and LL_RCC_DeInit() to add check on PLLRDY before clearing PLLCFGR register</li>
-<li>Update HAL_RCC_DeInit() to insure that default MSI range is set prior to enable MSI and use it as SYSCLK source</li>
-<li>Update LL_RCC_DeInit() to add the key word volatile and avoid compilation issue with gcc -O3</li>
-<li>Remove LSI_VALUE definition from stm32l1xx_hal_rcc_ex.h to have it declared in HAL Generic stm32l1xx_hal_conf_template.h/stm32l1xx_hal_conf.h as other families STM32 HAL drivers</li>
-<li>Correct LSI_VALUE LL definition in stm32l1xx_ll_rcc.h</li>
-<li>Update HAL_RCC_OscConfig() to avoid MCU hangs after some stop/wakeup cycles</li>
-<li>Replace all calls to HAL_InitTick(TICK_INT_PRIORITY) with HAL_InitTick(uwTickPrio) to avoid Tick priority overwrite</li>
-<li>Add new LL_RCC_PLL_SetMainSource macro to set the PLL source without enabling any PLL</li>
-</ul></li>
-<li><strong>HAL/LL RTC</strong> driver
-<ul>
-<li>Align HAL/LL RTC driver with latest updates and enhancements</li>
-<li>Remove unused value in HAL_RTC_SetTime() function</li>
-<li>Update implementation of LL_RTC_DATE_Get() function</li>
-<li>Correct issue in the argument of LL_RTC_ALMB_SetDay() function</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_RTC_RegisterCallback() and HAL_RTC_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_RTC_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SDMMC</strong> driver
-<ul>
-<li>Align HAL SDMMC driver with latest updates and enhancements</li>
-<li><strong>Due to limitation <em>SDIO hardware flow control</em> indicated in Errata Sheet</strong> :
-<ul>
-<li>In 4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or HAL_SD_WriteBlocks() APIs otherwise underrun will occur and there is not possibility to activate the flow control</li>
-<li>Use DMA mode when using 4-bits bus wide mode or decrease the frequency</li>
-</ul></li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SD_RegisterCallback(),HAL_SD_UnRegisterCallback(), HAL_SD_RegisterTransceiverCallback() and HAL_SD_UnRegisterTransceiverCallback APIs</li>
-<li>Add callback identifiers in HAL_SD_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL SMARTCARD</strong> driver
-<ul>
-<li>Align HAL SMARTCARD driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SMARTCARD_RegisterCallback() and HAL_SMARTCARD_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_SMARTCARD_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Review SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ</li>
-<li>Implement new APIs for HAL SMARTCARD Abort management:
-<ul>
-<li>HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()</li>
-</ul></li>
-<li>Optimize WaitOnFlag management in SMARTCARD_Transmit() function</li>
-<li>Optimize all HAL IRQ Handler routines</li>
-<li>Optimize HAL SMARTCARD to avoid using macros as argument of function calls</li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong> driver
-<ul>
-<li>Align HAL/LL SPI driver with latest updates and enhancements</li>
-<li><strong>Backward compatibility</strong>:
-<ul>
-<li>Remove <strong>stm32l1xx_hal_spi_ex.c/.h</strong> files and move the functions/definitions to stm32l1xx_hal_spi.c/.h</li>
-<li>The user projects must be updated to remove <strong>stm32l1xx_hal_spi_ex.c/.h</strong> from files list</li>
-</ul></li>
-<li>Fix issue in HAL_SPI_Transmit() and HAL_SPI_TransmitReceive() functions</li>
-<li>Update HAL/LL SPI driver to manage TI mode not supported by all STM32L1xx devices</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_SPI_RegisterCallback() and HAL_SPI_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_SPI_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong> driver
-<ul>
-<li>Align HAL/LL TIM driver with latest updates and enhancements</li>
-<li>Add support of preload control in HAL TIM API</li>
-<li>Remove TIM_CHANNEL_4 argument from description of HAL_TIMEx_OCN_xxx() and HAL_TIMEx_PWMN_xxxx() functions</li>
-<li>Update comments in HAL/LL functions to describe how to switch from Center Aligned counter mode to Edge Aligned Down mode</li>
-<li>Remove OCIdleState from TIM_OC_InitTypeDef and TIM_OnePulse_InitTypeDef</li>
-<li>Update behavior of LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent() functions</li>
-<li>Add callback registration feature + Add HAL_TIM_RegisterCallback() and HAL_TIM_UnRegisterCallback() APIs + Add callback identifiers in HAL_TIM_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li><strong>HAL UART/USART</strong> driver
-<ul>
-<li>Align HAL UART/USART driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_UART/USART_RegisterCallback() and HAL_UART/USART_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_UART/USART_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-<li>Add missing __IO in UART/USART_HandleTypeDef definition (for TxXferCount and RxXferCount)</li>
-<li>Review UART/USART state machine to avoid cases where UART/USART state is overwritten by UART/USART IRQ</li>
-<li>Implement new APIs for HAL UART/USART Abort management:
-<ul>
-<li>HAL_UART/USART_Abort(), HAL_UART/USART_AbortTransmit(), HAL_UART/USART_AbortReceive(), HAL_UART/USART_Abort_IT(), HAL_UART/USART_AbortTransmit_IT(), HAL_UART/USART_AbortReceive_IT()</li>
-</ul></li>
-<li>Optimize WaitOnFlag management in UART/USART_Transmit() function</li>
-<li>Optimize all HAL IRQ Handler routines</li>
-<li>Align __HAL_UART_GET_IT and __HAL_UART_GET_IT_SOURCE with other series</li>
-<li>Optimize HAL UART/USART to avoid using macros as argument of function calls</li>
-<li>Update USART BRR calculation</li>
-</ul></li>
-<li><strong>HAL USB</strong> driver
-<ul>
-<li>Align HAL USB driver with latest updates and enhancements</li>
-<li>Upgrade to USB Device Library v2.5.2</li>
-<li>Fix issue with Buffer Overflow in PCD_ReadPMA() function</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_PCD_RegisterCallback(),HAL_PCD_UnRegisterCallback(), HAL_PCD_RegisterDataOutStageCallback(), HAL_PCD_UnRegisterDataOutStageCallback(), HAL_PCD_RegisterDataInStageCallback(), HAL_PCD_UnRegisterDataInStageCallback(), HAL_PCD_RegisterIsoOutIncpltCallback(), HAL_PCD_UnRegisterIsoOutIncpltCallback(), HAL_PCD_RegisterIsoInIncpltCallback(), HAL_PCD_UnRegisterIsoInIncpltCallback(), HAL_PCD_RegisterBcdCallback(), HAL_PCD_UnRegisterBcdCallback(), HAL_PCD_RegisterLpmCallback() and HAL_PCD_UnRegisterLpmCallback() APIs</li>
-<li>Add callback identifiers in HAL_PCD_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-<li><strong>LL UTILS</strong> driver
-<ul>
-<li>Correct LL_GetUID_Word2 function to fix error in UID flash location</li>
-<li>Fix mismatch return type in LL_GetPackageType(void)</li>
-</ul></li>
-<li><strong>HAL WWDG</strong> driver
-<ul>
-<li>Align HAL WWDG driver with latest updates and enhancements</li>
-<li>Add callback registration feature
-<ul>
-<li>Add HAL_WWDG_RegisterCallback() and HAL_WWDG_UnRegisterCallback() APIs</li>
-<li>Add callback identifiers in HAL_WWDG_CallbackIDTypeDef enumerated typedef</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.3.1 / 25-August-2017</label>
-<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="patch-release">Patch release</h3>
-<h2 id="contents-5">Contents</h2>
-<ul>
-<li><strong>HAL/LL</strong> generic
-<ul>
-<li>Remove DATE and VERSION fields from header files</li>
-<li>Update CHM User Manual for Drivers/STM32L1xx_HAL_Driver</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.3.0 / 21-April-2017</label>
-<div>
-<h2 id="main-changes-6">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance release</h3>
-<h2 id="contents-6">Contents</h2>
-<ul>
-<li><strong>HAL/LL</strong> generic
-<ul>
-<li>Enhanced HAL delay and time base implementation:
-<ul>
-<li>Added new templates stm32l1xx_hal_timebase_tim_template.c which can be used to override the native HAL time base functions (defined as weak) and to use Timer as time base tick source.</li>
-<li>For more details about the usage of these drivers, please refer to HAL_TimeBase_TIM examples and FreeRTOS-based applications.</li>
-</ul></li>
-<li>Updated HAL Driver compliancy with MISRA C 2004 rules:
-<ul>
-<li>MISRA C 2004 rule 10.3 (illegal explicit conversion from type “unsigned int” to "uint16_t *)</li>
-<li>MISRA C 2004 rule 10.5 (if the bitwise operators ~ and &lt;&lt; are applied to an operand of underlying type ‘unsigned char’ or ‘unsigned short’, the result shall be immediately cast to the underlying type of the operand)</li>
-<li>MISRA C 2004 rule 11.4 (cast should not be performed between a pointer to object type and a different pointer to object type)</li>
-<li>MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators)</li>
-<li>MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types)</li>
-<li>MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself)</li>
-</ul></li>
-<li>Removed (uint32_t) cast when “U” is used in order to avoid double definitions.</li>
-<li>Replaced hard coded POSITION definition in HAL/LL drivers by the associated PPP_xxx_pos CMSIS define.</li>
-</ul></li>
-<li><strong>HAL CORTEX</strong>
-<ul>
-<li>Updated HAL_MPU_Disable function to clear whole CR register.</li>
-</ul></li>
-<li><strong>LL DMA</strong>
-<ul>
-<li>Improved CPAR and CMAR registers access in LL_DMA_ConfigAddresses function.</li>
-</ul></li>
-<li><strong>HAL FLASH</strong>
-<ul>
-<li>Updated HAL_FLASHEx_Erase_IT() function to check the FLASH is ready before starting Erase by IT.</li>
-</ul></li>
-<li><strong>HAL/LL GPIO</strong>
-<ul>
-<li>Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit to GPIO_AFRL_AFSELx.</li>
-</ul></li>
-<li><strong>HAL/LL I2C</strong>
-<ul>
-<li>Added LL_I2C_DisableReset() function to allow the disable of SWRST.</li>
-</ul></li>
-<li><strong>HAL PCD</strong>
-<ul>
-<li>Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.</li>
-<li>Added missing USB_CNTR_SOFM in the setting of wInterrupt_Mask global variable used in HAL_PCD_Init.</li>
-<li>Removed lock/unlock from receive and transmit endpoints.</li>
-</ul></li>
-<li><strong>HAL/LL PWR</strong>
-<ul>
-<li>Replaced HAL_PWREx_GetVoltageRange() function by direct register access to remove dependency with HAL PWR.</li>
-<li>Renamed the LL_PWR_IsActiveFlag_VOSF() API to LL_PWR_IsActiveFlag_VOS() in order to remove reference to PWR flag name and to refer to the Power feature.</li>
-</ul></li>
-<li><strong>HAL/LL RTC</strong>
-<ul>
-<li>Renamed RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.</li>
-</ul></li>
-<li><strong>HAL/LL SPI</strong>
-<ul>
-<li>Removed LL_SPI_SR_UDR define which is available only for I2S feature.</li>
-<li>Updated LL_SPI_TransmitData16() et LL_SPI_TransmitData8 functions.</li>
-</ul></li>
-<li><strong>HAL/LL TIM</strong>
-<ul>
-<li>Corrected error in LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent() functions.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.2.0 / 01-July-2016</label>
-<div>
-<h2 id="main-changes-7">Main Changes</h2>
-<h3 id="maintenance-release-6">Maintenance release</h3>
-<ul>
-<li>First official release supporting the <strong>Low Level</strong> drivers for the <strong>STM32L1xx</strong> family:
-<ul>
-<li>Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L1xx Reference Manual.</li>
-<li>Low Layer drivers are available for: ADC, COMP, CORTEX, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, OPAMP, PWR, RCC, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs.</li>
-<li>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l1xx_ll_ppp.h file must be included in user code.</li>
-</ul></li>
-</ul>
-<h2 id="contents-7">Contents</h2>
-<ul>
-<li><strong>Generic updates</strong>
-<ul>
-<li>Update HAL drivers to apply MISRA C 2004 rule 10.6.</li>
-<li>uwTick must be global and not static to allow overwrite of HAL_IncTick()</li>
-</ul></li>
-<li><strong>ADC</strong>
-<ul>
-<li>Clear the bit OVR (overrun) in addition to EOC (end of conversion) inside HAL_ADC_Start, HAL_ADC_Start_IT and HAL_ADC_Start_DMA.</li>
-</ul></li>
-<li><strong>CRC</strong>
-<ul>
-<li>HAL_CRC_DeInit() resets CRC_IDR register to reset value.</li>
-</ul></li>
-<li><strong>DMA</strong>
-<ul>
-<li>Add function HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma).</li>
-<li>This function aborts the DMA Transfer in Interrupt mode.</li>
-<li>Add macro __HAL_DMA_GET_COUNTER</li>
-<li>This macro permits to get the number of remaining data units in the current DMAy Channelx transfer.</li>
-<li>Global driver code optimization to reduce memory footprint</li>
-</ul></li>
-<li><strong>FLASH</strong>
-<ul>
-<li>Correct MISRA 10.3 Error[Pm069]: if identifiers are given for any of the parameters, then the identifiers used in the declaration and definition shall be identical (MISRA C 2004 rule 16.4).</li>
-</ul></li>
-<li><strong>GPIO</strong>
-<ul>
-<li>IS_GPIO_PIN is more robust.</li>
-</ul></li>
-<li><strong>I2C</strong>
-<ul>
-<li>WaitOnFlag is optimized to effectively last until the expected timeout of a transfer.</li>
-<li>Optimisation of the IRQHandler.</li>
-<li>Rework DMA end process and I2C error management during DMA transfer.</li>
-<li>HAL_I2C_Master_Transmit_DMA now returns an error in case of communication error.</li>
-<li>Add support for repeated start feature.</li>
-</ul></li>
-<li><strong>IWDG</strong>
-<ul>
-<li>New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs</li>
-<li>API functions are:</li>
-<li>HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter</li>
-<li>HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter</li>
-<li>Refer to the following example to identify the changes: IWDG_Example</li>
-</ul></li>
-<li><strong>PWR</strong>
-<ul>
-<li>Add new interface HAL_FLASHEx_GetError.</li>
-<li>Add constant FLASH_SIZE.</li>
-<li>Use suffix U for all the defines.</li>
-<li>HAL_PWREx_DisableLowPowerRunMode now returns HAL_StatusTypeDef instead of void.</li>
-<li>SB and ADDR are now managed in interrupt mode, not in polling.</li>
-<li>Add DMA abort treatment</li>
-</ul></li>
-<li><strong>RCC</strong>
-<ul>
-<li>Rework the correction from V1.1.3:
-<ul>
-<li>Backup domain are no more reseted when RTC clock source is changed from reset value.</li>
-</ul></li>
-</ul></li>
-<li><strong>RTC</strong>
-<ul>
-<li>Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.</li>
-</ul></li>
-<li><strong>SPI</strong>
-<ul>
-<li>Correct MISRA 5.2 “tmpreg” variable shall not be used inside MACRO.</li>
-<li>In the SPI_HandleTypeDef structure, RxXferCount and TxXferCount are now __IO.</li>
-<li>Clear the OVR flag before a new transfer.</li>
-</ul></li>
-<li><strong>TIMER</strong>
-<ul>
-<li>Correct the description of the function HAL_TIM_PWM_Start_IT.
-<ul>
-<li>The parameter Channel mentions the channel to be enabled and not the one to be disabled.</li>
-</ul></li>
-</ul></li>
-<li><strong>WWDG</strong>
-<ul>
-<li>New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs
-<ul>
-<li>Update HAL_WWDG_Refresh() API to remove counter parameter</li>
-<li>New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</li>
-<li>API functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</li>
-</ul></li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.1.3 / 04-March-2016</label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
-<h3 id="maintenance-release-7">Maintenance release</h3>
-<h2 id="contents-8">Contents</h2>
-<ul>
-<li><strong>Generic update</strong>
-<ul>
-<li>Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.</li>
-<li>Improve the update of the SystemCoreClock variable within the HAL Driver.</li>
-<li>Split aAPBAHBPrescTable into aAHBPrescTable and aAPBPrescTable.</li>
-<li>Reduce HSE_STARTUP_TIMEOUT from 5s to 100ms.</li>
-<li>Reduce MSI_TIMEOUT_VALUE from 100ms to 2ms.</li>
-<li>Reduce HSI_TIMEOUT_VALUE from 100ms to 2ms.</li>
-<li>Reduce LSI_TIMEOUT_VALUE from 100ms to 2ms.</li>
-<li>Reduce PLL_TIMEOUT_VALUE from 100ms to 2ms.</li>
-</ul></li>
-<li><strong>CORTEX</strong>
-<ul>
-<li>__HAL_CORTEX_SYSTICKCLK_CONFIG is now deprecated. Prefer using HAL_SYSTICK_CLKSourceConfig function.</li>
-</ul></li>
-<li><strong>FLASH</strong>
-<ul>
-<li>Correct issue preventing Cat.1 devices to write data in EEPROM.</li>
-</ul></li>
-<li><strong>I2C</strong>
-<ul>
-<li>Add NACK management during wait on flag treatment.</li>
-<li>Update the state machine.</li>
-<li>It is now possible to use the I2C transmission with a data size of 0.</li>
-</ul></li>
-<li><strong>RCC</strong>
-<ul>
-<li>Optimize HAL_RCC_ClockConfig.</li>
-<li>LSEON is reset only if required inside HAL_RCC_OscConfig.</li>
-<li>RCC HSE pre-scaler reconfiguration for LCD/RTC peripherical is now possible.</li>
-<li>Backup domain are no more reseted when RTC clock source is changed from reset value.</li>
-</ul></li>
-<li><strong>SMARTCARD</strong>
-<ul>
-<li>Update description of GuardTime and Prescaler fields in SMARTCARD_InitTypeDef structure.</li>
-</ul></li>
-<li><strong>UART</strong>
-<ul>
-<li>HAL_LIN_SendBreak() now use IS_UART_LIN_INSTANCE instead of IS_UART_INSTANCE.</li>
-<li>Correct the UART_BRR_SAMPLING8 macro in the case of cary handling.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.1.2 / 09-October-2015</label>
-<div>
-<h2 id="main-changes-9">Main Changes</h2>
-<h3 id="maintenance-release-8">Maintenance release</h3>
-<h2 id="contents-9">Contents</h2>
-<ul>
-<li><strong>ADC</strong>
-<ul>
-<li>The ADC internal macro “IS_ADC_RANGE” is modified to take into account the ADC resolution.</li>
-<li>The function HAL_ADC_PollForEvent, in case of timeout, returns HAL_TIMEOUT instead of HAL_ERROR.</li>
-<li>HAL_ADC_Init set the ADC handle in state HAL_ADC_ERROR_INTERNAL if the user try to initialize the ADC in DiscontinuousConvMode and ContinuousConvMode simultaneously, which is not possible.</li>
-<li>Enhance the check for ScanConvMode in HAL_ADC_Init.</li>
-</ul></li>
-<li><strong>Cortex</strong>
-<ul>
-<li>Corrected Misra error (MISRA C 2004 rule 10.5).</li>
-</ul></li>
-<li><strong>CRC</strong>
-<ul>
-<li>Corrected the macro __HAL_CRC_SET_IDR.</li>
-</ul></li>
-<li><strong>GPIO</strong>
-<ul>
-<li>Corrected the macro GPIO_GET_INDEX.</li>
-<li>To insure the same naming accross all STM32 families (F4, F2, F0, F1, L1 etc):
-<ul>
-<li>Replacing GPIO_SPEED_VERY_LOW by GPIO_SPEED_FREQ_LOW.</li>
-<li>Replacing GPIO_SPEED_LOW by GPIO_SPEED_FREQ_MEDIUM.</li>
-<li>Replacing GPIO_SPEED_MEDIUM by GPIO_SPEED_FREQ_HIGH.</li>
-<li>Replacing GPIO_SPEED_HIGH by GPIO_SPEED_FREQ_VERY_HIGH.</li>
-</ul></li>
-</ul></li>
-<li><strong>IRDA</strong>
-<ul>
-<li>Corrected the HAL_IRDA_IRQHandler which was preventing to handle 2 simultaneous errors.</li>
-</ul></li>
-<li><strong>I2C</strong>
-<ul>
-<li>Corrected an issue where the STOP bit was not cleared after reading data depending on APB/I2C frequency.</li>
-</ul></li>
-<li><strong>I2S</strong>
-<ul>
-<li>HAL_I2S_Transmit() is updated to keep the check on busy flag only for the slave.</li>
-</ul></li>
-<li><strong>PCD</strong>
-<ul>
-<li>Corrected issue when using USB Device double-buffering mode for IN endpoints.</li>
-<li>do{ … } while(0) is used for multi statement macros.</li>
-</ul></li>
-<li><strong>PWR</strong>
-<ul>
-<li>Corrected Misra error (MISRA C 2004 rule 14.3).</li>
-</ul></li>
-<li><strong>RCC</strong>
-<ul>
-<li>In HAL_RCCEx_PeriphCLKConfig, the reset of the backup domain occurs only if the RTC clock source has been changed.</li>
-<li>__HAL_RCC_HSE_CONFIG is updated to remove the transition from RCC_HSE_ON to RCC_HSE_BYPASS.</li>
-<li>Adding the macro __HAL_RCC_MCO1_CONFIG to configure the MCO clock.</li>
-<li>Adding the macros and function to handle LSE CSS interrupt.</li>
-<li>Corrected an error in HAL_RCC_GetSysClockFreq when the PLL is used as system clock. An incorrect sysclockfreq was returned.</li>
-</ul></li>
-<li><strong>RTC</strong>
-<ul>
-<li>RTC_TimeTypeDef.SecondFraction field is added to specifies the range or granularity of Sub Second register content.This field will be used only by HAL_RTC_GetTime function.</li>
-<li>HAL_RTC_GetTime is updated to take into account the new field RTC_TimeTypeDef.SecondFraction.</li>
-<li>Corrected error in __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG macro.</li>
-<li>Add additionnal checks on WUTWF flag in HAL_RTCEx_SetWakeUpTimer_IT.</li>
-<li>do{ … } while(0) is used for multi statement macros.</li>
-</ul></li>
-<li><strong>USART</strong>
-<ul>
-<li>Corrected the HAL_USART_IRQHandler which was preventing to handle 2 simultaneous errors.</li>
-</ul></li>
-<li><strong>UART</strong>
-<ul>
-<li>Removed the activation of ERR IT from HAL_UART_Transmit_IT() which was leading to HAL_UART_IRQ_Handler wrong behavior.</li>
-<li>Corrected the HAL_UART_IRQHandler which was preventing to handle 2 simultaneous errors.</li>
-</ul></li>
-<li><strong>SMARTCARD</strong>
-<ul>
-<li>Corrected the HAL_SMARTCARD_IRQHandler which was preventing to handle 2 simultaneous errors.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 31-March-2015</label>
-<div>
-<h2 id="main-changes-10">Main Changes</h2>
-<h3 id="maintenance-release-9">Maintenance release</h3>
-<ul>
-<li>Include path changes for compilation under Unix environment</li>
-<li>Update drivers to be C++ compliant</li>
-</ul>
-<h2 id="contents-10">Contents</h2>
-<ul>
-<li><strong>CORTEX</strong>
-<ul>
-<li>Added interface to access MPU features (refer to stm32l1xx_hal_cortex.h)</li>
-</ul></li>
-<li><strong>CRYP</strong>
-<ul>
-<li>Added Instance field in CRYP_HandleTypeDef.
-<ul>
-<li>HAL CRYP driver updated to support multi instance, so user must ensure that the new parameter Instance is initialized in his application (CRYPHandle.Instance = CRYP)</li>
-</ul></li>
-</ul></li>
-<li><strong>FLASH</strong>
-<ul>
-<li>Changing field name of NOR_CFITypeDef (CFI1X changed to CFI1_X)</li>
-</ul></li>
-<li><strong>PCD</strong>
-<ul>
-<li>HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup</li>
-<li>HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup</li>
-</ul></li>
-<li><strong>PWR</strong>
-<ul>
-<li>HAL_PWR_PVDConfig renamed HAL_PWR_ConfigPVD</li>
-<li>Added new interfaces:
-<ul>
-<li>void HAL_PWR_EnableSleepOnExit(void);</li>
-<li>void HAL_PWR_DisableSleepOnExit(void);</li>
-<li>void HAL_PWR_EnableSEVOnPend(void);</li>
-<li>void HAL_PWR_DisableSEVOnPend(void);</li>
-<li>void HAL_PWR_EnableSleepOnExit(void);</li>
-<li>uint32_t HAL_PWREx_GetVoltageRange(void);</li>
-</ul></li>
-</ul></li>
-<li><strong>RCC</strong>
-<ul>
-<li>HAL_RCC_CCSCallback renamed to HAL_RCC_CSSCallback</li>
-<li>Adding HAL_RCCEx_GetPeriphCLKFreq interface.</li>
-</ul></li>
-<li><strong>SMARTCARD</strong>
-<ul>
-<li>Removal of HAL_SMARTCARD_ReInit interface.</li>
-</ul></li>
-<li><strong>SPI</strong>
-<ul>
-<li>HAL_SPI_GetError now returns a uint32_t instead of HAL_SPI_ErrorTypeDef.</li>
-</ul></li>
-<li><strong>TIMER</strong>
-<ul>
-<li>Adding interface HAL_TIM_SlaveConfigSynchronization_IT</li>
-</ul></li>
-<li><strong>UART</strong>
-<ul>
-<li>The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.</li>
-</ul></li>
-<li><strong>USART</strong>
-<ul>
-<li>The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2015</label>
-<div>
-<h2 id="main-changes-11">Main Changes</h2>
-<h3 id="maintenance-release-10">Maintenance release</h3>
-<ul>
-<li>Add support of new <strong>STM32L1 eXtended devices</strong> - <strong>STM32l151xDX, STM32l152xDX &amp; STM32l62xDX</strong></li>
-</ul>
-<h2 id="contents-11">Contents</h2>
-<ul>
-<li><strong>HAL</strong> generic
-<ul>
-<li>Add eXtended Devices switchs when needed
-<ul>
-<li>STM32L151xDX has same features than STM32L151xE</li>
-<li>STM32L152xDX has same features than STM32L152xE</li>
-<li>STM32L162xDX has same features than STM32L162xE</li>
-</ul></li>
-</ul></li>
-<li><strong>HAL FLASH</strong>
-<ul>
-<li>Add support of new STM32L1 Devices (same as other HAL)</li>
-<li>stm32l1xx_hal_flash_ex.c : Specific treatment done in HAL_FLASHEx_Erase and HAL_FLASHEx_Erase_IT as memory is not continuous between 2 banks, user should perform pages erase by bank only</li>
-</ul></li>
-</ul>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 05-September-2014</label>
-<h2 id="main-changes-12">Main Changes</h2>
-<h3 id="first-official-release">First official release</h3>
-</div>
-</section>
-</div>
-<footer class="sticky">
-For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
-</footer>
-</body>
-</html>
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c
deleted file mode 100644
index 9d0f706e0b8..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal.c
-  * @author  MCD Application Team
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL.
-    [..]
-    The HAL contains two APIs categories:
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Defines HAL Private Defines
-  * @{
-  */
-
-/**
- * @brief STM32L1xx HAL Driver version number V1.4.4
-   */
-#define __STM32L1xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L1xx_HAL_VERSION_SUB1   (0x04) /*!< [23:16] sub1 version */
-#define __STM32L1xx_HAL_VERSION_SUB2   (0x04) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L1xx_HAL_VERSION         ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
-                                        |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
-                                        |(__STM32L1xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK    (0x00000FFFU)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/* Exported variables --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
-  * @{
-  */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
-uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..]  This section provides functions allowing to:
-      (+) Initialize the Flash interface, the NVIC allocation and initial clock
-          configuration. It initializes the source of time base also when timeout
-          is needed and the backup domain when enabled.
-      (+) De-initialize common part of the HAL.
-      (+) Configure the time base source to have 1ms time base with a dedicated
-          Tick interrupt priority.
-        (++) SysTick timer is used by default as source of time base, but user
-             can eventually implement his proper time base source (a general purpose
-             timer for example or other time source), keeping in mind that Time base
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically
-             at the beginning of the program after reset by HAL_Init() or at any time
-             when clock is configured, by HAL_RCC_ClockConfig().
-        (++) Source of time base is configured  to generate interrupts at regular
-             time intervals. Care must be taken if HAL_Delay() is called from a
-             peripheral ISR process, the Tick interrupt line must have higher priority
-            (numerically lower) than the peripheral interrupt. Otherwise the caller
-            ISR process will be blocked.
-       (++) functions affecting time base configurations are declared as __weak
-             to make  override possible  in case of other  implementations in user file.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function configures the Flash prefetch,
-  *        configures time base source, NVIC and Low level hardware
-  * @note This function is called at the beginning of program after reset and before
-  *       the clock configuration
-  * @note The time base configuration is based on MSI clock when exiting from Reset.
-  *       Once done, time base tick start incrementing.
-  *        In the default implementation,Systick is used as source of time base.
-  *        the tick variable is incremented each 1ms in its ISR.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  HAL_StatusTypeDef  status = HAL_OK;
-
-  /* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
-  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Init the low level hardware */
-    HAL_MspInit();
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief This function de-initializes common part of the HAL and stops the source
-  *        of time base.
-  * @note This function is optional.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB_FORCE_RESET();
-  __HAL_RCC_AHB_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief This function configures the source of the time base:
-  *        The time source is configured to have 1ms time base with a dedicated
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals.
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
-  *       The SysTick interrupt must have higher priority (numerically lower)
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  HAL_StatusTypeDef  status = HAL_OK;
-
-  if (uwTickFreq != 0U)
-  {
-    /*Configure the SysTick to have interrupt in 1ms time basis*/
-    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
-    {
-      /* Configure the SysTick IRQ priority */
-      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-      {
-        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
-        uwTickPrio = TickPriority;
-      }
-      else
-      {
-        status = HAL_ERROR;
-      }
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-      (+) Get the unique device identifier
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick += uwTickFreq;
-}
-
-/**
-  * @brief Provide a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function returns a tick priority.
-  * @retval tick priority
-  */
-uint32_t HAL_GetTickPrio(void)
-{
-  return uwTickPrio;
-}
-
-/**
-  * @brief Set new tick Freq.
-  * @param Freq tick frequency
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
-{
-  HAL_StatusTypeDef status  = HAL_OK;
-  uint32_t prevTickFreq;
-
-  assert_param(IS_TICKFREQ(Freq));
-
-  if (uwTickFreq != Freq)
-  {
-    /* Back up uwTickFreq frequency */
-    prevTickFreq = uwTickFreq;
-
-    /* Update uwTickFreq global variable used by HAL_InitTick() */
-    uwTickFreq = Freq;
-
-   /* Apply the new tick Freq  */
-    status = HAL_InitTick(uwTickPrio);
-
-    if (status != HAL_OK)
-    {
-      /* Restore previous tick frequency */
-      uwTickFreq = prevTickFreq;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief Return tick frequency.
-  * @retval tick period in Hz
-  */
-uint32_t HAL_GetTickFreq(void)
-{
-  return uwTickFreq;
-}
-
-/**
-  * @brief This function provides minimum delay (in milliseconds) based
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(uint32_t Delay)
-{
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t wait = Delay;
-
-  /* Add a period to guaranty minimum wait */
-  if (wait < HAL_MAX_DELAY)
-  {
-    wait += (uint32_t)(uwTickFreq);
-  }
-
-  while((HAL_GetTick() - tickstart) < wait)
-  {
-  }
-}
-
-/**
-  * @brief Suspend the Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief Resume the Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief Return the HAL revision
-  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
-  return __STM32L1xx_HAL_VERSION;
-}
-
-/**
-  * @brief Return the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-  return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
-  * @brief  Return the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier 31:0 bits
-  */
-uint32_t HAL_GetUIDw0(void)
-{
-  return(READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
-  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier 63:32 bits
-  */
-uint32_t HAL_GetUIDw1(void)
-{
-  return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U))));
-}
-
-/**
-  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier 95:64 bits
-  */
-uint32_t HAL_GetUIDw2(void)
-{
-  return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions
- *  @brief    DBGMCU Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### DBGMCU Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c
deleted file mode 100644
index a1d8ff05455..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c
+++ /dev/null
@@ -1,2409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc.c
-  * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of regular
-  *                group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Channels configuration on regular group
-  *             ++ Channels configuration on injected group
-  *             ++ Analog Watchdog configuration
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *          Other functions (extended functions) are available in file 
-  *          "stm32l1xx_hal_adc_ex.c".
-  *
-  @verbatim
-  ==============================================================================
-                     ##### ADC peripheral features #####
-  ==============================================================================
-  [..]
-  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
-
-  (+) Interrupt generation at the end of regular conversion, end of injected
-      conversion, and in case of analog watchdog or overrun events.
-  
-  (+) Single and continuous conversion modes.
-  
-  (+) Scan mode for conversion of several channels sequentially.
-  
-  (+) Data alignment with in-built data coherency.
-  
-  (+) Programmable sampling time (channel wise)
-  
-  (+) ADC conversion of regular group and injected group.
-  
-  (+) External trigger (timer or EXTI) with configurable polarity
-      for both regular and injected groups.
-  
-  (+) DMA request generation for transfer of conversions data of regular group.
-  
-  (+) ADC offset on injected channels
-  
-  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
-      slower speed.
-  
-  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
-      Vdda or to an external voltage reference).
-  
-  
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-     *** Configuration of top level parameters related to ADC ***
-     ============================================================
-     [..]
-
-    (#) Enable the ADC interface
-      (++) As prerequisite, ADC clock must be configured at RCC top level.
-           Caution: On STM32L1, ADC clock frequency max is 16MHz (refer
-                    to device datasheet).
-                    Therefore, ADC clock prescaler must be configured in 
-                    function of ADC clock source frequency to remain below
-                    this maximum frequency.
-
-        (++) Two clock settings are mandatory: 
-             (+++) ADC clock (core clock).
-             (+++) ADC clock (conversions clock).
-                   Only one possible clock source: derived from HSI RC 16MHz oscillator
-                   (HSI). 
-                   ADC is connected directly to HSI RC 16MHz oscillator.
-                   Therefore, RCC PLL setting has no impact on ADC.
-                   PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or 
-                   enabled with HSI16 as clock source
-                   (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device 
-                   main clock source SYSCLK.
-                   The only mandatory setting is ".HSIState = RCC_HSI_ON"
-
-             (+++) Example:
-                   Into HAL_ADC_MspInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) __HAL_RCC_ADC1_CLK_ENABLE();
-
-               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
-               (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI);
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
-               (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-               (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
-               (+++) RCC_OscInitStructure.PLL.PLLSource = ...
-               (+++) RCC_OscInitStructure.PLL...
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-        (++) ADC clock prescaler is configured at ADC level with
-             parameter "ClockPrescaler" using function HAL_ADC_Init().
-
-    (#) ADC pins configuration
-         (++) Enable the clock for the ADC GPIOs
-              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
-         (++) Configure these ADC pins in analog mode
-              using function HAL_GPIO_Init()
-
-    (#) Optionally, in case of usage of ADC with interruptions:
-         (++) Configure the NVIC for ADC
-              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding ADC interruption vector 
-              ADCx_IRQHandler().
-
-    (#) Optionally, in case of usage of DMA:
-         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
-              using function HAL_DMA_Init().
-         (++) Configure the NVIC for DMA
-              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding DMA interruption vector 
-              DMAx_Channelx_IRQHandler().
-
-     *** Configuration of ADC, groups regular/injected, channels parameters ***
-     ==========================================================================
-     [..]
-
-    (#) Configure the ADC parameters (resolution, data alignment, ...)
-        and regular group parameters (conversion trigger, sequencer, ...)
-        using function HAL_ADC_Init().
-
-    (#) Configure the channels for regular group parameters (channel number, 
-        channel rank into sequencer, ..., into regular group)
-        using function HAL_ADC_ConfigChannel().
-
-    (#) Optionally, configure the injected group parameters (conversion trigger, 
-        sequencer, ..., of injected group)
-        and the channels for injected group parameters (channel number, 
-        channel rank into sequencer, ..., into injected group)
-        using function HAL_ADCEx_InjectedConfigChannel().
-
-    (#) Optionally, configure the analog watchdog parameters (channels
-        monitored, thresholds, ...)
-        using function HAL_ADC_AnalogWDGConfig().
-
-    (#) Optionally, for devices with several ADC instances: configure the 
-        multimode parameters
-        using function HAL_ADCEx_MultiModeConfigChannel().
-
-     *** Execution of ADC conversions ***
-     ====================================
-     [..]
-
-    (#) ADC driver can be used among three modes: polling, interruption,
-        transfer by DMA.
-
-        (++) ADC conversion by polling:
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start()
-          (+++) Wait for ADC conversion completion 
-                using function HAL_ADC_PollForConversion()
-                (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
-          (+++) Retrieve conversion results 
-                using function HAL_ADC_GetValue()
-                (or for injected group: HAL_ADCEx_InjectedGetValue() )
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop()
-
-        (++) ADC conversion by interruption: 
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start_IT()
-          (+++) Wait for ADC conversion completion by call of function
-                HAL_ADC_ConvCpltCallback()
-                (this function must be implemented in user program)
-                (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
-          (+++) Retrieve conversion results 
-                using function HAL_ADC_GetValue()
-                (or for injected group: HAL_ADCEx_InjectedGetValue() )
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop_IT()
-
-        (++) ADC conversion with transfer by DMA:
-          (+++) Activate the ADC peripheral and start conversions
-                using function HAL_ADC_Start_DMA()
-          (+++) Wait for ADC conversion completion by call of function
-                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
-                (these functions must be implemented in user program)
-          (+++) Conversion results are automatically transferred by DMA into
-                destination variable address.
-          (+++) Stop conversion and disable the ADC peripheral 
-                using function HAL_ADC_Stop_DMA()
-
-        (++) For devices with several ADCs: ADC multimode conversion 
-             with transfer by DMA:
-          (+++) Activate the ADC peripheral (slave) and start conversions
-                using function HAL_ADC_Start()
-          (+++) Activate the ADC peripheral (master) and start conversions
-                using function HAL_ADCEx_MultiModeStart_DMA()
-          (+++) Wait for ADC conversion completion by call of function
-                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
-                (these functions must be implemented in user program)
-          (+++) Conversion results are automatically transferred by DMA into
-                destination variable address.
-          (+++) Stop conversion and disable the ADC peripheral (master)
-                using function HAL_ADCEx_MultiModeStop_DMA()
-          (+++) Stop conversion and disable the ADC peripheral (slave)
-                using function HAL_ADC_Stop_IT()
-
-     [..]
-
-    (@) Callback functions must be implemented in user program:
-      (+@) HAL_ADC_ErrorCallback()
-      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
-      (+@) HAL_ADC_ConvCpltCallback()
-      (+@) HAL_ADC_ConvHalfCpltCallback
-      (+@) HAL_ADCEx_InjectedConvCpltCallback()
-
-     *** Deinitialization of ADC ***
-     ============================================================
-     [..]
-
-    (#) Disable the ADC interface
-      (++) ADC clock can be hard reset and disabled at RCC top level.
-        (++) Hard reset of ADC peripherals
-             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
-        (++) ADC clock disable
-             using the equivalent macro/functions as configuration step.
-             (+++) Example:
-                   Into HAL_ADC_MspDeInit() (recommended code location) or with
-                   other device clock parameters configuration:
-               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
-               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
-               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-    (#) ADC pins configuration
-         (++) Disable the clock for the ADC GPIOs
-              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
-    (#) Optionally, in case of usage of ADC with interruptions:
-         (++) Disable the NVIC for ADC
-              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
-    (#) Optionally, in case of usage of DMA:
-         (++) Deinitialize the DMA
-              using function HAL_DMA_Init().
-         (++) Disable the NVIC for DMA
-              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
-    [..]
-    
-    *** Callback registration ***
-    =============================================
-    [..]
-
-     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_ADC_RegisterCallback()
-     to register an interrupt callback.
-    [..]
-
-     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-
-     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
-     weak function.
-    [..]
-
-     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     [..]
-
-     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
-     these callbacks are null (not registered beforehand).
-    [..]
-
-     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-     [..]
-
-     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-    [..]
-
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
-     or @ref HAL_ADC_Init() function.
-     [..]
-
-     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-  /* Timeout values for ADC enable and disable settling time.                 */
-  /* Values defined to be higher than worst cases: low clocks freq,           */
-  /* maximum prescaler.                                                       */
-  /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
-  /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
-  /* Unit: ms                                                                 */
-  #define ADC_ENABLE_TIMEOUT              (2U)
-  #define ADC_DISABLE_TIMEOUT             (2U)
-
-  /* Delay for ADC stabilization time.                                        */
-  /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
-  /* Unit: us                                                                 */
-  #define ADC_STAB_DELAY_US               (3U)
-
-  /* Delay for temperature sensor stabilization time.                         */
-  /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
-  /* Unit: us                                                                 */
-  #define ADC_TEMPSENSOR_DELAY_US         (10U)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions 
-  * @brief    ADC Initialization and Configuration functions
-  *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADC peripheral and regular group according to  
-  *         parameters specified in structure "ADC_InitTypeDef".
-  * @note   As prerequisite, ADC clock must be configured at RCC top level
-  *         (clock source APB2).
-  *         See commented example code below that can be copied and uncommented 
-  *         into HAL_ADC_MspInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
-  *         coming from ADC state reset. Following calls to this function can
-  *         be used to reconfigure some parameters of ADC_InitTypeDef  
-  *         structure on the fly, without modifying MSP configuration. If ADC  
-  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
-  *         before HAL_ADC_Init().
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_InitTypeDef".
-  * @note   This function configures the ADC within 2 scopes: scope of entire 
-  *         ADC and scope of regular group. For parameters details, see comments 
-  *         of structure "ADC_InitTypeDef".
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  uint32_t tmp_cr1 = 0;
-  uint32_t tmp_cr2 = 0;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
-  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait));
-  assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff));
-  assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-    if(hadc->Init.DiscontinuousConvMode != DISABLE)
-    {
-      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
-    }
-  }
-      
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  }
-  
-  
-  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
-  /* at RCC top level.                                                        */
-  /* Refer to header of this file for more details on clock enabling          */
-  /* procedure.                                                               */
-
-  /* Actions performed only if ADC is coming from state reset:                */
-  /* - Initialization of ADC MSP                                              */
-  if (hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Initialize ADC error code */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Allocate lock resource and initialize it */
-    hadc->Lock = HAL_UNLOCKED;
-    
-    /* Enable SYSCFG clock to control the routing Interface (RI) */
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    /* Init the ADC Callback settings */
-    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
-    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
-    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
-    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
-    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
-    
-    if (hadc->MspInitCallback == NULL)
-    {
-      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
-    }
-    
-    /* Init the low level hardware */
-    hadc->MspInitCallback(hadc);
-#else
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-  }
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_BUSY_INTERNAL);
-    
-    /* Set ADC parameters */
-    
-    /* Configuration of common ADC clock: clock source HSI with selectable    */
-    /* prescaler                                                              */
-    MODIFY_REG(ADC->CCR                 ,
-               ADC_CCR_ADCPRE           ,
-               hadc->Init.ClockPrescaler );
-
-    /* Configuration of ADC:                                                  */
-    /*  - external trigger polarity                                           */
-    /*  - End of conversion selection                                         */
-    /*  - DMA continuous request                                              */
-    /*  - Channels bank (Banks availability depends on devices categories)    */
-    /*  - continuous conversion mode                                          */
-    tmp_cr2 |= (hadc->Init.DataAlign                                           |
-                hadc->Init.EOCSelection                                        |
-                ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
-                hadc->Init.ChannelsBank                                        |
-                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)     );
-
-    /* Enable external trigger if trigger selection is different of software  */
-    /* start.                                                                 */
-    /* Note: This configuration keeps the hardware feature of parameter       */
-    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-    /*       software start.                                                  */
-    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-    {
-      tmp_cr2 |= ( hadc->Init.ExternalTrigConv    |
-                  hadc->Init.ExternalTrigConvEdge );
-    }
-    
-    /* Parameters update conditioned to ADC state:                            */
-    /* Parameters that can be updated only when ADC is disabled:              */
-    /*  - delay selection (LowPowerAutoWait mode)                             */
-    /*  - resolution                                                          */
-    /*  - auto power off (LowPowerAutoPowerOff mode)                          */
-    /*  - scan mode                                                           */
-    /*  - discontinuous mode disable/enable                                   */
-    /*  - discontinuous mode number of conversions                            */
-    if ((ADC_IS_ENABLE(hadc) == RESET))
-    {
-      tmp_cr2 |= hadc->Init.LowPowerAutoWait;
-      
-      tmp_cr1 |= (hadc->Init.Resolution                     |
-                  hadc->Init.LowPowerAutoPowerOff           |
-                  ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)  );
-      
-      /* Enable discontinuous mode only if continuous mode is disabled */
-      /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter  */
-      /*       discontinuous is set anyway, but has no effect on ADC HW.      */
-      if (hadc->Init.DiscontinuousConvMode == ENABLE)
-      {
-        if (hadc->Init.ContinuousConvMode == DISABLE)
-        {
-          /* Enable the selected ADC regular discontinuous mode */
-          /* Set the number of channels to be converted in discontinuous mode */
-          SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
-                           ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)  );
-        }
-        else
-        {
-          /* ADC regular group settings continuous and sequencer discontinuous*/
-          /* cannot be enabled simultaneously.                                */
-          
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-          
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-        }
-      }
-      
-      /* Update ADC configuration register CR1 with previous settings */
-        MODIFY_REG(hadc->Instance->CR1,
-                   ADC_CR1_RES     |
-                   ADC_CR1_PDI     |
-                   ADC_CR1_PDD     |
-                   ADC_CR1_DISCNUM |
-                   ADC_CR1_DISCEN  |
-                   ADC_CR1_SCAN     ,
-                   tmp_cr1           );
-    }
-    
-    /* Update ADC configuration register CR2 with previous settings */
-    MODIFY_REG(hadc->Instance->CR2    ,
-               ADC_CR2_MASK_ADCINIT() ,
-               tmp_cr2                 );
-    
-    /* Configuration of regular group sequencer:                              */
-    /* - if scan mode is disabled, regular channels sequence length is set to */
-    /*   0x00: 1 channel converted (channel on regular rank 1)                */
-    /*   Parameter "NbrOfConversion" is discarded.                            */
-    /*   Note: Scan mode is present by hardware on this device and, if        */
-    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
-    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
-    /* - if scan mode is enabled, regular channels sequence length is set to  */
-    /*   parameter "NbrOfConversion"                                          */
-    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
-    {
-      MODIFY_REG(hadc->Instance->SQR1                         ,
-                 ADC_SQR1_L                                   ,
-                 ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion)  );
-    }
-    else
-    {
-      MODIFY_REG(hadc->Instance->SQR1,
-                 ADC_SQR1_L          ,
-                 0x00000000           );
-    }
-    
-    /* Check back that ADC registers have effectively been configured to      */
-    /* ensure of no potential problem of ADC core IP clocking.                */
-    /* Check through register CR2 (excluding execution control bits ADON,     */
-    /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL).       */
-    if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
-                                           ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
-                                           ADC_CR2_JEXTEN  | ADC_CR2_JEXTSEL   ))
-         == tmp_cr2)
-    {
-      /* Set ADC error code to none */
-      ADC_CLEAR_ERRORCODE(hadc);
-      
-      /* Set the ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_BUSY_INTERNAL,
-                        HAL_ADC_STATE_READY);
-    }
-    else
-    {
-      /* Update ADC state machine to error */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_BUSY_INTERNAL,
-                        HAL_ADC_STATE_ERROR_INTERNAL);
-      
-      /* Set ADC error code to ADC IP internal error */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-      
-      tmp_hal_status = HAL_ERROR;
-    }
-    
-  }
-  else
-  {
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Deinitialize the ADC peripheral registers to its default reset values.
-  * @note   To not impact other ADCs, reset of common ADC registers have been
-  *         left commented below.
-  *         If needed, the example code can be copied and uncommented into
-  *         function HAL_ADC_MspDeInit().
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check ADC handle */
-  if(hadc == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-  
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* ========== Reset ADC registers ========== */
-    /* Reset register SR */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
-                                ADC_FLAG_JSTRT | ADC_FLAG_STRT));
-                         
-    /* Reset register CR1 */
-    CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE   | ADC_CR1_RES     | ADC_CR1_AWDEN  |
-                                    ADC_CR1_JAWDEN  | ADC_CR1_PDI     | ADC_CR1_PDD    |
-                                    ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
-                                    ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN   |
-                                    ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE  |
-                                    ADC_CR1_AWDCH                                       ));
-    
-    /* Reset register CR2 */
-    ADC_CR2_CLEAR(hadc);
-    
-    /* Reset register SMPR0 */
-    ADC_SMPR0_CLEAR(hadc);
-    
-    /* Reset register SMPR1 */
-    ADC_SMPR1_CLEAR(hadc);
-    
-    /* Reset register SMPR2 */
-    CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | 
-                                      ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | 
-                                      ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
-                                      ADC_SMPR2_SMP10                                      ));
-    
-    /* Reset register SMPR3 */
-    CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | 
-                                      ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | 
-                                      ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
-                                      ADC_SMPR3_SMP0                                    ));
-    
-    /* Reset register JOFR1 */
-    CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
-    /* Reset register JOFR2 */
-    CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
-    /* Reset register JOFR3 */
-    CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
-    /* Reset register JOFR4 */
-    CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
-    
-    /* Reset register HTR */
-    CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
-    /* Reset register LTR */
-    CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
-    
-    /* Reset register SQR1 */
-    CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX));
-    
-    /* Reset register SQR2 */
-    CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | 
-                                     ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19  ));
-    
-    /* Reset register SQR3 */
-    CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | 
-                                     ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13  ));
-    
-    /* Reset register SQR4 */
-    CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | 
-                                     ADC_SQR4_SQ9  | ADC_SQR4_SQ8  | ADC_SQR4_SQ7   ));
-    
-    /* Reset register SQR5 */
-    CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | 
-                                     ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1  ));
-    
-    
-    /* Reset register JSQR */
-    CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL |
-                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | 
-                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  ));
-    
-    /* Reset register DR */
-    /* bits in access mode read only, no direct reset applicable*/
-    
-    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
-    /* bits in access mode read only, no direct reset applicable*/
-    
-    /* Reset register CCR */
-    CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE);   
-    
-    /* ========== Hard reset ADC peripheral ========== */
-    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
-    /* forced to a similar state after device power-on.                       */
-    /* If needed, copy-paste and uncomment the following reset code into      */
-    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
-    /*                                                                        */
-    /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
-    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */
-    
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    if (hadc->MspDeInitCallback == NULL)
-    {
-      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
-    }
-    
-    /* DeInit the low level hardware */
-    hadc->MspDeInitCallback(hadc);
-#else
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    
-    /* Set ADC error code to none */
-    ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Set ADC state */
-    hadc->State = HAL_ADC_STATE_RESET;
-    
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Initializes the ADC MSP.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the ADC MSP.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspDeInit must be implemented in the user file.
-   */ 
-}
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User ADC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = pCallback;
-        break;
-      
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = pCallback;
-        break;
-      
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = pCallback;
-        break;
-      
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = pCallback;
-        break;
-      
-      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
-        hadc->InjectedConvCpltCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-      
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Unregister a ADC Callback
-  *         ADC callback is redirected to the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
-        break;
-      
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
-        break;
-      
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
-        break;
-      
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
-        break;
-      
-      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
-        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
-        break;
-      
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
-        break;
-      
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
-        break;
-      
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
-        break;
-        
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-        
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
- *  @brief    ADC IO operation functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular group.
-      (+) Stop conversion of regular group.
-      (+) Poll for conversion complete on regular group.
-      (+) Poll for conversion event.
-      (+) Get result of regular channel conversion.
-      (+) Start conversion of regular group and enable interruptions.
-      (+) Stop conversion of regular group and disable interruptions.
-      (+) Handle ADC interrupt request
-      (+) Start conversion of regular group and enable DMA transfer.
-      (+) Stop conversion of regular group and disable ADC DMA transfer.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group.
-  *         Interruptions enabled in this function: None.
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  tmp_hal_status = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-    
-    /* Enable conversion of regular group.                                    */
-    /* If software start has been selected, conversion starts immediately.    */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected channels in 
-  *         case of auto_injection mode), disable ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential 
-  *         conversion on injected group. If injected group is under use, it
-  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Wait for regular group conversion to be completed.
-  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
-  *         conversion) are cleared by this function, with an exception:
-  *         if low power feature "LowPowerAutoWait" is enabled, flags are 
-  *         not cleared to not interfere with this feature until data register
-  *         is read using function HAL_ADC_GetValue().
-  * @note   This function cannot be used in a particular setup: ADC configured 
-  *         in DMA mode and polling for end of each conversion (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
-  *         In this case, DMA resets the flag EOC and polling cannot be
-  *         performed on each conversion. Nevertheless, polling can still 
-  *         be performed on the complete sequence (ADC init
-  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
-  * @param  hadc ADC handle
-  * @param  Timeout Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Verification that ADC configuration is compliant with polling for      */
-  /* each conversion:                                                       */
-  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
-  /* several ranks and polling for end of each conversion.                  */
-  /* For code simplicity sake, this particular case is generalized to       */
-  /* ADC configured in DMA mode and and polling for end of each conversion. */
-  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
-      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hadc);
-    
-    return HAL_ERROR;
-  }
-
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  /* Wait until End of Conversion flag is raised */
-  while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
-        {
-          /* Update ADC state machine to timeout */
-          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  
-  /* Clear end of conversion flag of regular group if low power feature     */
-  /* "Auto Wait" is disabled, to not interfere with this feature until data */
-  /* register is read using function HAL_ADC_GetValue().                    */
-  if (hadc->Init.LowPowerAutoWait == DISABLE)
-  {
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-  }
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-  
-  /* Determine whether any further conversion upcoming on group regular       */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32L1, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-     (hadc->Init.ContinuousConvMode == DISABLE)            &&
-     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-    
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    { 
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for conversion event.
-  * @param  hadc ADC handle
-  * @param  EventType the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
-  *            @arg ADC_OVR_EVENT: ADC Overrun event.
-  * @param  Timeout Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-  
-  /* Get tick count */
-  tickstart = HAL_GetTick();
-  
-  /* Check selected event flag */
-  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-        {
-          /* Update ADC state machine to timeout */
-          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  
-  switch(EventType)
-  {
-  /* Analog watchdog (level out of window) event */
-  case ADC_AWD_EVENT:
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-      
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    break;
-  
-  /* Overrun event */
-  default: /* Case ADC_OVR_EVENT */
-    /* Note: On STM32L1, ADC overrun can be set through other parameters      */
-    /*       refer to description of parameter "EOCSelection" for more        */
-    /*       details.                                                         */
-
-    /* Set ADC state */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
-    /* Set ADC error code to overrun */
-    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-    
-    /* Clear ADC overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    break;
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group with interruption.
-  *         Interruptions enabled in this function:
-  *          - EOC (end of conversion of regular group)
-  *          - overrun
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  tmp_hal_status = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-    
-    /* Enable end of conversion interrupt for regular group */
-    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-    
-    /* Enable conversion of regular group.                                    */
-    /* If software start has been selected, conversion starts immediately.    */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable interrution of 
-  *         end-of-conversion, disable ADC peripheral.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Disable ADC end of conversion interrupt for regular group */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-    
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group and transfers result
-  *         through DMA.
-  *         Interruptions enabled in this function:
-  *          - DMA transfer complete
-  *          - DMA half transfer
-  *          - overrun
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc ADC handle
-  * @param  pData The destination Buffer address.
-  * @param  Length The length of data to be transferred from ADC peripheral to memory.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Enable the ADC peripheral */
-  tmp_hal_status = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to regular group conversion results     */
-    /* - Set state bitfield related to regular group operation                */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
-                      HAL_ADC_STATE_REG_BUSY);
-    
-    /* If conversions on group regular are also triggering group injected,    */
-    /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
-    {
-      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
-    }
-    
-    /* State machine update: Check if an injected conversion is ongoing */
-    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-    {
-      /* Reset ADC error code fields related to conversions on group regular */
-      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
-    }
-    else
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-    
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-    
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* Enable ADC DMA mode */
-    hadc->Instance->CR2 |= ADC_CR2_DMA;
-    
-    /* Start the DMA channel */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-    
-    /* Enable conversion of regular group.                                    */
-    /* If software start has been selected, conversion starts immediately.    */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* Note: Alternate trigger for single conversion could be to force an     */
-    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
-    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable ADC DMA transfer, disable 
-  *         ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential 
-  *         conversion on injected group. If injected group is under use, it
-  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-     
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Disable ADC DMA mode */
-    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
-    {
-      HAL_DMA_Abort(hadc->DMA_Handle);
-      
-      /* Check if DMA channel effectively disabled */
-      if (tmp_hal_status != HAL_OK)
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-      }
-    }
-    
-    /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
-    
-    /* Disable ADC overrun interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Get ADC regular group conversion result.
-  * @note   Reading register DR automatically clears ADC flag EOC
-  *         (ADC group regular end of unitary conversion).
-  * @note   This function does not clear ADC flag EOS 
-  *         (ADC group regular end of sequence conversion).
-  *         Occurrence of flag EOS rising:
-  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
-  *            to flag EOC.
-  *          - If sequencer is composed of several ranks, during the scan
-  *            sequence flag EOC only is raised, at the end of the scan sequence
-  *            both flags EOC and EOS are raised.
-  *         To clear this flag, either use function: 
-  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
-  *         model polling: @ref HAL_ADC_PollForConversion() 
-  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
-  * @param  hadc ADC handle
-  * @retval ADC group regular conversion data
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Note: EOC flag is not cleared here by software because automatically     */
-  /*       cleared by hardware when reading register DR.                      */
-  
-  /* Return ADC converted value */ 
-  return hadc->Instance->DR;
-}
-
-/**
-  * @brief  Handles ADC interrupt request  
-  * @param  hadc ADC handle
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-
-  
-  /* ========== Check End of Conversion flag for regular group ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
-    {
-      /* Update state machine on conversion status if not in error state */
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-      {
-        /* Set ADC state */
-        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
-      }
-
-      /* Determine whether any further conversion upcoming on group regular   */
-      /* by external trigger, continuous mode or scan sequence on going.      */
-      /* Note: On STM32L1, there is no independent flag of end of sequence.   */
-      /*       The test of scan sequence on going is done either with scan    */
-      /*       sequence disabled or with end of conversion flag set to        */
-      /*       of end of sequence.                                            */
-      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-         (hadc->Init.ContinuousConvMode == DISABLE)            &&
-         (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
-          HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-      {
-        /* Disable ADC end of single conversion interrupt on group regular */
-        /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-        /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-        /* by overrun IRQ process below.                                      */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-        
-        /* Set ADC state */
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-        
-        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-        {
-          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-        }
-      }
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ConvCpltCallback(hadc);
-#else
-      HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-      
-      /* Clear regular group conversion flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-    }
-  }
-
-  /* ========== Check End of Conversion flag for injected group ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
-    {
-      /* Update state machine on conversion status if not in error state */
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
-      {
-        /* Set ADC state */
-        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-      }
-
-      /* Determine whether any further conversion upcoming on group injected  */
-      /* by external trigger, scan sequence on going or by automatic injected */
-      /* conversion from group regular (same conditions as group regular      */
-      /* interruption disabling above).                                       */
-      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-         (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
-          HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
-         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-          (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
-          (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
-      {
-        /* Disable ADC end of single conversion interrupt on group injected */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-        
-        /* Set ADC state */
-        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
-
-        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-        { 
-          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-        }
-      }
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->InjectedConvCpltCallback(hadc);
-#else
-      HAL_ADCEx_InjectedConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-      
-      /* Clear injected group conversion flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
-    }
-  }
-   
-  /* ========== Check Analog watchdog flags ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
-    {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-      
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->LevelOutOfWindowCallback(hadc);
-#else
-      HAL_ADC_LevelOutOfWindowCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-      
-      /* Clear the ADC analog watchdog flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    }
-  }
-  
-  /* ========== Check Overrun flag ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR))
-    {
-      /* Note: On STM32L1, ADC overrun can be set through other parameters    */
-      /*       refer to description of parameter "EOCSelection" for more      */
-      /*       details.                                                       */
-      
-      /* Set ADC error code to overrun */
-      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
-      
-      /* Clear ADC overrun flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-      
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ErrorCallback(hadc);
-#else
-      HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-      
-      /* Clear the Overrun flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    }
-  }
-  
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode 
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Conversion DMA half-transfer callback in non blocking mode 
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog callback in non blocking mode. 
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  ADC error callback in non blocking mode
-  *         (ADC conversion with interruption or transfer by DMA)
-  * @note   In case of error due to overrun when using ADC with DMA transfer 
-  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
-  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
-  *         - If needed, restart a new ADC conversion using function
-  *           "HAL_ADC_Start_DMA()"
-  *           (this function is also clearing overrun flag)
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ErrorCallback must be implemented in the user file.
-  */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on regular group
-      (+) Configure the analog watchdog
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the the selected channel to be linked to the regular
-  *         group.
-  * @note   In case of usage of internal measurement channels:
-  *         Vbat/VrefInt/TempSensor.
-  *         These internal paths can be be disabled using function 
-  *         HAL_ADC_DeInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes channel into regular group, following  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting 
-  *         the ADC.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_ChannelConfTypeDef".
-  * @param  hadc ADC handle
-  * @param  sConfig Structure of ADC channel for regular group.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-   
-  /* Regular sequence configuration */
-  /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7)
-  {
-    MODIFY_REG(hadc->Instance->SQR5,
-               ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
-               ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13)
-  {
-    MODIFY_REG(hadc->Instance->SQR4,
-               ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
-               ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 13 to 18 */
-  else if (sConfig->Rank < 19)
-  {
-    MODIFY_REG(hadc->Instance->SQR3,
-               ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
-               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 19 to 24 */
-  else if (sConfig->Rank < 25)
-  {
-    MODIFY_REG(hadc->Instance->SQR2,
-               ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank),
-               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 25 to 28 */
-  else
-  {
-    MODIFY_REG(hadc->Instance->SQR1,
-               ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank),
-               ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  
-  
-  /* Channel sampling time configuration */
-  /* For channels 0 to 9 */
-  if (sConfig->Channel < ADC_CHANNEL_10)
-  {
-    MODIFY_REG(hadc->Instance->SMPR3,
-               ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
-               ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 10 to 19 */
-  else if (sConfig->Channel < ADC_CHANNEL_20)
-  {
-    MODIFY_REG(hadc->Instance->SMPR2,
-               ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
-               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
-  /* For channels 20 to 29 for devices Cat4, Cat.5 */
-  else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
-  {
-    MODIFY_REG(hadc->Instance->SMPR1,
-               ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel),
-               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 30 to 31 for devices Cat4, Cat.5 */
-  else
-  {
-    ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
-  }
-
-  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
-  /* and VREFINT measurement path.                                            */
-  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
-      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
-  {
-      if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
-      {
-        SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
-        
-        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
-        {
-          /* Delay for temperature sensor stabilization time */
-          /* Compute number of CPU cycles to wait for */
-          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-          while(wait_loop_index != 0)
-          {
-            wait_loop_index--;
-          }
-        }
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Configures the analog watchdog.
-  * @note   Analog watchdog thresholds can be modified while ADC conversion
-  *         is on going.
-  *         In this case, some constraints must be taken into account:
-  *         the programmed threshold values are effective from the next
-  *         ADC EOC (end of unitary conversion).
-  *         Considering that registers write delay may happen due to
-  *         bus activity, this might cause an uncertainty on the
-  *         effective timing of the new programmed threshold values.
-  * @param  hadc ADC handle
-  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-  assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
-  
-  if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
-  {
-    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Analog watchdog configuration */
-
-  /* Configure ADC Analog watchdog interrupt */
-  if(AnalogWDGConfig->ITMode == ENABLE)
-  {
-    /* Enable the ADC Analog watchdog interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
-  }
-  else
-  {
-    /* Disable the ADC Analog watchdog interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
-  }
-  
-  /* Configuration of analog watchdog:                                        */
-  /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
-  /*    one or all channels.                                                  */
-  /*  - Set the Analog watchdog channel (is not used if watchdog              */
-  /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                             */
-  hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL |
-                            ADC_CR1_JAWDEN |
-                            ADC_CR1_AWDEN  |
-                            ADC_CR1_AWDCH   );
-  
-  hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode |
-                           AnalogWDGConfig->Channel       );
-      
-  /* Set the high threshold */
-  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
-  
-  /* Set the low threshold */
-  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief    Peripheral State functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions to get in run-time the status of the  
-    peripheral.
-      (+) Check the ADC state
-      (+) Check the ADC error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the ADC state
-  * @param  hadc ADC handle
-  * @retval HAL state
-  */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Return ADC state */
-  return hadc->State;
-}
-
-/**
-  * @brief  Return the ADC error code
-  * @param  hadc ADC handle
-  * @retval ADC Error Code
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Enable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC must be disabled
-  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @note   If low power mode AutoPowerOff is enabled, power-on/off phases are
-  *         performed automatically by hardware.
-  *         In this mode, this function is useless and must not be called because 
-  *         flag ADC_FLAG_RDY is not usable.
-  *         Therefore, this function must be called under condition of
-  *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
-  /* enabling phase not yet completed: flag ADC ready not yet set).           */
-  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
-  /* causes: ADC clock not running, ...).                                     */
-  if (ADC_IS_ENABLE(hadc) == RESET)
-  {
-    /* Enable the Peripheral */
-    __HAL_ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time */
-    /* Compute number of CPU cycles to wait for */
-    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(wait_loop_index != 0)
-    {
-      wait_loop_index--;
-    }
-    
-    /* Get tick count */
-    tickstart = HAL_GetTick();    
-
-    /* Wait for ADC effectively enabled */
-    while(ADC_IS_ENABLE(hadc) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(ADC_IS_ENABLE(hadc) == RESET)
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop ADC conversion and disable the selected ADC
-  * @note   Prerequisite condition to use this function: ADC conversions must be
-  *         stopped to disable the ADC.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0;
-  
-  /* Verification if ADC is not already disabled */
-  if (ADC_IS_ENABLE(hadc) != RESET)
-  {
-    /* Disable the ADC peripheral */
-    __HAL_ADC_DISABLE(hadc);
-     
-    /* Get tick count */
-    tickstart = HAL_GetTick();
-    
-    /* Wait for ADC effectively disabled */    
-    while(ADC_IS_ENABLE(hadc) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
-      {
-        /* New check to avoid false timeout detection in case of preemption */
-        if(ADC_IS_ENABLE(hadc) != RESET)
-        {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
-          /* Set ADC error code to ADC IP internal error */
-          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Update state machine on conversion status if not in error state */
-  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
-  {
-    /* Update ADC state machine */
-    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-    
-    /* Determine whether any further conversion upcoming on group regular   */
-    /* by external trigger, continuous mode or scan sequence on going.      */
-    /* Note: On STM32L1, there is no independent flag of end of sequence.   */
-    /*       The test of scan sequence on going is done either with scan    */
-    /*       sequence disabled or with end of conversion flag set to        */
-    /*       of end of sequence.                                            */
-    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
-       (hadc->Init.ContinuousConvMode == DISABLE)            &&
-       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
-        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
-    {
-      /* Disable ADC end of single conversion interrupt on group regular */
-      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
-      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
-      /* by overrun IRQ process below.                                      */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-      
-      /* Set ADC state */
-      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
-      
-      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
-      {
-        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-      }
-    }
-    
-    /* Conversion complete callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvCpltCallback(hadc);
-#else
-    HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
-  }
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Half conversion callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvHalfCpltCallback(hadc);
-#else
-  HAL_ADC_ConvHalfCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Set ADC state */
-  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-  
-  /* Set ADC error code to DMA error */
-  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-  
-  /* Error callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  hadc->ErrorCallback(hadc);
-#else
-  HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c
deleted file mode 100644
index 6b5a8fe566c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of injected
-  *                group, using 2 possible modes: polling, interruption.
-  *           + Control functions
-  *             ++ Channels configuration on injected group
-  *          Other functions (generic functions) are available in file 
-  *          "stm32l1xx_hal_adc.c".
-  *
-  @verbatim
-  [..] 
-  (@) Sections "ADC peripheral features" and "How to use this driver" are
-      available in file of generic functions "stm32l1xx_hal_adc.c".
-  [..]
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC Extension HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
-  * @{
-  */
-
-  /* ADC conversion cycles (unit: ADC clock cycles)                           */
-  /* (selected sampling time + conversion time of 12 ADC clock cycles, with   */
-  /* resolution 12 bits)                                                      */
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5   ( 16U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES   ( 21U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES  ( 28U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES  ( 36U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES  ( 60U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES  (108U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES (204U)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES (396U)
-
-  /* Delay for temperature sensor stabilization time.                         */
-  /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
-  /* Unit: us                                                                 */
-  #define ADC_TEMPSENSOR_DELAY_US         (10U)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 ADC Extended IO operation functions
- *  @brief    ADC Extended Input and Output operation functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of injected group.
-      (+) Stop conversion of injected group.
-      (+) Poll for conversion complete on injected group.
-      (+) Get result of injected channel conversion.
-      (+) Start conversion of injected group and enable interruptions.
-      (+) Stop conversion of injected group and disable interruptions.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC, starts conversion of injected group.
-  *         Interruptions enabled in this function: None.
-  * @param  hadc ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmp_hal_status = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-    
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Enable conversion of injected group.                                   */
-    /* If software start has been selected, conversion starts immediately.    */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* If automatic injected conversion is enabled, conversion will start     */
-    /* after next regular group conversion.                                   */
-    if (ADC_IS_SOFTWARE_START_INJECTED(hadc)              && 
-        HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)  )
-    {
-      /* Enable ADC software conversion for injected channels */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
-    }
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
-  *         no regular conversion is on going.
-  * @note   If ADC must be disabled and if conversion is on going on 
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Wait for injected group conversion to be completed.
-  * @param  hadc ADC handle
-  * @param  Timeout Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Variables for polling in case of scan mode enabled and polling for each  */
-  /* conversion.                                                              */
-  /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU      */
-  /* cycles to compensate number of CPU cycles for processing of variable     */
-  /* "conversion_timeout_cpu_cycles_max"                                      */
-  uint32_t conversion_timeout_cpu_cycles = 28;
-  uint32_t conversion_timeout_cpu_cycles_max = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();  
-     
-  /* Polling for end of conversion: differentiation if single/sequence        */
-  /* conversion.                                                              */
-  /* For injected group, flag JEOC is set only at the end of the sequence,    */
-  /* not for each conversion within the sequence.                             */
-  /* If setting "EOCSelection" is set to poll for each single conversion,     */
-  /* management of polling depends on setting of injected group sequencer:    */ 
-  /*  - If single conversion for injected group (scan mode disabled or        */
-  /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
-  /*    conversion completion.                                                */
-  /*  - If sequence conversion for injected group (scan mode enabled and      */
-  /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
-  /*    sequence.                                                             */
-  /*    To poll for each conversion, the maximum conversion time is computed  */
-  /*    from ADC conversion time (selected sampling time + conversion time of */
-  /*    12 ADC clock cycles) and APB2/ADC clock prescalers (depending on      */
-  /*    settings, conversion time range can vary from 8 to several thousands  */
-  /*    of CPU cycles).                                                       */
-
-  /* Note: On STM32L1, setting "EOCSelection" is related to regular group     */
-  /*       only, by hardware. For compatibility with other STM32 devices,     */
-  /*       this setting is related also to injected group by software.        */
-  if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)  ||
-      (hadc->Init.EOCSelection != ADC_EOC_SINGLE_CONV)   )
-  {
-    /* Wait until End of Conversion flag is raised */
-    while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
-    {
-      /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* New check to avoid false timeout detection in case of preemption */
-          if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
-          {
-            /* Update ADC state machine to timeout */
-            SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-            /* Process unlocked */
-            __HAL_UNLOCK(hadc);
-
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Computation of CPU cycles corresponding to ADC conversion cycles.      */
-    /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all  */
-    /* channels.                                                              */
-    conversion_timeout_cpu_cycles_max = ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc);
-    conversion_timeout_cpu_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
-
-    /* Poll with maximum conversion time */
-    while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max)
-    {
-      /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* New check to avoid false timeout detection in case of preemption */
-          if(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max)
-          {
-            /* Update ADC state machine to timeout */
-            SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
-            /* Process unlocked */
-            __HAL_UNLOCK(hadc);
-
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      conversion_timeout_cpu_cycles ++;
-    }
-  }
-  
-  /* Clear end of conversion flag of injected group if low power feature      */
-  /* "Auto Wait" is disabled, to not interfere with this feature until data   */
-  /* register is read using function HAL_ADCEx_InjectedGetValue().            */
-  if (hadc->Init.LowPowerAutoWait == DISABLE)
-  {
-    /* Clear injected group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
-  }
-  
-  /* Update ADC state machine */
-  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-  
-  /* Determine whether any further conversion upcoming on group injected      */
-  /* by external trigger, continuous mode or scan sequence on going.          */
-  /* Note: On STM32L1, there is no independent flag of end of sequence.       */
-  /*       The test of scan sequence on going is done either with scan        */
-  /*       sequence disabled or with end of conversion flag set to            */
-  /*       of end of sequence.                                                */
-  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
-     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
-      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
-     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
-      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
-      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
-  {
-    /* Set ADC state */
-    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-    
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    { 
-      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-    }
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of injected group with interruption.
-  *          - JEOC (end of conversion of injected group)
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmp_hal_status = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
-  {
-    /* Set ADC state                                                          */
-    /* - Clear state bitfield related to injected group conversion results    */
-    /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
-    
-    /* Check if a regular conversion is ongoing */
-    /* Note: On this device, there is no ADC error code fields related to     */
-    /*       conversions on group injected only. In case of conversion on     */
-    /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
-    {
-      /* Reset ADC all error code fields */
-      ADC_CLEAR_ERRORCODE(hadc);
-    }
-    
-    /* Process unlocked */
-    /* Unlock before starting ADC conversions: in case of potential           */
-    /* interruption, to let the process to ADC IRQ Handler.                   */
-    __HAL_UNLOCK(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-    
-    /* Enable conversion of injected group.                                   */
-    /* If software start has been selected, conversion starts immediately.    */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* If automatic injected conversion is enabled, conversion will start     */
-    /* after next regular group conversion.                                   */
-    if (ADC_IS_SOFTWARE_START_INJECTED(hadc)              && 
-        HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)  )
-    {
-      /* Enable ADC software conversion for injected channels */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
-    }
-  }
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Stop conversion of injected channels, disable interruption of 
-  *         end-of-conversion. Disable ADC peripheral if no regular conversion
-  *         is on going.
-  * @note   If ADC must be disabled and if conversion is on going on 
-  *         regular group, function HAL_ADC_Stop must be used to stop both
-  *         injected and regular groups, and disable the ADC.
-  * @note   If injected group mode auto-injection is enabled,
-  *         function HAL_ADC_Stop must be used.
-  * @param  hadc ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
-    {
-      /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-      
-      /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-      
-    tmp_hal_status = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @brief  Get ADC injected group conversion result.
-  * @note   Reading register JDRx automatically clears ADC flag JEOC
-  *         (ADC group injected end of unitary conversion).
-  * @note   This function does not clear ADC flag JEOS 
-  *         (ADC group injected end of sequence conversion)
-  *         Occurrence of flag JEOS rising:
-  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
-  *            to flag JEOC.
-  *          - If sequencer is composed of several ranks, during the scan
-  *            sequence flag JEOC only is raised, at the end of the scan sequence
-  *            both flags JEOC and EOS are raised.
-  *         Flag JEOS must not be cleared by this function because
-  *         it would not be compliant with low power features
-  *         (feature low power auto-wait, not available on all STM32 families).
-  *         To clear this flag, either use function: 
-  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
-  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion() 
-  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
-  * @param  hadc ADC handle
-  * @param  InjectedRank the converted ADC injected rank.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
-  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
-  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
-  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
-  * @retval ADC group injected conversion data
-  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
-  uint32_t tmp_jdr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-  
-  /* Get ADC converted value */
-  switch(InjectedRank)
-  {  
-    case ADC_INJECTED_RANK_4:
-      tmp_jdr = hadc->Instance->JDR4;
-      break;
-    case ADC_INJECTED_RANK_3: 
-      tmp_jdr = hadc->Instance->JDR3;
-      break;
-    case ADC_INJECTED_RANK_2: 
-      tmp_jdr = hadc->Instance->JDR2;
-      break;
-    case ADC_INJECTED_RANK_1:
-    default:
-      tmp_jdr = hadc->Instance->JDR1;
-      break;
-  }
-  
-  /* Return ADC converted value */ 
-  return tmp_jdr;
-}
-
-/**
-  * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
-  * @brief    ADC Extended Peripheral Control functions
-  *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on injected group
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the ADC injected group and the selected channel to be
-  *         linked to the injected group.
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes injected group, following calls to this 
-  *         function can be used to reconfigure some parameters of structure
-  *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
-  *         The setting of these parameters is conditioned to ADC state: 
-  *         this function must be called when ADC is not under conversion.
-  * @param  hadc ADC handle
-  * @param  sConfigInjected Structure of ADC injected group and ADC channel for
-  *         injected group.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{   
-  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
-  assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, sConfigInjected->InjectedOffset));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
-    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
-  }
-  
-  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Configuration of injected group sequencer:                               */
-  /* - if scan mode is disabled, injected channels sequence length is set to  */
-  /*   0x00: 1 channel converted (channel on regular rank 1)                  */
-  /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
-  /*   Note: Scan mode is present by hardware on this device and, if          */
-  /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
-  /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
-  /* - if scan mode is enabled, injected channels sequence length is set to   */
-  /*   parameter ""InjectedNbrOfConversion".                                  */
-  if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
-  {
-    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
-    {
-      /* Clear the old SQx bits for all injected ranks */
-        MODIFY_REG(hadc->Instance->JSQR                              ,
-                   ADC_JSQR_JL   |
-                   ADC_JSQR_JSQ4 |
-                   ADC_JSQR_JSQ3 |
-                   ADC_JSQR_JSQ2 |
-                   ADC_JSQR_JSQ1                                     ,
-                   ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
-                                    ADC_INJECTED_RANK_1,
-                                    0x01)                             );
-    }
-    /* If another injected rank than rank1 was intended to be set, and could  */
-    /* not due to ScanConvMode disabled, error is reported.                   */
-    else
-    {
-      /* Update ADC state machine to error */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-      tmp_hal_status = HAL_ERROR;
-    }
-  }
-  else
-  {   
-    /* Since injected channels rank conv. order depends on total number of   */
-    /* injected conversions, selected rank must be below or equal to total   */
-    /* number of injected conversions to be updated.                         */
-    if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
-    {
-      /* Clear the old SQx bits for the selected rank */
-      /* Set the SQx bits for the selected rank */
-      MODIFY_REG(hadc->Instance->JSQR                                                     ,
-                 
-                 ADC_JSQR_JL                                               |
-                 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                         
-                                  sConfigInjected->InjectedRank,         
-                                  sConfigInjected->InjectedNbrOfConversion)               ,
-                 
-                 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion)             |
-                 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,      
-                                                sConfigInjected->InjectedRank,         
-                                                sConfigInjected->InjectedNbrOfConversion)  );
-    }
-    else
-    {
-      /* Clear the old SQx bits for the selected rank */
-      MODIFY_REG(hadc->Instance->JSQR                                       ,
-                 
-                 ADC_JSQR_JL                                               |
-                 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                         
-                                  sConfigInjected->InjectedRank,         
-                                  sConfigInjected->InjectedNbrOfConversion) ,
-                 
-                 0x00000000                                                  );
-    }
-  } 
-    
-  /* Enable external trigger if trigger selection is different of software    */
-  /* start.                                                                   */
-  /* Note: This configuration keeps the hardware feature of parameter         */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to             */
-  /*       software start.                                                    */
-  
-  if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {    
-    MODIFY_REG(hadc->Instance->CR2                        ,
-               ADC_CR2_JEXTEN  |
-               ADC_CR2_JEXTSEL                            ,
-               sConfigInjected->ExternalTrigInjecConv    |
-               sConfigInjected->ExternalTrigInjecConvEdge  );
-  }
-  else
-  {
-    MODIFY_REG(hadc->Instance->CR2,
-               ADC_CR2_JEXTEN  |
-               ADC_CR2_JEXTSEL    ,
-               0x00000000          );
-  }
-
-  /* Configuration of injected group                                          */
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated only when ADC is disabled:                */
-  /*  - Automatic injected conversion                                         */
-  /*  - Injected discontinuous mode                                           */
-  if ((ADC_IS_ENABLE(hadc) == RESET))
-  {
-    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO   |
-                             ADC_CR1_JDISCEN  );
-    
-    /* Automatic injected conversion can be enabled if injected group         */
-    /* external triggers are disabled.                                        */
-    if (sConfigInjected->AutoInjectedConv == ENABLE)
-    {
-      if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
-      {
-        SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      }
-      else
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-        tmp_hal_status = HAL_ERROR;
-      }
-    }
-    
-    /* Injected discontinuous can be enabled only if auto-injected mode is    */
-    /* disabled.                                                              */  
-    if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
-    {
-      if (sConfigInjected->AutoInjectedConv == DISABLE)
-      {
-        SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
-      } 
-      else
-      {
-        /* Update ADC state machine to error */
-        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-        
-        tmp_hal_status = HAL_ERROR;
-      }
-    }
-  }
-
-  /* Channel sampling time configuration */
-  /* For InjectedChannels 0 to 9 */
-  if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10)
-  {
-    MODIFY_REG(hadc->Instance->SMPR3,
-               ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel),
-               ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 10 to 19 */
-  else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20)
-  {
-    MODIFY_REG(hadc->Instance->SMPR2,
-               ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
-               ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
-  /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */
-  else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX)
-  {   
-    MODIFY_REG(hadc->Instance->SMPR1,
-               ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel),
-               ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */
-  else
-  {
-    ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-  
-  
-  /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
-  switch(sConfigInjected->InjectedRank)
-  {
-    case 1:
-      /* Set injected channel 1 offset */
-      MODIFY_REG(hadc->Instance->JOFR1,
-                 ADC_JOFR1_JOFFSET1,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 2:
-      /* Set injected channel 2 offset */
-      MODIFY_REG(hadc->Instance->JOFR2,
-                 ADC_JOFR2_JOFFSET2,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 3:
-      /* Set injected channel 3 offset */
-      MODIFY_REG(hadc->Instance->JOFR3,
-                 ADC_JOFR3_JOFFSET3,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 4:
-    default:
-      MODIFY_REG(hadc->Instance->JOFR4,
-                 ADC_JOFR4_JOFFSET4,
-                 sConfigInjected->InjectedOffset);
-      break;
-  }
-  
-  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
-  /* and VREFINT measurement path.                                            */
-  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
-      (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
-  {
-    SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
-    
-    if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
-    {
-      /* Delay for temperature sensor stabilization time */
-      /* Compute number of CPU cycles to wait for */
-      wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-      while(wait_loop_index != 0)
-      {
-        wait_loop_index--;
-      }
-    }
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmp_hal_status;
-}
-
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c
deleted file mode 100644
index d85ed54b8f7..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_comp.c
+++ /dev/null
@@ -1,1080 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp.c
-  * @author  MCD Application Team
-  * @brief   COMP HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the COMP peripheral:
-  *           + Initialization and de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-================================================================================
-          ##### COMP Peripheral features #####
-================================================================================
-  [..]       
-      The STM32L1xx device family integrates 2 analog comparators COMP1 and 
-      COMP2:
-      (#) The non inverting input and inverting input can be set to GPIO pins.
-          HAL COMP driver configures the Routing Interface (RI) to connect the
-          selected I/O pins to comparator input.
-          Caution: Comparator COMP1 and ADC cannot be used at the same time as 
-          ADC since they share the ADC switch matrix: COMP1 non-inverting 
-          input is routed through ADC switch matrix. Except if ADC is intended 
-          to measure voltage on COMP1 non-inverting input: it can be performed 
-          on ADC channel VCOMP.
-
-      (#) The COMP output is available using HAL_COMP_GetOutputLevel().
-
-      (#) The COMP output can be redirected to embedded timers (TIM2, TIM3, 
-          TIM4, TIM10).
-          COMP output cannot be redirected to any I/O pin.
-
-      (#) The comparators COMP1 and COMP2 can be combined in window mode. 
-          In this mode, COMP2 non inverting input is used as common 
-          non-inverting input.
-  
-      (#) The 2 comparators have interrupt capability with wake-up
-          from Sleep and Stop modes (through the EXTI controller):
-          (++) COMP1 is internally connected to EXTI Line 21
-          (++) COMP2 is internally connected to EXTI Line 22
-
-          From the corresponding IRQ handler, the right interrupt source can be retrieved with the 
-          macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
-  
-      (#) The comparators also offer the possibility to output the voltage 
-          reference (VrefInt), used on inverting inputs, on I/O pin through 
-          a buffer. To use it, refer to macro "__HAL_SYSCFG_VREFINT_OUT_ENABLE()".
-
-            ##### How to use this driver #####
-================================================================================
-  [..]
-      This driver provides functions to configure and program the Comparators of all STM32L1xx devices.
-
-      To use the comparator, perform the following steps:
-  
-      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit().
-      (++) Configure the comparator input I/O pin using HAL_GPIO_Init():
-           - For all inputs: I/O pin in analog mode (Schmitt trigger disabled)
-           - Possible alternate configuration, for non-inverting inputs of comparator 2: I/O pin in floating mode (Schmitt trigger enabled).
-           It is recommended to use analog configuration to avoid any overconsumption around VDD/2.
-      (++) Enable COMP Peripheral clock using macro __HAL_RCC_COMP_CLK_ENABLE()
-      (++) If required enable the COMP interrupt (EXTI line Interrupt): enable
-           the comparator interrupt vector using HAL_NVIC_EnableIRQ(COMP_IRQn)
-           and HAL_NVIC_SetPriority(COMP_IRQn, xxx, xxx) functions.
-  
-      (#) Configure the comparator using HAL_COMP_Init() function:
-      (++) Select the inverting input (COMP2 only)
-      (++) Select the non-inverting input
-      (++) Select the output redirection to timers (COMP2 only)
-      (++) Select the speed mode (COMP2 only)
-      (++) Select the window mode (related to COMP1 and COMP2, but selected 
-           by COMP2 only)
-      (++) Select the pull-up/down resistors on non-inverting input (COMP1 only)
-
-      (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() 
-          function
-    
-      (#) If needed, use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
-          functions to manage comparator actions (output level or events)
-
-      (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() 
-          function
-
-      (#) De-initialize the comparator using HAL_COMP_DeInit() function
-
-    *** Callback registration ***
-    =============================================
-    [..]
-
-     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_COMP_RegisterCallback()
-     to register an interrupt callback.
-    [..]
-
-     Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
-       (+) TriggerCallback       : callback for COMP trigger.
-       (+) MspInitCallback       : callback for Msp Init.
-       (+) MspDeInitCallback     : callback for Msp DeInit.
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-
-     Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
-     weak function.
-    [..]
-
-     @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) TriggerCallback       : callback for COMP trigger.
-       (+) MspInitCallback       : callback for Msp Init.
-       (+) MspDeInitCallback     : callback for Msp DeInit.
-     [..]
-
-     By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     example @ref HAL_COMP_TriggerCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
-     these callbacks are null (not registered beforehand).
-    [..]
-
-     If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-     [..]
-
-     Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-    [..]
-
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
-     or @ref HAL_COMP_Init() function.
-     [..]
-
-     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/*
-  Additionnal remark: 
-    Table 1. COMP Inputs for the STM32L1xx devices
-    +----------------------------------------------------------------------+
-    |                 |                                |  COMP1  |  COMP2  |
-    |-----------------|--------------------------------|---------|---------|
-    |                 | 1/4 VREFINT                    |   --    |   OK    |
-    |                 | 1/2 VREFINT                    |   --    |   OK    |
-    |                 | 3/4 VREFINT                    |   --    |   OK    |
-    | Inverting       | VREFINT                        |   OK    |   OK    |
-    | input           | DAC Ch1 OUT (PA4)              |   --    |   OK    |
-    |                 | DAC Ch2 OUT (PA5)              |   --    |   OK    |
-    |                 | IO: PB3                        |   --    |   OK    |
-    |-----------------|--------------------------------|---------|---------|
-    |                 | IO:                            |         |         |
-    |                 |   PB4, 5, 6*, 7*               |   ---   |   OK    |
-    | Non-inverting   |   PA0*, 1*, 2*, 3*, 4, 5, 6, 7 |   OK    |   ---   |
-    | input           |   PB0, 1, 12, 13, 14, 15       |   OK    |   ---   |
-    |                 |   PC0, 1, 2, 3, 4, 5           |   OK    |   ---   |
-    |                 |   PE7, 8, 9, 10                |   OK    |   ---   |
-    |                 |   PF6, 7, 8, 9, 10             |   OK    |   ---   |
-    |                 | OPAMP1 output                  |   OK    |   ---   |
-    |                 | OPAMP2 output                  |   OK    |   ---   |
-    |                 | OPAMP3 output**                |   OK    |   ---   |
-    +----------------------------------------------------------------------+
-    *: Available on devices category Cat.3, Cat.4, Cat.5 only. 
-    **: Available on devices category Cat.4 only. 
-    
-    [..] Table 2. COMP Outputs redirection to embedded timers
-    +-----------------------------------+     
-    |      COMP1      |      COMP2      |
-    |-----------------|-----------------|
-    |                 |  TIM2 IC4       |
-    |                 |  TIM2 OCREF CLR |
-    | (no redirection |  TIM3 IC4       |
-    |   to timers)    |  TIM3 OCREF CLR |
-    |                 |  TIM4 IC4       |
-    |                 |  TIM4 OCREF CLR |
-    |                 |  TIM10 IC1      |
-    +-----------------------------------+
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMP COMP
-  * @brief COMP HAL module driver
-  * @{
-  */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Constants COMP Private Constants
-  * @{
-  */
-  /* Delay for COMP start-up time.                                            */
-  /* Maximum delay is 10us for comparator 1 and 25us for comparator 2 in slow */
-  /* mode (refer to device datasheet, parameter tSTART).                      */
-  /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */
-  /* have the minimum number of CPU cycles to fulfill this delay.             */
-  /*  - Comparator 1: delay minimum of 320 CPU cycles. Wait loop takes 3 CPU  */
-  /*                 cycles per iteration, therefore total wait iterations    */
-  /*                 number must be initialized at 106 iterations.            */
-  /*  - Comparator 2: delay minimum of 800 CPU cycles. Wait loop takes 3 CPU  */
-  /*                 cycles per iteration, therefore total wait iterations    */
-  /*                 number must be initialized at 266 iterations.            */
-#define COMP1_START_DELAY_CPU_CYCLES       (106U)
-#define COMP2_START_DELAY_CPU_CYCLES       (266U)
-
-  /* Comparator status "locked": to update COMP handle state (software lock   */
-  /* only on COMP of STM32L1xx devices) by bitfield:                          */
-  /* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED.          */
-#define COMP_STATE_BIT_LOCK     (0x00000010U)  
-
-/**
-  * @}
-  */
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Functions COMP Exported Functions
-  * @{
-  */
-
-/** @defgroup COMP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions to initialize and de-initialize comparators 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the COMP according to the specified
-  *         parameters in the COMP_InitTypeDef and create the associated handle.
-  * @note   If the selected comparator is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if (hcomp->Instance == COMP1)
-    {
-      assert_param(IS_COMP_NONINVERTINGINPUTPULL(hcomp->Init.NonInvertingInputPull));
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
-      assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
-      assert_param(IS_COMP_MODE(hcomp->Init.Mode));
-      assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
-    }
-  
-    /* In window mode, non-inverting inputs of the 2 comparators are          */
-    /* connected together and are using inputs of COMP2 only. If COMP1 is     */
-    /* selected, this parameter is discarded.                                 */
-    if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLE) ||
-        (hcomp->Instance == COMP2)                            )
-    {
-      assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
-    }
-    
-      
-    /* Enable SYSCFG clock and the low level hardware to access comparators */
-    if(hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      /* Allocate lock resource and initialize it */
-      hcomp->Lock = HAL_UNLOCKED;
-
-      /* Enable SYSCFG clock to control the routing Interface (RI) */
-      __HAL_RCC_SYSCFG_CLK_ENABLE();
-      
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-      /* Init the COMP Callback settings */
-      hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
-
-      if (hcomp->MspInitCallback == NULL)
-      {
-        hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
-      }
-      
-      /* Init the low level hardware */
-      hcomp->MspInitCallback(hcomp);
-#else
-      /* Init the low level hardware */
-      HAL_COMP_MspInit(hcomp);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-    }
-  
-    /* Configuration of comparator:                                           */
-    /*  - Output selection                                                    */
-    /*  - Inverting input selection                                           */
-    /*  - Window mode                                                         */
-    /*  - Mode fast/slow speed                                                */
-    /*  - Inverting input pull-up/down resistors                              */
-    
-    /* Configuration depending on comparator instance */
-    if (hcomp->Instance == COMP1)
-    {
-      MODIFY_REG(COMP->CSR, COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU,
-                            hcomp->Init.NonInvertingInputPull                                   );
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      /* Note: If comparator 2 is not enabled, inverting input (parameter     */
-      /*       "hcomp->Init.InvertingInput") is configured into function      */
-      /*       "HAL_COMP_Start()" since inverting  input selection also       */
-      /*       enables the comparator 2.                                      */
-      /*       If comparator 2 is already enabled, inverting input is         */
-      /*       reconfigured on the fly.                                       */
-      if (__COMP_IS_ENABLED(hcomp) == RESET)
-      {
-        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
-                              COMP_CSR_WNDWE   |
-                              COMP_CSR_SPEED          ,
-                              hcomp->Init.Output     |
-                              hcomp->Init.WindowMode |
-                              hcomp->Init.Mode        );
-      }
-      else
-      {
-        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
-                              COMP_CSR_INSEL   |
-                              COMP_CSR_WNDWE   |
-                              COMP_CSR_SPEED              ,
-                              hcomp->Init.Output         |
-                              hcomp->Init.InvertingInput |
-                              hcomp->Init.WindowMode     |
-                              hcomp->Init.Mode            );
-      }
-    }
-    
-    /* Configure Routing Interface (RI) switches for comparator non-inverting */
-    /* input.                                                                 */
-    /* Except in 2 cases:                                                     */
-    /* - if non-inverting input has no selection: it can be the case for      */
-    /*   COMP1 in window mode.                                                */
-    /* - particular case for PC3: if switch COMP1_SW1 is closed               */
-    /*   (by macro "__HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()" or             */
-    /*   "__HAL_RI_SWITCH_COMP1_SW1_CLOSE()"), connection between pin PC3     */
-    /*    (or OPAMP3, if available) and COMP1 is done directly, without going */
-    /*    through ADC switch matrix.                                          */
-#if defined(COMP_CSR_SW1)
-    if(READ_BIT(COMP->CSR, COMP_CSR_SW1) != RESET)
-    {
-      if(hcomp->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_PC3)
-      {
-        /* Case of switch COMP1_SW1 closed and non-inverting input different of PC3:
-           setting of another input is not possible (issue of pin shorted with PC3) */
-        status = HAL_ERROR;
-      }
-    }
-    else
-#endif
-    {
-      if (__COMP_ROUTING_INTERFACE_TOBECONFIGURED(hcomp))
-      {
-        if (hcomp->Instance == COMP1)
-        {
-          /* Enable the switch control mode */
-          __HAL_RI_SWITCHCONTROLMODE_ENABLE();
-
-          /* Close the analog switch of ADC switch matrix to COMP1 (ADC         */
-          /* channel 26: Vcomp)                                                 */
-          __HAL_RI_IOSWITCH_CLOSE(RI_IOSWITCH_VCOMP);
-        }
-
-        /* Close the I/O analog switch corresponding to comparator              */
-        /* non-inverting input selected.                                        */
-        __HAL_RI_IOSWITCH_CLOSE(hcomp->Init.NonInvertingInput);
-      }
-    }
-
-    
-    /* Initialize the COMP state*/
-    if(hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-  }
-  
-  return status;
-}
-
-
-/**
-  * @brief  DeInitializes the COMP peripheral 
-  * @note   Deinitialization can't be performed if the COMP configuration is locked.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    
-    /* Reset configuration depending on comparator instance */
-    if (hcomp->Instance == COMP1)
-    {
-      CLEAR_BIT(COMP->CSR , COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU);
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      CLEAR_BIT(COMP->CSR , COMP_CSR_OUTSEL |
-                            COMP_CSR_WNDWE  |
-                            COMP_CSR_INSEL  |
-                            COMP_CSR_SPEED   );
-    }
-    
-    
-    /* Restore default state of Routing Interface (RI) switches for           */
-    /* comparator non-inverting input.                                        */
-    if (hcomp->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE)
-    {
-      /* Open the I/O analog switch corresponding to comparator               */
-      /* non-inverting input selected.                                        */
-      __HAL_RI_IOSWITCH_OPEN(hcomp->Init.NonInvertingInput);
-    }
-    if (hcomp->Instance == COMP1)
-    {
-      /* Open the analog switch of ADC switch matrix to COMP1 (ADC            */
-      /* channel 26: Vcomp)                                                   */
-      __HAL_RI_IOSWITCH_OPEN(RI_IOSWITCH_VCOMP);
-      
-      /* Disable the switch control mode */
-      __HAL_RI_SWITCHCONTROLMODE_DISABLE();
-    }
-
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-    if (hcomp->MspDeInitCallback == NULL)
-    {
-      hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
-    }
-    
-    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-    hcomp->MspDeInitCallback(hcomp);
-#else
-    /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK, NVIC */
-    HAL_COMP_MspDeInit(hcomp);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-    hcomp->State = HAL_COMP_STATE_RESET;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcomp);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the COMP MSP.
-  * @param  hcomp COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_COMP_MspInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes COMP MSP.
-  * @param  hcomp COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_COMP_MspDeInit could be implenetd in the user file
-   */
-}
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User COMP Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
-  *                the configuration information for the specified COMP.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
-  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  
-  if (HAL_COMP_STATE_READY == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_TRIGGER_CB_ID :
-        hcomp->TriggerCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_COMP_STATE_RESET == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = pCallback;
-        break;
-      
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = pCallback;
-        break;
-      
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-    
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Unregister a COMP Callback
-  *         COMP callback is redirected to the weak predefined callback
-  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
-  *                the configuration information for the specified COMP.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
-  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (HAL_COMP_STATE_READY == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_TRIGGER_CB_ID :
-        hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
-        break;
-      
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
-        break;
-
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
-        break;
-
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_COMP_STATE_RESET == hcomp->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_COMP_MSPINIT_CB_ID :
-        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
-        break;
-
-      case HAL_COMP_MSPDEINIT_CB_ID :
-        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
-        break;
-
-      default :
-        /* Update the error code */
-        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions 
- *  @brief   I/O operation functions
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the COMP 
-    start and stop actions with or without interruption on ExtI line.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the comparator 
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t wait_loop_cycles = 0;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if(hcomp->State == HAL_COMP_STATE_READY)
-    {
-      
-      /* Note: For comparator 2, inverting input (parameter                   */
-      /*       "hcomp->Init.InvertingInput") is configured into this          */
-      /*       function instead of function "HAL_COMP_Init()" since           */
-      /*       inverting input selection also enables the comparator 2.       */
-      __HAL_COMP_ENABLE(hcomp);
-
-      /* Set delay for COMP start-up time */
-      if (hcomp->Instance == COMP1)
-      {
-        wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES;
-      }
-      else /* if (hcomp->Instance == COMP2) */
-      {
-        wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES;
-      }
-
-      /* Delay for COMP start-up time.                                         */
-      /* Delay fixed to worst case: maximum CPU frequency                     */
-      while(wait_loop_index < wait_loop_cycles)
-      {
-        wait_loop_index++;
-      }
-
-      /* Update COMP state */
-      hcomp->State = HAL_COMP_STATE_BUSY;
-      
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Stop the comparator 
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if(hcomp->State == HAL_COMP_STATE_BUSY)
-    {
-      /* Disable the selected comparator */
-      __HAL_COMP_DISABLE(hcomp);
-      
-      /* Update COMP state */
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Enables the interrupt and starts the comparator
-  * @param  hcomp COMP handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t extiline = 0;
-  
-  status = HAL_COMP_Start(hcomp);
-  if(status == HAL_OK)
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
-    
-    /* Get the Exti Line output configuration */
-    extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-    
-    /* Configure the trigger rising edge */
-    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
-    {
-      SET_BIT(EXTI->RTSR, extiline);
-    }
-    else
-    {
-      CLEAR_BIT(EXTI->RTSR, extiline);
-    }
-  
-    /* Configure the trigger falling edge */
-    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
-    {
-      SET_BIT(EXTI->FTSR, extiline);
-    }
-    else
-    {
-      CLEAR_BIT(EXTI->FTSR, extiline);
-    }
-    
-    /* Clear COMP EXTI pending bit */
-    WRITE_REG(EXTI->PR, extiline);
-    
-    /* Enable EXTI interrupt mode */
-    SET_BIT(EXTI->IMR, extiline);
-    
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Disable the interrupt and Stop the comparator 
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Disable the EXTI Line interrupt mode */
-  CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance));
-  
-  status = HAL_COMP_Stop(hcomp);
-  
-  return status;
-}
-
-/**
-  * @brief  Comparator IRQ Handler 
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
-{
-  uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-  
-  /* Check COMP Exti flag */
-  if(READ_BIT(EXTI->PR, extiline) != RESET)
-  {
-    /* Clear COMP EXTI pending bit */
-    WRITE_REG(EXTI->PR, extiline);
-
-    /* COMP trigger callback */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-    hcomp->TriggerCallback(hcomp);
-#else
-    HAL_COMP_TriggerCallback(hcomp);    
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   Peripheral Control functions
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the COMP 
-    management functions: Lock status, comparator output level check, IRQ
-    callback (in case of usage of comparator with interruption on ExtI line).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected comparator configuration.
-  *         Caution: On STM32L1, HAL COMP lock is software lock only (not  
-  *         hardware lock as on some other STM32 devices)
-  * @param  hcomp COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    /* Set lock flag on state */
-    switch(hcomp->State)
-    {
-    case HAL_COMP_STATE_BUSY:
-      hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
-      break;
-    case HAL_COMP_STATE_READY:
-      hcomp->State = HAL_COMP_STATE_READY_LOCKED;
-      break;
-    default:
-      /* unexpected state */
-      status = HAL_ERROR;
-      break;
-    }
-  }
-  
-  return status; 
-}
-
-/**
-  * @brief  Return the output level (high or low) of the selected comparator. 
-  *         The output level depends on the selected polarity.
-  *           - Comparator output is low when the non-inverting input is at a lower
-  *             voltage than the inverting input
-  *           - Comparator output is high when the non-inverting input is at a higher
-  *             voltage than the inverting input
-  * @param  hcomp COMP handle
-  * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
-  *       
-  */
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
-{
-  uint32_t level = 0;
-  
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-  /* Read output level of the selected comparator */
-  if(READ_BIT(COMP->CSR, __COMP_CSR_CMPXOUT(hcomp)) == RESET)
-  {
-    level = COMP_OUTPUTLEVEL_LOW;
-  }
-  else
-  {
-    level = COMP_OUTPUTLEVEL_HIGH;
-  }
-  
-  return(level);
-}
-
-/**
-  * @brief  Comparator trigger callback.
-  * @param  hcomp COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcomp);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_COMP_TriggerCallback should be implemented in the user file
-   */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the COMP state
-  * @param  hcomp  COMP handle
-  * @retval HAL state
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the COMP handle allocation */
-  if(hcomp == NULL)
-  {
-    return HAL_COMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-  return hcomp->State;
-}
-
-/**
-  * @brief  Return the COMP error code.
-  * @param hcomp COMP handle
-  * @retval COMP error code
-  */
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-  
-  return hcomp->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c
deleted file mode 100644
index d88dcf4b0f5..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @brief   CORTEX HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the CORTEX:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *          
-  *  @verbatim    
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]  
-    *** How to configure Interrupts using Cortex HAL driver ***
-    ===========================================================
-    [..]     
-    This section provide functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M3 exceptions are managed by CMSIS functions.
-   
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
-
-     (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 
-
-     (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 
-      
-
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. 
-         The pending IRQ priority will be managed only by the sub priority.
-   
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest pre-emption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
- 
-    [..]  
-    *** How to configure Systick using Cortex HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for 1 msec interrupts.
-           
-   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-    
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32l1xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-                            
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-   
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/*
-  Additional Tables: CORTEX_NVIC_Priority_Table
-     The table below gives the allowed values of the pre-emption priority and subpriority according
-     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-       ==========================================================================================================================
-         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-       ==========================================================================================================================
-        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
-                              |                                   |                             | 4 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------
-        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
-                              |                                   |                             | 3 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-                              |                                   |                             | 2 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-                              |                                   |                             | 1 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
-                              |                                   |                             | 0 bits for subpriority                       
-       ==========================================================================================================================
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]
-      This section provide the Cortex HAL driver functions allowing to configure Interrupts
-      Systick functionalities 
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup The priority grouping bits length. 
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *                                    1 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *                                    0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority 
-  * @param  SubPriority the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t prioritygroup = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiates a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief    Cortex control functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK, MPU) functionalities. 
- 
-      
-@endverbatim
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Enable the MPU.
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged accessto the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
-
-  /* Ensure MPU setting take effects */
-  __DSB();
-  __ISB();
-}
-
-/**
-  * @brief  Disable the MPU.
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-
-  /* Disable the MPU and clear the control register*/
-  MPU->CTRL  = 0;
-}
-
-/**
-  * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) != RESET)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-    
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  * @param  PriorityGroup the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *                                      1 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *                                      0 bits for subpriority
-  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets Pending Interrupt (reads the pending register in the NVIC 
-  *         and returns the pending bit for the specified interrupt).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Clears the pending bit of an external interrupt.
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{ 
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  CLKSource specifies the SysTick clock source.
-  *         This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  This function handles SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c
deleted file mode 100644
index 0773fadc915..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_crc.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_crc.c
-  * @author  MCD Application Team
-  * @brief   CRC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]
-         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-         (+) Initialize CRC calculator
-             (++) specify generating polynomial (peripheral default or non-default one)
-             (++) specify initialization value (peripheral default or non-default one)
-             (++) specify input data format
-             (++) specify input or output data inversion mode if any
-         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
-             input data buffer starting with the previously computed CRC as
-             initialization value
-         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
-             input data buffer starting with the defined initialization value
-             (default or non-default) to initiate CRC calculation
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRC CRC
-  * @brief CRC HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions.
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRC according to the specified parameters
-          in the CRC_InitTypeDef and create the associated handle
-      (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP (MCU Specific Package)
-      (+) DeInitialize the CRC MSP
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and create the associated handle.
-  * @param  hcrc CRC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if (hcrc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  if (hcrc->State == HAL_CRC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcrc->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CRC_MspInit(hcrc);
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the CRC peripheral.
-  * @param  hcrc CRC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if (hcrc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  /* Check the CRC peripheral state */
-  if (hcrc->State == HAL_CRC_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Reset CRC calculation unit */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  /* Reset IDR register content */
-  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
-
-  /* DeInit the low level hardware */
-  HAL_CRC_MspDeInit(hcrc);
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_RESET;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hcrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRC MSP.
-  * @param  hcrc CRC handle
-  * @retval None
-  */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the CRC MSP.
-  * @param  hcrc CRC handle
-  * @retval None
-  */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspDeInit can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief    management functions.
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) compute the 32-bit CRC value of a 32-bit data buffer
-          using combination of the previous CRC value and the new one.
-
-       [..]  or
-
-      (+) compute the 32-bit CRC value of a 32-bit data buffer
-          independently of the previous CRC value.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
-  *         starting with the previously computed CRC as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer.
-  * @param  BufferLength input data buffer length (number of uint32_t words).
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Enter Data to the CRC calculator */
-  for (index = 0U; index < BufferLength; index++)
-  {
-    hcrc->Instance->DR = pBuffer[index];
-  }
-  temp = hcrc->Instance->DR;
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return the CRC computed value */
-  return temp;
-}
-
-/**
-  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
-  *         starting with hcrc->Instance->INIT as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer.
-  * @param  BufferLength input data buffer length (number of uint32_t words).
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
-  */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
-  *  written in hcrc->Instance->DR) */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  /* Enter 32-bit input data to the CRC calculator */
-  for (index = 0U; index < BufferLength; index++)
-  {
-    hcrc->Instance->DR = pBuffer[index];
-  }
-  temp = hcrc->Instance->DR;
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Return the CRC computed value */
-  return temp;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
-  *  @brief    Peripheral State functions.
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the CRC handle state.
-  * @param  hcrc CRC handle
-  * @retval HAL state
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
-  /* Return CRC handle state */
-  return hcrc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c
deleted file mode 100644
index 04f13d0f4e3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp.c
+++ /dev/null
@@ -1,2163 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp.c
-  * @author  MCD Application Team
-  * @brief   CRYP HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Processing functions by algorithm using polling mode
-  *           + Processing functions by algorithm using interrupt mode
-  *           + Processing functions by algorithm using DMA mode
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The CRYP HAL driver can be used as follows:
-
-      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
-         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
-         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
-             (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
-             (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
-             (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
-         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
-             (+) Enable the DMA2 interface clock using 
-                 (++) __HAL_RCC_DMA2_CLK_ENABLE()
-             (+) Configure and enable two DMA Channels one for managing data transfer from
-                 memory to peripheral (input channel) and another channel for managing data
-                 transfer from peripheral to memory (output channel)
-             (+) Associate the initialized DMA handle to the CRYP DMA handle
-                 using  __HAL_LINKDMA()
-             (+) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-                 (++) HAL_NVIC_SetPriority()
-                 (++) HAL_NVIC_EnableIRQ()
-    
-      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
-         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
-         (##) The encryption/decryption key.
-         (##) The initialization vector (counter). It is not used ECB mode.
-    
-      (#)Three processing (encryption/decryption) functions are available:
-         (##) Polling mode: encryption and decryption APIs are blocking functions
-              i.e. they process the data and wait till the processing is finished
-              e.g. HAL_CRYP_AESCBC_Encrypt()
-         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
-              i.e. they process the data under interrupt
-              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
-         (##) DMA mode: encryption and decryption APIs are not blocking functions
-              i.e. the data transfer is ensured by DMA
-              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
-    
-      (#)When the processing function is called for the first time after HAL_CRYP_Init()
-         the CRYP peripheral is initialized and processes the buffer in input.
-         At second call, the processing function performs an append of the already
-         processed buffer.
-         When a new data block is to be processed, call HAL_CRYP_Init() then the
-         processing function.
-         
-      (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYP CRYP
-  * @brief CRYP HAL module driver.
-  * @{
-  */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
-  * @{
-  */
-
-#define  CRYP_ALGO_CHAIN_MASK         (AES_CR_MODE | AES_CR_CHMOD)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
-  * @{
-  */
-
-static HAL_StatusTypeDef  CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
-static void               CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
-static void               CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
-static HAL_StatusTypeDef  CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static void               CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void               CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
-  * @{
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRYP according to the specified parameters 
-          in the CRYP_InitTypeDef and creates the associated handle
-      (+) DeInitialize the CRYP peripheral
-      (+) Initialize the CRYP MSP
-      (+) DeInitialize CRYP MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP according to the specified
-  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{ 
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
-  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-  
-  if(hcryp->State == HAL_CRYP_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcryp->Lock = HAL_UNLOCKED;
-
-    /* Init the low level hardware */
-    HAL_CRYP_MspInit(hcryp);
-  }
-  
-  /* Check if AES already enabled */
-  if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;  
-
-    /* Set the data type*/
-    MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-    
-    /* Reset CrypInCount and CrypOutCount */
-    hcryp->CrypInCount = 0;
-    hcryp->CrypOutCount = 0;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Set the default CRYP phase */
-    hcryp->Phase = HAL_CRYP_PHASE_READY;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
-    /* enabled is forbidden to avoid unpredictable AES behavior.*/
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-}
-
-/**
-  * @brief  DeInitializes the CRYP peripheral. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set the default CRYP phase */
-  hcryp->Phase = HAL_CRYP_PHASE_READY;
-  
-  /* Reset CrypInCount and CrypOutCount */
-  hcryp->CrypInCount = 0;
-  hcryp->CrypOutCount = 0;
-  
-  /* Disable the CRYP Peripheral Clock */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_CRYP_MspDeInit(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP MSP.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspInit can be implemented in the user file */
-}
-
-/**
-  * @brief  DeInitializes CRYP MSP.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspDeInit can be implemented in the user file */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions 
- *  @brief   processing functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### AES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using AES algorithm in different chaining modes
-      (+) Decrypt cyphertext using AES algorithm in different chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-
-  /* Check that data aligned on u32 and Size multiple of 16*/
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-	
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout Specify Timeout value   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if initialization phase has already been performed */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey);
-    
-    /* Reset the CHMOD & MODE bits */
-    CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-    
-    /* Set the CRYP peripheral in AES CTR decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-  /* Write Cypher Data and Get Plain Data */
-  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-   
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR decryption mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {  
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Release Lock */
-    __HAL_UNLOCK(hcryp);
-  
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions 
- *  @brief   DMA callback functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### DMA callback functions  #####
-  ==============================================================================  
-    [..]  This section provides DMA callback functions:
-      (+) DMA Input data transfer complete
-      (+) DMA Output data transfer complete
-      (+) DMA error
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  CRYP error callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_ErrorCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Input transfer completed callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_InCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Output transfer completed callback.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_OutCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler 
- *  @brief   CRYP IRQ handler.
- *
-@verbatim   
-  ==============================================================================
-                ##### CRYP IRQ handler management #####
-  ==============================================================================  
-[..]  This section provides CRYP IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function handles CRYP interrupt request.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check if error occurred*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
-  {
-    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-    }
-    
-    hcryp->State= HAL_CRYP_STATE_ERROR;
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
-    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
-    
-    HAL_CRYP_ErrorCallback(hcryp);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    return;
-  }
-  
-  /* Check if computation complete interrupt was enabled*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
-  {
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-  
-    CRYP_EncryptDecrypt_IT(hcryp);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRYP state.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL state
-  */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
-  return hcryp->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  IT function called under interruption context to continue encryption or decryption
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-
-  /* Get the last Output data adress */
-  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-  
-  /* Read the Output block from the Output Register */
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-  
-  hcryp->pCrypOutBuffPtr += 16;
-  hcryp->CrypOutCount -= 16;
-  
-  /* Check if all input text is encrypted or decrypted */
-  if(hcryp->CrypOutCount == 0)
-  {
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CC);
-    __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Call computation complete callback */
-    HAL_CRYPEx_ComputationCpltCallback(hcryp);
-  }
-  else /* Process the rest of input text */
-  {
-    /* Get the last Intput data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;      
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  DMA CRYP Input Data process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for input request  */
-  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-  
-  /* Call input data transfer complete callback */
-  HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP Output Data process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
-     in the DMACR register */
-  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
-  /* Clear CCF Flag */
-  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-
-  /* Disable CRYP */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* Change the CRYP state to ready */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Call output data transfer complete callback */
-  HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP communication error callback. 
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  hcryp->State= HAL_CRYP_STATE_ERROR;
-  HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
-  * @brief  Writes the Key in Key registers. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Key Pointer to Key buffer
-  * @note Key must be written as little endian.
-  *         If Key pointer points at address n, 
-  *         n[15:0] contains key[96:127], 
-  *         (n+4)[15:0] contains key[64:95], 
-  *         (n+8)[15:0] contains key[32:63] and 
-  *         (n+12)[15:0] contains key[0:31]
-  * @retval None
-  */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
-{  
-  uint32_t keyaddr = (uint32_t)Key;
-  
-  hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
-}
-
-/**
-  * @brief  Writes the InitVector/InitCounter in IV registers. 
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  InitVector Pointer to InitVector/InitCounter buffer
-  * @note Init Vector must be written as little endian.
-  *         If Init Vector pointer points at address n, 
-  *         n[15:0] contains Vector[96:127], 
-  *         (n+4)[15:0] contains Vector[64:95], 
-  *         (n+8)[15:0] contains Vector[32:63] and 
-  *         (n+12)[15:0] contains Vector[0:31]
-  * @retval None
-  */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
-{
-  uint32_t ivaddr = (uint32_t)InitVector;
-  
-  hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
-}
-
-/**
-  * @brief  Process Data: Writes Input data in polling mode and reads the output data
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Input Pointer to the Input buffer
-  * @param  Ilength Length of the Input buffer, must be a multiple of 16.
-  * @param  Output Pointer to the returned buffer
-  * @param  Timeout Specify Timeout value  
-  * @retval None
-  */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  uint32_t index = 0;
-  uint32_t inputaddr  = (uint32_t)Input;
-  uint32_t outputaddr = (uint32_t)Output;
-  
-  for(index=0; (index < Ilength); index += 16)
-  {
-    /* Write the Input block in the Data Input register */
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
-    {    
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */          
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
-    
-    /* Read the Output block from the Data Output Register */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-    outputaddr+=4;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the DMA configuration and start the DMA transfer
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  inputaddr address of the Input buffer
-  * @param  Size Size of the Input buffer, must be a multiple of 16.
-  * @param  outputaddr address of the Output buffer
-  * @retval None
-  */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-  
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
-
-  /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
-
-  /* Enable In and Out DMA requests */
-  SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
-
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-}
-
-/**
-  * @}
-  */
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c
deleted file mode 100644
index 47da4426bb4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cryp_ex.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp_ex.c
-  * @author  MCD Application Team
-  * @brief   CRYPEx HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) extension peripheral:
-  *           + Computation completed callback.
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYPEx CRYPEx
-  * @brief CRYP HAL Extended module driver.
-  * @{
-  */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions 
- *  @brief    Extended features functions. 
- *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- =============================================================================== 
-    [..]  This section provides callback functions:
-      (+) Computation completed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Computation completed callbacks.
-  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcryp);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYPEx_ComputationCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c
deleted file mode 100644
index 103793e6667..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c
+++ /dev/null
@@ -1,1353 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac.c
-  * @author  MCD Application Team
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  *
-  @verbatim
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]
-      *** DAC Channels ***
-      ====================
-    [..]
-    STM32L1 devices integrate two 12-bit Digital Analog Converters
-
-    The 2 converters (i.e. channel1 & channel2)
-    can be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
-          peripherals (ex. timers).
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
-          peripherals (ex. timers).
-
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
-    [..]
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_PIN_9) must be configured in input mode.
-
-      (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7, TIM9
-          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
-      (#) Software using DAC_TRIGGER_SOFTWARE
-
-      *** DAC Buffer mode feature ***
-      ===============================
-      [..]
-      Each DAC channel integrates an output buffer that can be used to
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use
-      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]
-      (@) Refer to the device datasheet for more details about output
-          impedance value with and without output buffer.
-
-      *** GPIO configurations guidelines ***
-      =====================
-      [..]
-      When a DAC channel is used (ex channel1 on PA4) and the other is not
-      (ex channel2 on PA5 is configured in Analog and disabled).
-      Channel1 may disturb channel2 as coupling effect.
-      Note that there is no coupling on channel2 as soon as channel2 is turned on.
-      Coupling on adjacent channel could be avoided as follows:
-      when unused PA5 is configured as INPUT PULL-UP or DOWN.
-      PA5 is configured in ANALOG just before it is turned on.
-
-       *** DAC wave generation feature ***
-       ===================================
-       [..]
-       Both DAC channels can be used to generate
-         (#) Noise wave
-         (#) Triangle wave
-
-       *** DAC data format ***
-       =======================
-       [..]
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
-       *** DAC data value to voltage correspondence ***
-       ================================================
-       [..]
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation:
-       [..]
-       DAC_OUTx = VREF+ * DOR / 4095
-       (+) with  DOR is the Data Output Register
-       [..]
-          VREF+ is the input voltage reference (refer to the device datasheet)
-       [..]
-        e.g. To set DAC_OUT1 to 0.7V, use
-       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
-       *** DMA requests ***
-       =====================
-       [..]
-       A DMA request can be generated when an external trigger (but not a software trigger)
-       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
-       DMA1 requests are mapped as following:
-      (#) DAC channel1 mapped on (no request on STM32L1XX) / DMA1 channel2
-      (#) DAC channel2 mapped on (no request on STM32L1XX) / DMA1 channel3
-
-     [..]
-    (@) For Dual mode and specific signal (Triangle and noise) generation please
-        refer to Extended Features Driver description
-
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
-
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Start the DAC peripheral using HAL_DAC_Start()
-       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
-           of data to be transferred at each end of conversion
-           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
-       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-           function is executed and user can add his own code by customization of function pointer
-           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-           function is executed and user can add his own code by customization of function pointer
-           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
-            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
-           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
-           function is executed and user can add his own code by customization of function pointer
-           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
-    *** Callback registration ***
-    =============================================
-    [..]
-      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-    Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
-      it allows to register following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
-      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
-      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
-      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
-      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.
-      (+) MspDeInitCallback       : DAC MspdeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-    Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
-      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
-      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
-      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
-      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.
-      (+) MspDeInitCallback       : DAC MspdeInit.
-      (+) All Callbacks
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-      By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-      Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
-      and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-      Callbacks can be registered/unregistered in READY state only.
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-      during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
-      or @ref HAL_DAC_Init function.
-
-      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
-
-     *** DAC HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros
-
-@endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(DAC1)
-
-/** @defgroup DAC DAC
-  * @brief DAC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC.
-      (+) De-initialize the DAC.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct and initialize the associated handle.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
-{
-  /* Check DAC handle */
-  if (hdac == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  if (hdac->State == HAL_DAC_STATE_RESET)
-  {
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-    /* Init the DAC Callback settings */
-    hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
-    hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
-    hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
-    hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
-
-    hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
-    hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
-    hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
-    hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
-
-    if (hdac->MspInitCallback == NULL)
-    {
-      hdac->MspInitCallback             = HAL_DAC_MspInit;
-    }
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-    /* Allocate lock resource and initialize it */
-    hdac->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-    /* Init the low level hardware */
-    hdac->MspInitCallback(hdac);
-#else
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-  }
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
-{
-  /* Check DAC handle */
-  if (hdac == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  if (hdac->MspDeInitCallback == NULL)
-  {
-    hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hdac->MspDeInitCallback(hdac);
-#else
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the DAC MSP.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the DAC MSP.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
-  *  @brief    IO operation functions
-  *
-@verbatim
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-
-  if (Channel == DAC_CHANNEL_1)
-  {
-    /* Check if software trigger enabled */
-    if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
-    {
-      /* Enable the selected DAC software conversion */
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
-    }
-  }
-
-  else
-  {
-    /* Check if software trigger enabled */
-    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
-    {
-      /* Enable the selected DAC software conversion*/
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
-    }
-  }
-
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                    uint32_t Alignment)
-{
-  HAL_StatusTypeDef status;
-  uint32_t tmpreg = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  if (Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-    /* Enable the selected DAC channel1 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
-    /* Case of use of channel 1 */
-    switch (Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-  }
-
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
-    /* Enable the selected DAC channel2 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
-    /* Case of use of channel 2 */
-    switch (Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-
-
-  /* Enable the DMA channel */
-  if (Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
-    /* Enable the DMA channel */
-    status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  }
-
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
-    /* Enable the DMA channel */
-    status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-
-  if (status == HAL_OK)
-  {
-    /* Enable the Peripheral */
-    __HAL_DAC_ENABLE(hdac, Channel);
-  }
-  else
-  {
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Disable the selected DAC channel DMA request */
-  hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
-
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-
-  /* Disable the DMA channel */
-
-  /* Channel1 is used */
-  if (Channel == DAC_CHANNEL_1)
-  {
-    /* Disable the DMA channel */
-    (void)HAL_DMA_Abort(hdac->DMA_Handle1);
-
-    /* Disable the DAC DMA underrun interrupt */
-    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
-  }
-
-  else /* Channel2 is used for */
-  {
-    /* Disable the DMA channel */
-    (void)HAL_DMA_Abort(hdac->DMA_Handle2);
-
-    /* Disable the DAC DMA underrun interrupt */
-    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
-  }
-
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles DAC interrupt request
-  *         This function uses the interruption of DMA
-  *         underrun.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
-{
-  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
-  {
-    /* Check underrun flag of DAC channel 1 */
-    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-    {
-      /* Change DAC state to error state */
-      hdac->State = HAL_DAC_STATE_ERROR;
-
-      /* Set DAC error code to channel1 DMA underrun error */
-      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
-      /* Clear the underrun flag */
-      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
-
-      /* Disable the selected DAC channel1 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
-      /* Error callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-      hdac->DMAUnderrunCallbackCh1(hdac);
-#else
-      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-    }
-  }
-
-
-  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
-  {
-    /* Check underrun flag of DAC channel 2 */
-    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-    {
-      /* Change DAC state to error state */
-      hdac->State = HAL_DAC_STATE_ERROR;
-
-      /* Set DAC error code to channel2 DMA underrun error */
-      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-
-      /* Clear the underrun flag */
-      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
-
-      /* Disable the selected DAC channel2 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
-      /* Error callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-      hdac->DMAUnderrunCallbackCh2(hdac);
-#else
-      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-    }
-  }
-
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Alignment Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
-  __IO uint32_t tmp = 0UL;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-
-  tmp = (uint32_t)hdac->Instance;
-  if (Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
-
-
-  /* Set the DAC channel selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode for Channel1
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure channels.
-      (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
-{
-  uint32_t result;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  if (Channel == DAC_CHANNEL_1)
-  {
-    result = hdac->Instance->DOR1;
-  }
-
-  else
-  {
-    result = hdac->Instance->DOR2;
-  }
-
-  /* Returns the DAC channel data output register value */
-  return result;
-}
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig DAC configuration structure.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1;
-  uint32_t tmpreg2;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHANNEL(Channel));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Get the DAC CR value */
-  tmpreg1 = hdac->Instance->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */
-  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
-  /* Write to DAC CR */
-  hdac->Instance->CR = tmpreg1;
-  /* Disable wave generation */
-  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   Peripheral State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC handle state
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
-{
-  /* Return DAC handle state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User DAC Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param  hdac DAC handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
-  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
-  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
-  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
-  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
-  *
-  * @param  pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
-                                           pDAC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  if (hdac->State == HAL_DAC_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_DAC_CH1_COMPLETE_CB_ID :
-        hdac->ConvCpltCallbackCh1 = pCallback;
-        break;
-      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
-        hdac->ConvHalfCpltCallbackCh1 = pCallback;
-        break;
-      case HAL_DAC_CH1_ERROR_ID :
-        hdac->ErrorCallbackCh1 = pCallback;
-        break;
-      case HAL_DAC_CH1_UNDERRUN_CB_ID :
-        hdac->DMAUnderrunCallbackCh1 = pCallback;
-        break;
-
-      case HAL_DAC_CH2_COMPLETE_CB_ID :
-        hdac->ConvCpltCallbackCh2 = pCallback;
-        break;
-      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
-        hdac->ConvHalfCpltCallbackCh2 = pCallback;
-        break;
-      case HAL_DAC_CH2_ERROR_ID :
-        hdac->ErrorCallbackCh2 = pCallback;
-        break;
-      case HAL_DAC_CH2_UNDERRUN_CB_ID :
-        hdac->DMAUnderrunCallbackCh2 = pCallback;
-        break;
-
-      case HAL_DAC_MSPINIT_CB_ID :
-        hdac->MspInitCallback = pCallback;
-        break;
-      case HAL_DAC_MSPDEINIT_CB_ID :
-        hdac->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* Update the error code */
-        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hdac->State == HAL_DAC_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_DAC_MSPINIT_CB_ID :
-        hdac->MspInitCallback = pCallback;
-        break;
-      case HAL_DAC_MSPDEINIT_CB_ID :
-        hdac->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* Update the error code */
-        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User DAC Callback
-  *         DAC Callback is redirected to the weak (surcharged) predefined callback
-  * @param  hdac DAC handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 transfer Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
-  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
-  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
-  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
-  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
-  *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  if (hdac->State == HAL_DAC_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_DAC_CH1_COMPLETE_CB_ID :
-        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
-        break;
-      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
-        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
-        break;
-      case HAL_DAC_CH1_ERROR_ID :
-        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
-        break;
-      case HAL_DAC_CH1_UNDERRUN_CB_ID :
-        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-        break;
-
-      case HAL_DAC_CH2_COMPLETE_CB_ID :
-        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
-        break;
-      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
-        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
-        break;
-      case HAL_DAC_CH2_ERROR_ID :
-        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
-        break;
-      case HAL_DAC_CH2_UNDERRUN_CB_ID :
-        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-        break;
-
-      case HAL_DAC_MSPINIT_CB_ID :
-        hdac->MspInitCallback = HAL_DAC_MspInit;
-        break;
-      case HAL_DAC_MSPDEINIT_CB_ID :
-        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-        break;
-      case HAL_DAC_ALL_CB_ID :
-        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
-        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
-        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
-        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-
-        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
-        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
-        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
-        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-
-        hdac->MspInitCallback = HAL_DAC_MspInit;
-        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-        break;
-      default :
-        /* Update the error code */
-        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hdac->State == HAL_DAC_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_DAC_MSPINIT_CB_ID :
-        hdac->MspInitCallback = HAL_DAC_MspInit;
-        break;
-      case HAL_DAC_MSPDEINIT_CB_ID :
-        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
-        break;
-      default :
-        /* Update the error code */
-        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-  return status;
-}
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  DMA conversion complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvCpltCallbackCh1(hdac);
-#else
-  HAL_DAC_ConvCpltCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvHalfCpltCallbackCh1(hdac);
-#else
-  HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-#endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA error callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ErrorCallbackCh1(hdac);
-#else
-  HAL_DAC_ErrorCallbackCh1(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c
deleted file mode 100644
index 4178cb2b35f..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac_ex.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended DAC HAL module driver.
-  *          This file provides firmware functions to manage the extended
-  *          functionalities of the DAC peripheral.
-  *
-  *
-  @verbatim
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-     *** Dual mode IO operation ***
-     ==============================
-     [..]
-      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
-          Channel 1 and Channel 2.
-
-     *** Signal generation operation ***
-     ===================================
-     [..]
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-#if defined(DAC1)
-
-/** @defgroup DACEx DACEx
-  * @brief DAC Extended HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
-  *  @brief    Extended IO operation functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Extended features functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion.
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Enables DAC and starts conversion of both channels.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
-{
-  uint32_t tmp_swtrig = 0UL;
-
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
-  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
-
-  /* Check if software trigger enabled */
-  if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
-  {
-    tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
-  }
-  if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
-  {
-    tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
-  }
-  /* Enable the selected DAC software conversion*/
-  SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of both channels.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
-{
-
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
-  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude Select max triangle amplitude.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the triangle wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
-             (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the noise wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
-             (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
-  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
-  uint32_t data;
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8U) | Data1;
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16U) | Data1;
-  }
-
-  tmp = (uint32_t)hdac->Instance;
-  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Conversion complete callback in non-blocking mode for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Extended Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Return the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
-{
-  uint32_t tmp = 0UL;
-
-  tmp |= hdac->Instance->DOR1;
-
-  tmp |= hdac->Instance->DOR2 << 16UL;
-
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx private functions
-  *  @brief    Extended private functions
-  * @{
-  */
-
-
-/**
-  * @brief  DMA conversion complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvCpltCallbackCh2(hdac);
-#else
-  HAL_DACEx_ConvCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvHalfCpltCallbackCh2(hdac);
-#else
-  HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA error callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ErrorCallbackCh2(hdac);
-#else
-  HAL_DACEx_ErrorCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c
deleted file mode 100644
index bedf33b7260..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c
+++ /dev/null
@@ -1,908 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Channel
-       (except for internal SRAM / FLASH memories: no initialization is
-       necessary). Please refer to the Reference manual for connection between peripherals
-       and DMA requests.
-
-   (#) For a given Channel, program the required configuration through the following parameters:
-       Channel request, Transfer Direction, Source and Destination data formats,
-       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
-       using HAL_DMA_Init() function.
-
-   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
-       detection.
-
-   (#) Use HAL_DMA_Abort() function to abort the current transfer
-
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
-           address and destination address and the Length of data to be transferred
-       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
-           case a fixed Timeout can be configured by User depending from his application.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
-       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
-           Source address and destination address and the Length of data to be transferred.
-           In this case the DMA interrupt is configured
-       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
-              add his own function to register callbacks with HAL_DMA_RegisterCallback().
-
-     *** DMA HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of macros in DMA HAL driver.
-
-       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
-       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
-       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
-       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
-       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
-       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
-
-     [..]
-      (@) You can refer to the DMA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @{
-  */
-
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Channel source
-    and destination addresses, incrementation and data sizes, transfer direction,
-    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp;
-
-  /* Check the DMA handle allocation */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
-#if defined (DMA2)
-  /* Compute the channel index */
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
-  {
-    /* DMA1 */
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
-    hdma->DmaBaseAddress = DMA1;
-  }
-  else
-  {
-    /* DMA2 */
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
-    hdma->DmaBaseAddress = DMA2;
-  }
-#else
-  /* calculation of the channel index */
-  /* DMA1 */
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
-  hdma->DmaBaseAddress = DMA1;
-#endif
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Get the CR register value */
-  tmp = hdma->Instance->CCR;
-
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE   | DMA_CCR_PSIZE  |
-                      DMA_CCR_MINC  | DMA_CCR_PINC    | DMA_CCR_CIRC   |
-                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
-
-  /* Prepare the DMA Channel configuration */
-  tmp |=  hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* Write to DMA Channel CR register */
-  hdma->Instance->CCR = tmp;
-
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state*/
-  hdma->State = HAL_DMA_STATE_READY;
-
-  /* Allocate lock resource and initialize it */
-  hdma->Lock = HAL_UNLOCKED;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the DMA peripheral.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-
-  /* Check the DMA handle allocation */
-  if (NULL == hdma )
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
-  /* Disable the selected DMA Channelx */
-  __HAL_DMA_DISABLE(hdma);
-
-#if defined (DMA2)
-  /* Compute the channel index */
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
-  {
-    /* DMA1 */
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
-    hdma->DmaBaseAddress = DMA1;
-  }
-  else
-  {
-    /* DMA2 */
-    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
-    hdma->DmaBaseAddress = DMA2;
-  }
-#else
-  /* calculation of the channel index */
-  /* DMA1 */
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
-  hdma->DmaBaseAddress = DMA1;
-#endif
-
-  /* Reset DMA Channel CR register */
-  hdma->Instance->CCR = 0U;
-
-  /* Clear all flags */
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-  /* Clean callbacks */
-  hdma->XferCpltCallback = NULL;
-  hdma->XferHalfCpltCallback = NULL;
-  hdma->XferErrorCallback = NULL;
-  hdma->XferAbortCallback = NULL;
-
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Input and Output operation functions
- *
-@verbatim
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the DMA Transfer.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Disable the peripheral */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Configure the source, destination address and the data length & clear flags*/
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    status = HAL_BUSY;
-  }
-  return status;
-}
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-    /* Disable the peripheral */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Configure the source, destination address and the data length & clear flags*/
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the transfer complete interrupt */
-    /* Enable the transfer Error interrupt */
-    if(NULL != hdma->XferHalfCpltCallback )
-    {
-      /* Enable the Half transfer complete interrupt as well */
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-    }
-    else
-    {
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
-    }
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Remain BUSY */
-    status = HAL_BUSY;
-  }
-  return status;
-}
-
-/**
-  * @brief  Abort the DMA Transfer.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the DMA peripheral state */
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    return status;
-  }
-}
-
-/**
-  * @brief  Aborts the DMA Transfer in Interrupt mode.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Disable DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Disable the channel */
-    __HAL_DMA_DISABLE(hdma);
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    /* Call User Abort callback */
-    if(hdma->XferAbortCallback != NULL)
-    {
-      hdma->XferAbortCallback(hdma);
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel Specifies the DMA level complete.
-  * @param  Timeout       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
-  uint32_t temp;
-  uint32_t tickstart;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* no transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    __HAL_UNLOCK(hdma);
-    return HAL_ERROR;
-  }
-
-  /* Polling mode not supported in circular mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-
-  /* Get the level transfer complete flag */
-  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
-  {
-    /* Transfer Complete flag */
-    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
-  }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while((hdma->DmaBaseAddress->ISR & temp) == 0U)
-  {
-    if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
-    {
-      /* When a DMA transfer error occurs */
-      /* A hardware clear of its EN bits is performed */
-      /* Clear all flags */
-      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-    }
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-
-  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
-  {
-    /* Clear the transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
-
-    /* The selected Channelx EN bit is cleared (DMA is disabled and
-    all transfers are complete) */
-    hdma->State = HAL_DMA_STATE_READY;
-  }
-  else
-  {
-    /* Clear the half transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle DMA interrupt request.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
-  uint32_t source_it = hdma->Instance->CCR;
-
-  /* Half Transfer Complete Interrupt management ******************************/
-  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
-  {
-    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-    {
-      /* Disable the half transfer interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-    }
-    /* Clear the half transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
-
-    /* DMA peripheral state is not updated in Half Transfer */
-    /* but in Transfer Complete case */
-
-    if(hdma->XferHalfCpltCallback != NULL)
-    {
-      /* Half transfer callback */
-      hdma->XferHalfCpltCallback(hdma);
-    }
-  }
-
-  /* Transfer Complete Interrupt management ***********************************/
-  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
-  {
-    
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-    {
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
-      /* Disable the transfer complete and error interrupt */
-      /* if the DMA mode is not CIRCULAR  */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-    }
-    /* Clear the transfer complete flag */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    if(hdma->XferCpltCallback != NULL)
-    {
-      /* Transfer complete callback */
-      hdma->XferCpltCallback(hdma);
-    }
-  }
-
-  /* Transfer Error Interrupt management **************************************/
-  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))
-  {
-    /* When a DMA transfer error occurs */
-    /* A hardware clear of its EN bits is performed */
-    /* Disable ALL DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
-    /* Clear all flags */
-    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-    /* Update error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
-    if (hdma->XferErrorCallback != NULL)
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-  else
-  {
-    /* Nothing To Do */
-  }
-  return;
-}
-
-/**
-  * @brief  Register callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Channel.
-  * @param  CallbackID           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @param  pCallback            pointer to private callbacsk function which has pointer to
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-     case  HAL_DMA_XFER_CPLT_CB_ID:
-           hdma->XferCpltCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-           hdma->XferHalfCpltCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_ERROR_CB_ID:
-           hdma->XferErrorCallback = pCallback;
-           break;
-
-     case  HAL_DMA_XFER_ABORT_CB_ID:
-           hdma->XferAbortCallback = pCallback;
-           break;
-
-     default:
-           status = HAL_ERROR;
-           break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Channel.
-  * @param  CallbackID           User Callback identifer
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-    /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-     case  HAL_DMA_XFER_CPLT_CB_ID:
-           hdma->XferCpltCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-           hdma->XferHalfCpltCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_ERROR_CB_ID:
-           hdma->XferErrorCallback = NULL;
-           break;
-
-     case  HAL_DMA_XFER_ABORT_CB_ID:
-           hdma->XferAbortCallback = NULL;
-           break;
-
-    case   HAL_DMA_XFER_ALL_CB_ID:
-           hdma->XferCpltCallback = NULL;
-           hdma->XferHalfCpltCallback = NULL;
-           hdma->XferErrorCallback = NULL;
-           hdma->XferAbortCallback = NULL;
-           break;
-
-    default:
-           status = HAL_ERROR;
-           break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief    Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the DMA handle state.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  /* Return DMA handle state */
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Channel.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear all flags */
-  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
-
-  /* Configure DMA Channel data length */
-  hdma->Instance->CNDTR = DataLength;
-
-  /* Memory to Peripheral */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CPAR = DstAddress;
-
-    /* Configure DMA Channel source address */
-    hdma->Instance->CMAR = SrcAddress;
-  }
-  /* Peripheral to Memory */
-  else
-  {
-    /* Configure DMA Channel source address */
-    hdma->Instance->CPAR = SrcAddress;
-
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CMAR = DstAddress;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c
deleted file mode 100644
index 9b7748df5d3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### EXTI Peripheral features #####
-  ==============================================================================
-  [..]
-    (+) Each Exti line can be configured within this driver.
-
-    (+) Exti line can be configured in 3 different modes
-        (++) Interrupt
-        (++) Event
-        (++) Both of them
-
-    (+) Configurable Exti lines can be configured with 3 different triggers
-        (++) Rising
-        (++) Falling
-        (++) Both of them
-
-    (+) When set in interrupt mode, configurable Exti lines have two different
-        interrupts pending registers which allow to distinguish which transition
-        occurs:
-        (++) Rising edge pending interrupt
-        (++) Falling
-
-    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
-        be selected through multiplexer.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-
-    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
-        (++) Choose the interrupt line number by setting "Line" member from
-             EXTI_ConfigTypeDef structure.
-        (++) Configure the interrupt and/or event mode using "Mode" member from
-             EXTI_ConfigTypeDef structure.
-        (++) For configurable lines, configure rising and/or falling trigger
-             "Trigger" member from EXTI_ConfigTypeDef structure.
-        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
-             member from GPIO_InitTypeDef structure.
-
-    (#) Get current Exti configuration of a dedicated line using
-        HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
-
-    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-
-    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
-        (++) Provide exiting handle as first parameter.
-        (++) Provide which callback will be registered using one value from
-             EXTI_CallbackIDTypeDef.
-        (++) Provide callback function pointer.
-
-    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup EXTI
-  * @{
-  */
-/** MISRA C:2012 deviation rule has been granted for following rule:
-  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
-  * of bounds [0,3] in following API :
-  * HAL_EXTI_SetConfigLine
-  * HAL_EXTI_GetConfigLine
-  * HAL_EXTI_ClearConfigLine
-  */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
-  *  @brief    Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on EXTI configuration to be set.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
-  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
-  /* Assign line number to handle */
-  hexti->Line = pExtiConfig->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* Configure triggers for configurable lines */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
-    /* Configure rising trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
-    {
-      EXTI->RTSR |= maskline;
-    }
-    else
-    {
-      EXTI->RTSR &= ~maskline;
-    }
-
-    /* Configure falling trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
-    {
-      EXTI->FTSR |= maskline;
-    }
-    else
-    {
-      EXTI->FTSR &= ~maskline;
-    }
-
-
-    /* Configure gpio port selection in case of gpio exti line */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  /* Configure interrupt mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
-  {
-    EXTI->IMR |= maskline;
-  }
-  else
-  {
-    EXTI->IMR &= ~maskline;
-  }
-
-  /* Configure event mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
-  {
-    EXTI->EMR |= maskline;
-  }
-  else
-  {
-    EXTI->EMR &= ~maskline;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on structure to store Exti configuration.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* Store handle line number to configuration structure */
-  pExtiConfig->Line = hexti->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Get core mode : interrupt */
-
-  /* Check if selected line is enable */
-  if ((EXTI->IMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
-  }
-  else
-  {
-    pExtiConfig->Mode = EXTI_MODE_NONE;
-  }
-
-  /* Get event mode */
-  /* Check if selected line is enable */
-  if ((EXTI->EMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode |= EXTI_MODE_EVENT;
-  }
-
-  /* Get default Trigger and GPIOSel configuration */
-  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
-  pExtiConfig->GPIOSel = 0x00u;
-
-  /* 2] Get trigger for configurable lines : rising */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->RTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
-    }
-
-    /* Get falling configuration */
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->FTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
-    }
-
-    /* Get Gpio port selection for gpio lines */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear whole configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Clear interrupt mode */
-  EXTI->IMR = (EXTI->IMR & ~maskline);
-
-  /* 2] Clear event mode */
-  EXTI->EMR = (EXTI->EMR & ~maskline);
-
-  /* 3] Clear triggers in case of configurable lines */
-  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
-  {
-    EXTI->RTSR = (EXTI->RTSR & ~maskline);
-    EXTI->FTSR = (EXTI->FTSR & ~maskline);
-
-    /* Get Gpio port selection for gpio lines */
-    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Register callback for a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  CallbackID User callback identifier.
-  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
-  * @param  pPendingCbfn function pointer to be stored as callback.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  switch (CallbackID)
-  {
-    case  HAL_EXTI_COMMON_CB_ID:
-      hexti->PendingCallback = pPendingCbfn;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Store line number as handle private field.
-  * @param  hexti Exti handle.
-  * @param  ExtiLine Exti line number.
-  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(ExtiLine));
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Store line number as handle private field */
-    hexti->Line = ExtiLine;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
-  *  @brief EXTI IO functions.
-  *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Handle EXTI interrupt request.
-  * @param  hexti Exti handle.
-  * @retval none.
-  */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t maskline;
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Get pending bit  */
-  regval = (EXTI->PR & maskline);
-  if (regval != 0x00u)
-  {
-    /* Clear pending bit */
-    EXTI->PR = maskline;
-
-    /* Call callback */
-    if (hexti->PendingCallback != NULL)
-    {
-      hexti->PendingCallback();
-    }
-  }
-}
-
-/**
-  * @brief  Get interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be checked.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval 1 if interrupt is pending else 0.
-  */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* return 1 if bit is set else 0 */
-  regval = ((EXTI->PR & maskline) >> linepos);
-  return regval;
-}
-
-/**
-  * @brief  Clear interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be clear.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval None.
-  */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Clear Pending bit */
-  EXTI->PR =  maskline;
-}
-
-/**
-  * @brief  Generate a software interrupt for a dedicated line.
-  * @param  hexti Exti handle.
-  * @retval None.
-  */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Generate Software interrupt */
-  EXTI->SWIER = maskline;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c
deleted file mode 100644
index 38d07cf4431..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c
+++ /dev/null
@@ -1,726 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash.c
-  * @author  MCD Application Team
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-      prefetch. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) Option Bytes programming
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]                             
-      This driver provides functions and macros to configure and program the FLASH 
-      memory of all STM32L1xx devices.
-    
-      (#) FLASH Memory I/O Programming functions: this group includes all needed
-          functions to erase and program the main memory:
-        (++) Lock and Unlock the FLASH interface
-        (++) Erase function: Erase page
-        (++) Program functions: Fast Word and Half Page(should be 
-        executed from internal SRAM).
-  
-      (#) DATA EEPROM Programming functions: this group includes all 
-          needed functions to erase and program the DATA EEPROM memory:
-        (++) Lock and Unlock the DATA EEPROM interface.
-        (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase 
-             Double Word (should be executed from internal SRAM).
-        (++) Program functions: Fast Program Byte, Fast Program Half-Word, 
-             FastProgramWord, Program Byte, Program Half-Word, 
-             Program Word and Program Double-Word (should be executed 
-             from internal SRAM).
-
-      (#) FLASH Option Bytes Programming functions: this group includes all needed
-          functions to manage the Option Bytes:
-        (++) Lock and Unlock the Option Bytes
-        (++) Set/Reset the write protection
-        (++) Set the Read protection Level
-        (++) Program the user Option Bytes
-        (++) Launch the Option Bytes loader
-        (++) Set/Get the Read protection Level.
-        (++) Set/Get the BOR level.
-        (++) Get the Write protection.
-        (++) Get the user option bytes.
-    
-      (#) Interrupts and flags management functions : this group 
-          includes all needed functions to:
-        (++) Handle FLASH interrupts
-        (++) Wait for last FLASH operation according to its status
-        (++) Get error flag status
-
-    (#) FLASH Interface configuration functions: this group includes 
-      the management of following features:
-      (++) Enable/Disable the RUN PowerDown mode.
-      (++) Enable/Disable the SLEEP PowerDown mode.  
-  
-    (#) FLASH Peripheral State methods: this group includes 
-      the management of following features:
-      (++) Wait for the FLASH operation
-      (++)  Get the specific FLASH error flag
-    
-  [..] In addition to these function, this driver includes a set of macros allowing
-       to handle the following operations:
-      
-      (+) Set/Get the latency
-      (+) Enable/Disable the prefetch buffer
-      (+) Enable/Disable the 64 bit Read Access.
-      (+) Enable/Disable the Flash power-down
-      (+) Enable/Disable the FLASH interrupts
-      (+) Monitor the FLASH flags status
-          
-                 ##### Programming operation functions #####
-  ===============================================================================  
-     [..]
-     This subsection provides a set of functions allowing to manage the FLASH 
-     program operations.
-  
-    [..] The FLASH Memory Programming functions, includes the following functions:
-     (+) HAL_FLASH_Unlock(void);
-     (+) HAL_FLASH_Lock(void);
-     (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-     (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and 
-         program memory access.
-     (#) Call the desired function to erase page or program data.
-     (#) Call the HAL_FLASH_Lock() to disable the flash program memory access 
-        (recommended to protect the FLASH memory against possible unwanted operation).
-  
-               ##### Option Bytes Programming functions ##### 
-   ==============================================================================  
-  
-     [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
-     (+) HAL_FLASH_OB_Unlock(void);
-     (+) HAL_FLASH_OB_Lock(void);
-     (+) HAL_FLASH_OB_Launch(void);
-     (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-     (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control 
-         register access.
-     (#) Call the following functions to program the desired option bytes.
-         (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);      
-     (#) Once all needed option bytes to be programmed are correctly written, call the
-         HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-     (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-         to protect the option Bytes against possible unwanted operations).
-  
-    [..] Proprietary code Read Out Protection (PcROP):    
-    (#) The PcROP sector is selected by using the same option bytes as the Write
-        protection. As a result, these 2 options are exclusive each other.
-    (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:
-        (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macro ---------------------------- ---------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
- 
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
-  * @{
-  */
-/* Variables used for Erase pages under interruption*/
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
-  * @{
-  */
-static  void   FLASH_SetErrorCode(void);
-extern void    FLASH_PageErase(uint32_t PageAddress);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
-  *  @brief   Programming operation functions 
-  *
-@verbatim   
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  *
-  * @param  TypeProgram   Indicate the way to program at a specified address.
-  *                       This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address       Specifie the address to be programmed.
-  * @param  Data          Specifie the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /*Program word (32-bit) at a specified address.*/
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Program word at a specified address  with interrupt enabled.
-  *
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *                      This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address      Specifie the address to be programmed.
-  * @param  Data         Specifie the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Enable End of FLASH Operation and Error source interrupts */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-  
-  pFlash.Address = Address;
-  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  /* Clean the error context */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-  {
-    /* Program word (32-bit) at a specified address. */
-    *(__IO uint32_t *)Address = Data;
-  }
-  return status;
-}
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t addresstmp = 0U;
-  
-  /* Check FLASH operation error flags */
-  if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     || 
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     || 
-#if defined(FLASH_SR_RDERR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      || 
-#endif /* FLASH_SR_RDERR */
-#if defined(FLASH_SR_OPTVERRUSR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || 
-#endif /* FLASH_SR_OPTVERRUSR */
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )
-  {
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-    {
-      /* Return the faulty sector */
-      addresstmp = pFlash.Page;
-      pFlash.Page = 0xFFFFFFFFU;
-    }
-    else
-    {
-      /* Return the faulty address */
-      addresstmp = pFlash.Address;
-    }
-    /* Save the Error code */
-    FLASH_SetErrorCode();
-    
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(addresstmp);
-
-    /* Stop the procedure ongoing */
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    
-    /* Process can continue only if no error detected */
-    if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
-    {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-      {
-        /* Nb of pages to erased can be decreased */
-        pFlash.NbPagesToErase--;
-
-        /* Check if there are still pages to erase */
-        if(pFlash.NbPagesToErase != 0U)
-        {
-          addresstmp = pFlash.Page;
-          /*Indicate user which sector has been erased */
-          HAL_FLASH_EndOfOperationCallback(addresstmp);
-
-          /*Increment sector number*/
-          addresstmp = pFlash.Page + FLASH_PAGE_SIZE;
-          pFlash.Page = addresstmp;
-
-          /* If the erase operation is completed, disable the ERASE Bit */
-          CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-          FLASH_PageErase(addresstmp);
-        }
-        else
-        {
-          /* No more pages to Erase, user callback can be called. */
-          /* Reset Sector and stop Erase pages procedure */
-          pFlash.Page = addresstmp = 0xFFFFFFFFU;
-          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-          /* FLASH EOP interrupt user callback */
-          HAL_FLASH_EndOfOperationCallback(addresstmp);
-        }
-      }
-      else
-      {
-          /* If the program operation is completed, disable the PROG Bit */
-          CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-          /* Program ended. Return the selected address */
-          /* FLASH EOP interrupt user callback */
-          HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-        
-          /* Reset Address and stop Program procedure */
-          pFlash.Address = 0xFFFFFFFFU;
-          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-      }
-    }
-  }
-  
-
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Operation is completed, disable the PROG and ERASE */
-    CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));
-
-    /* Disable End of FLASH Operation and Error source interrupts */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                 - Pages Erase: Address of the page which has been erased 
-  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                 - Pages Erase: Address of the page which returned an error
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
-  {
-    /* Unlocking FLASH_PECR register access*/
-    if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-    {  
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
-      
-      /* Verify that PELOCK is unlocked */
-      if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-      {
-        return HAL_ERROR;
-      }
-    }
-    
-    /* Unlocking the program memory access */
-    WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
-    WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);  
-    
-    /* Verify that PRGLOCK is unlocked */
-    if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
-    {
-      return HAL_ERROR;
-    }
-  }
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the PRGLOCK Bit to lock the FLASH Registers access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
-  {
-    /* Unlocking FLASH_PECR register access*/
-    if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-    {  
-      /* Unlocking FLASH_PECR register access*/
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
-      WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
-
-      /* Verify that PELOCK is unlocked */
-      if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    /* Unlocking the option bytes block access */
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
-    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
-
-    /* Verify that OPTLOCK is unlocked */
-    if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
-    {
-      return HAL_ERROR;
-    }
-  }
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the option bytes block access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
-  
-  return HAL_OK;  
-}
-  
-/**
-  * @brief  Launch the option byte loading.
-  * @note   This function will reset automatically the MCU.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OBL_Launch bit to launch the option byte loading */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
-  
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
-}
-
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions 
- *  @brief    Peripheral errors functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time errors of  the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode The returned value can be:
-  *            @ref FLASH_Error_Codes
-  */
-uint32_t HAL_FLASH_GetError(void)
-{
-   return pFlash.ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout  maximum flash operation timeout
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-     
-  uint32_t tickstart = HAL_GetTick();
-     
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
-  { 
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
-#if defined(FLASH_SR_RDERR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || 
-#endif /* FLASH_SR_RDERR */
-#if defined(FLASH_SR_OPTVERRUSR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || 
-#endif /* FLASH_SR_OPTVERRUSR */
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || 
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* There is no error flag set */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{
-  uint32_t flags = 0U;
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-    flags |= FLASH_FLAG_WRPERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-    flags |= FLASH_FLAG_PGAERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
-    flags |= FLASH_FLAG_OPTVERR;
-  }
-
-#if defined(FLASH_SR_RDERR)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    flags |= FLASH_FLAG_RDERR;
-  }
-#endif /* FLASH_SR_RDERR */
-#if defined(FLASH_SR_OPTVERRUSR)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
-    flags |= FLASH_FLAG_OPTVERRUSR;
-  }
-#endif /* FLASH_SR_OPTVERRUSR */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE;
-    flags |= FLASH_FLAG_SIZERR;
-  }
-  /* Clear FLASH error pending bits */
-  __HAL_FLASH_CLEAR_FLAG(flags);
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c
deleted file mode 100644
index d2284d3e3de..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c
+++ /dev/null
@@ -1,1873 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended FLASH HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the internal FLASH memory:
-  *            + FLASH Interface configuration
-  *            + FLASH Memory Erasing
-  *            + DATA EEPROM Programming/Erasing
-  *            + Option Bytes Programming
-  *            + Interrupts management
-  *
-  @verbatim
-  ==============================================================================
-               ##### Flash peripheral Extended features  #####
-  ==============================================================================
-
-  [..] Comparing to other products, the FLASH interface for STM32L1xx
-       devices contains the following additional features
-       (+) Erase functions
-       (+) DATA_EEPROM memory management
-       (+) BOOT option bit configuration
-       (+) PCROP protection for all sectors
-
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory
-       of all STM32L1xx. It includes:
-       (+) Full DATA_EEPROM erase and program management
-       (+) Boot activation
-       (+) PCROP protection configuration and control for all pages
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
-  * @{
-  */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
- * @{
- */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-void                      FLASH_PageErase(uint32_t PageAddress);
-static HAL_StatusTypeDef  FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState);
-static void               FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState);
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-static void               FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState);
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)   \
- || defined(STM32L162xE)
-static void               FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState);
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-static void               FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState);
-#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */
-#if defined(FLASH_OBR_SPRMOD)
-static HAL_StatusTypeDef  FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState);
-#endif /* FLASH_OBR_SPRMOD */
-#if defined(FLASH_OBR_nRST_BFB2)
-static HAL_StatusTypeDef  FLASH_OB_BootConfig(uint8_t OB_BOOT);
-#endif /* FLASH_OBR_nRST_BFB2 */
-static HAL_StatusTypeDef  FLASH_OB_RDPConfig(uint8_t OB_RDP);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-static HAL_StatusTypeDef  FLASH_OB_BORConfig(uint8_t OB_BOR);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint8_t            FLASH_OB_GetUser(void);
-static uint8_t            FLASH_OB_GetBOR(void);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
- *  @brief   FLASH Memory Erasing functions
- *
-@verbatim
-  ==============================================================================
-                ##### FLASH Erasing Programming functions #####
-  ==============================================================================
-
-    [..] The FLASH Memory Erasing functions, includes the following functions:
-    (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
-    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
-        is called with parameter 0xFFFFFFFF
-
-    [..] Any operation of erase should follow these steps:
-    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
-        program memory access.
-    (#) Call the desired function to erase page.
-    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
-       (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Erase the specified FLASH memory Pages
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @note   For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between
-  *         2 banks, user should perform pages erase by bank only.
-  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @param[out]  PageError pointer to variable  that
-  *         contains the configuration information on faulty page in case of error
-  *         (0xFFFFFFFF means that all the pages have been correctly erased)
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t address = 0U;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /*Initialization of PageError variable*/
-    *PageError = 0xFFFFFFFFU;
-
-    /* Check the parameters */
-    assert_param(IS_NBPAGES(pEraseInit->NbPages));
-    assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
-
-#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)
-    /* Check on which bank belongs the 1st address to erase */
-    if (pEraseInit->PageAddress < FLASH_BANK2_BASE)
-    {
-      /* BANK1 */
-      /* Check that last page to erase still belongs to BANK1 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
-      {
-        /*  Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
-            continuous */
-        /* Process Unlocked */
-        __HAL_UNLOCK(&pFlash);
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* BANK2 */
-      /* Check that last page to erase still belongs to BANK2 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
-      {
-        /*  Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
-            continuous */
-        /* Process Unlocked */
-        __HAL_UNLOCK(&pFlash);
-        return HAL_ERROR;
-      }
-    }
-#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */
-
-    /* Erase page by page to be done*/
-    for(address = pEraseInit->PageAddress;
-        address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
-        address += FLASH_PAGE_SIZE)
-    {
-      FLASH_PageErase(address);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-      /* If the erase operation is completed, disable the ERASE Bit */
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-      if (status != HAL_OK)
-      {
-        /* In case of error, stop erase procedure and return the faulty address */
-        *PageError = address;
-        break;
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a page erase of the specified FLASH memory pages  with interrupt enabled
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  *          End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter
-  *          0xFFFFFFFF
-  * @note   For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between
-  *         2 banks, user should perform pages erase by bank only.
-  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* If procedure already ongoing, reject the next one */
-  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_NBPAGES(pEraseInit->NbPages));
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)
-    /* Check on which bank belongs the 1st address to erase */
-    if (pEraseInit->PageAddress < FLASH_BANK2_BASE)
-    {
-      /* BANK1 */
-      /* Check that last page to erase still belongs to BANK1 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
-      {
-        /*  Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
-            continuous */
-        /* Process Unlocked */
-        __HAL_UNLOCK(&pFlash);
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* BANK2 */
-      /* Check that last page to erase still belongs to BANK2 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
-      {
-        /*  Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
-            continuous */
-        /* Process Unlocked */
-        __HAL_UNLOCK(&pFlash);
-        return HAL_ERROR;
-      }
-    }
-#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /* Enable End of FLASH Operation and Error source interrupts */
-    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
-    pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
-    pFlash.NbPagesToErase = pEraseInit->NbPages;
-    pFlash.Page = pEraseInit->PageAddress;
-
-    /*Erase 1st page and wait for IT*/
-    FLASH_PageErase(pEraseInit->PageAddress);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- *  @brief   Option Bytes Programming functions
- *
-@verbatim
-  ==============================================================================
-                ##### Option Bytes Programming functions #####
-  ==============================================================================
-
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the @ref HAL_FLASH_OB_Unlock() function to enable the Flash option control
-        register access.
-    (#) Call following function to program the desired option bytes.
-        (++) @ref HAL_FLASHEx_OBProgram:
-         - To Enable/Disable the desired sector write protection.
-         - To set the desired read Protection Level.
-         - To configure the user option Bytes: IWDG, STOP and the Standby.
-         - To Set the BOR level.
-    (#) Once all needed option bytes to be programmed are correctly written, call the
-        @ref HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-    (#) Call the @ref HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-        to protect the option Bytes against possible unwanted operations).
-
-    [..] Proprietary code Read Out Protection (PcROP):
-    (#) The PcROP sector is selected by using the same option bytes as the Write
-        protection (nWRPi bits). As a result, these 2 options are exclusive each other.
-    (#) In order to activate the PcROP (change the function of the nWRPi option bits),
-        the SPRMOD option bit must be activated.
-    (#) The active value of nWRPi bits is inverted when PCROP mode is active, this
-        means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i"
-        is read/write protected.
-    (#) To activate PCROP mode for Flash sector(s), you need to call the following function:
-        (++) @ref HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected
-        (++) @ref HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection
-    (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program option bytes
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /*Write protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
-    {
-      /* Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_WRPConfig(pOBInit, ENABLE);
-    }
-    else
-    {
-      /* Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_WRPConfig(pOBInit, DISABLE);
-    }
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-
-  /* Read protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-
-  /* USER  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW,
-                                 pOBInit->USERConfig & OB_STOP_NORST,
-                                 pOBInit->USERConfig & OB_STDBY_NORST);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-
-  /* BOR Level  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BORConfig(pOBInit->BORLevel);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      return status;
-    }
-  }
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Get the Option byte configuration
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
-
-  /*Get WRP1*/
-  pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1);
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-
-  /*Get WRP2*/
-  pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2);
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-
-  /*Get WRP3*/
-  pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3);
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-
-  /*Get WRP4*/
-  pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4);
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel   = FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel   = FLASH_OB_GetBOR();
-}
-
-#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
-
-/**
-  * @brief  Program option bytes
-  * @note   This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_OBEX(pAdvOBInit->OptionType));
-
-#if defined(FLASH_OBR_SPRMOD)
-
-  /* Program PCROP option byte*/
-  if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
-  {
-    /* Check the parameters */
-    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
-    if (pAdvOBInit->PCROPState == OB_PCROP_STATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE);
-      if (status != HAL_OK)
-      {
-        return status;
-      }
-    }
-    else
-    {
-      /* Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE);
-      if (status != HAL_OK)
-      {
-        return status;
-      }
-    }
-  }
-
-#endif /* FLASH_OBR_SPRMOD */
-
-#if defined(FLASH_OBR_nRST_BFB2)
-
-  /* Program BOOT config option byte */
-  if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
-  {
-    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
-  }
-
-#endif /* FLASH_OBR_nRST_BFB2 */
-
-  return status;
-}
-
-/**
-  * @brief  Get the OBEX byte configuration
-  * @note   This function can be used only for Cat2  & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval None
-  */
-void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  pAdvOBInit->OptionType = 0U;
-
-#if defined(FLASH_OBR_SPRMOD)
-
-  pAdvOBInit->OptionType |= OPTIONBYTE_PCROP;
-
-  /*Get PCROP state */
-  pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD);
-
-  /*Get PCROP protected sector from 0 to 31 */
-  pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1;
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
-
-  /*Get PCROP protected sector from 32 to 63 */
-  pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2;
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#endif /* FLASH_OBR_SPRMOD */
-
-#if defined(FLASH_OBR_nRST_BFB2)
-
-  pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;
-
-  /* Get Boot config OB */
-  pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U;
-
-#endif /* FLASH_OBR_nRST_BFB2 */
-}
-
-#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
-
-#if defined(FLASH_OBR_SPRMOD)
-
-/**
-  * @brief  Select the Protection Mode (SPRMOD).
-  * @note   This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices
-  * @note   Once SPRMOD bit is active, unprotection of a protected sector is not possible
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0U;
-  uint32_t tmp2 = 0U;
-  uint8_t optiontmp = 0U;
-  uint16_t optiontmp2 = 0U;
-
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE));
-
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp);
-
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* program PCRop */
-    OB->RDP = tmp2;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Read protection operation Status */
-  return status;
-}
-
-/**
-  * @brief  Deselect the Protection Mode (SPRMOD).
-  * @note   This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices
-  * @note   Once SPRMOD bit is active, unprotection of a protected sector is not possible
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0U;
-  uint32_t tmp2 = 0U;
-  uint8_t optiontmp = 0U;
-  uint16_t optiontmp2 = 0U;
-
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE));
-
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp);
-
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* program PCRop */
-    OB->RDP = tmp2;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Read protection operation Status */
-  return status;
-}
-
-#endif /* FLASH_OBR_SPRMOD */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions
- *  @brief   DATA EEPROM Programming functions
- *
-@verbatim
- ===============================================================================
-                     ##### DATA EEPROM Programming functions #####
- ===============================================================================
-
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access
-        and Flash program erase control register access.
-    (#) Call the desired function to erase or program data.
-    (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access
-        and Flash program erase control register access(recommended
-        to protect the DATA_EEPROM against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlocks the data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void)
-{
-  if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-  {
-    /* Unlocking the Data memory and FLASH_PECR register access*/
-    FLASH->PEKEYR = FLASH_PEKEY1;
-    FLASH->PEKEYR = FLASH_PEKEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Locks the Data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)
-{
-  /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Erase a word in data memory.
-  * @param  Address specifies the address to be erased.
-  * @param  TypeErase  Indicate the way to erase at a specified address.
-  *         This parameter can be a value of @ref FLASH_Type_Program
-  * @note   To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access
-  *         and Flash program erase control register access(recommended to protect
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_TYPEERASEDATA(TypeErase));
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    if(TypeErase == FLASH_TYPEERASEDATA_WORD)
-    {
-      /* Write 00000000h to valid address in the data memory */
-      *(__IO uint32_t *) Address = 0x00000000U;
-    }
-
-    if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD)
-    {
-      /* Write 0000h to valid address in the data memory */
-      *(__IO uint16_t *) Address = (uint16_t)0x0000;
-    }
-
-    if(TypeErase == FLASH_TYPEERASEDATA_BYTE)
-    {
-      /* Write 00h to valid address in the data memory */
-      *(__IO uint8_t *) Address = (uint8_t)0x00;
-    }
-
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before
-  *         this function to configure the Fixed Time Programming.
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *         This parameter can be a value of @ref FLASHEx_Type_Program_Data
-  * @param  Address  specifie the address to be programmed.
-  * @param  Data     specifie the data to be programmed
-  *
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-
-HAL_StatusTypeDef   HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMDATA(TypeProgram));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)
-    {
-      /* Program word (32-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
-    {
-      /* Program halfword (16-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
-    {
-      /* Program byte (8-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)
-    {
-      /*Program word (8-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
-    {
-      /* Program halfword (16-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
-    {
-      /* Program word (32-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Enable DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void)
-{
-  SET_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-}
-
-/**
-  * @brief  Disables DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
-{
-  CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-
-/*
-==============================================================================
-              OPTIONS BYTES
-==============================================================================
-*/
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note   To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function
-  *         must be called before.
-  * @param  OB_RDP specifies the read protection level.
-  *   This parameter can be:
-  *     @arg @ref OB_RDP_LEVEL_0 No protection
-  *     @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
-  *     @arg @ref OB_RDP_LEVEL_2 Chip protection
-  *
-  *  !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0
-  *
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_RDP(OB_RDP));
-
-  tmp1 = (uint32_t)(OB->RDP & FLASH_OBR_RDPRT);
-
-  /* According to errata sheet, DocID022054 Rev 5, par2.1.5
-  Before setting Level0 in the RDP register, check that the current level is not equal to Level0.
-  If the current level is not equal to Level0, Level0 can be activated.
-  If the current level is Level0 then the RDP register must not be written again with Level0. */
-
-  if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0))
-  {
-    /*current level is Level0 then the RDP register must not be written again with Level0. */
-    status = HAL_ERROR;
-  }
-  else
-  {
-#if defined(FLASH_OBR_SPRMOD)
-    /* Mask SPRMOD bit */
-    tmp3 = (uint32_t)(OB->RDP & FLASH_OBR_SPRMOD);
-#endif
-
-    /* calculate the option byte to write */
-    tmp1 = (~((uint32_t)(OB_RDP | tmp3)));
-    tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3)));
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-    if(status == HAL_OK)
-    {
-      /* Clean the error context */
-      pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-      /* program read protection level */
-      OB->RDP = tmp2;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-  }
-
-  /* Return the Read protection operation Status */
-  return status;
-}
-
-/**
-  * @brief  Programs the FLASH brownout reset threshold level Option Byte.
-  * @param  OB_BOR Selects the brownout reset threshold level.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD
-  *                      power supply reaches the PDR(Power Down Reset) threshold (1.5V)
-  *     @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
-  *     @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0U, tmp1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(OB_BOR));
-
-  /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U);
-
-  /* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/
-  tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U;
-  tmp |= (OB_BOR | tmp1);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the BOR Option Byte */
-    OB->USER = tmp;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Option Byte BOR Programming Status */
-  return status;
-}
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @retval The FLASH User Option Bytes.
-  */
-static uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return (uint8_t)((FLASH->OBR & (FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U);
-}
-
-/**
-  * @brief  Returns the FLASH Read Protection level.
-  * @retval FLASH RDP level
-  *         This parameter can be one of the following values:
-  *            @arg @ref OB_RDP_LEVEL_0 No protection
-  *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
-  *            @arg @ref OB_RDP_LEVEL_2 Full chip protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  uint8_t rdp_level = (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT);
-
-  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
-  {
-    return (OB_RDP_LEVEL_1);
-  }
-  else
-  {
-    return (rdp_level);
-  }
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval The BOR level Option Bytes.
-  */
-static uint8_t FLASH_OB_GetBOR(void)
-{
-  /* Return the BOR level */
-  return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U);
-}
-
-/**
-  * @brief  Write protects the desired pages of the first 64KB of the Flash.
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains WRP parameters.
-  * @param  NewState new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval HAL_StatusTypeDef
-  */
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* WRP for sector between 0 to 31 */
-    if (pOBInit->WRPSector0To31 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState);
-    }
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-
-    /* Pages for Cat3, Cat4 & Cat5 devices*/
-    /* WRP for sector between 32 to 63 */
-    if (pOBInit->WRPSector32To63 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState);
-    }
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-
-    /* Pages for devices with FLASH >= 256KB*/
-    /* WRP for sector between 64 to 95 */
-    if (pOBInit->WRPSector64To95 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState);
-    }
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-
-    /* Pages for Cat5 devices*/
-    /* WRP for sector between 96 to 127 */
-    if (pOBInit->WRPSector96To127 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState);
-    }
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the write protection operation Status */
-  return status;
-}
-
-#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
- || defined(STM32L162xC)
-/**
-  * @brief  Enables the read/write protection (PCROP) of the desired
-  *         sectors.
-  * @note   This function can be used only for Cat2 & Cat3 devices
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains PCROP parameters.
-  * @param  NewState new state of the specified FLASH Pages read/Write protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  FunctionalState pcropstate = DISABLE;
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  /* Invert state to use same function of WRP */
-  if (NewState == DISABLE)
-  {
-    pcropstate = ENABLE;
-  }
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Pages for Cat2 devices*/
-    /* PCROP for sector between 0 to 31 */
-    if (pAdvOBInit->PCROPSector0To31 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate);
-    }
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
-
-    /* Pages for Cat3 devices*/
-    /* WRP for sector between 32 to 63 */
-    if (pAdvOBInit->PCROPSector32To63 != 0U)
-    {
-      FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate);
-    }
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC  */
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the write protection operation Status */
-  return status;
-}
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-/**
-  * @brief  Write protects the desired pages of the first 128KB of the Flash.
-  * @param  WRP1OrPCROP1 specifies the address of the pages to be write protected.
-  *   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1
-  * @param  NewState new state of the specified FLASH Pages Write protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState)
-{
-  uint32_t wrp01data = 0U, wrp23data = 0U;
-
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP(WRP1OrPCROP1));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));
-    wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23)));
-    tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data);
-    OB->WRP01 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data);
-    OB->WRP23 = tmp2;
-  }
-  else
-  {
-    wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01));
-    wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23)));
-
-    tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data);
-    OB->WRP01 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data);
-    OB->WRP23 = tmp2;
-  }
-}
-
-#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)    \
- || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
- || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD)  \
- || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
-/**
-  * @brief  Enable Write protects the desired pages of the second 128KB of the Flash.
-  * @note   This function can be used only for Cat3, Cat4  & Cat5 devices.
-  * @param  WRP2OrPCROP2 specifies the address of the pages to be write protected.
-  *   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2
-  * @param  NewState new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState)
-{
-  uint32_t wrp45data = 0U, wrp67data = 0U;
-
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP(WRP2OrPCROP2));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));
-    wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67)));
-    tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data);
-    OB->WRP45 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data);
-    OB->WRP67 = tmp2;
-  }
-  else
-  {
-    wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45));
-    wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67)));
-
-    tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data);
-    OB->WRP45 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data);
-    OB->WRP67 = tmp2;
-  }
-}
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
- || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE)  \
- || defined(STM32L162xE)
-/**
-  * @brief  Enable Write protects the desired pages of the third 128KB of the Flash.
-  * @note   This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD  & Cat5 devices.
-  * @param  WRP3 specifies the address of the pages to be write protected.
-  *   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3
-  * @param  NewState new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
-{
-  uint32_t wrp89data = 0U, wrp1011data = 0U;
-
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP(WRP3));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));
-    wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011)));
-    tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data);
-    OB->WRP89 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data);
-    OB->WRP1011 = tmp2;
-  }
-  else
-  {
-    wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89));
-    wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011)));
-
-    tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data);
-    OB->WRP89 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data);
-    OB->WRP1011 = tmp2;
-  }
-}
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
- || defined(STM32L152xDX) || defined(STM32L162xDX)
-/**
-  * @brief  Enable Write protects the desired pages of the Fourth 128KB of the Flash.
-  * @note   This function can be used only for Cat5 & STM32L1xxDX devices.
-  * @param  WRP4 specifies the address of the pages to be write protected.
-  *   This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4
-  * @param  NewState new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
-{
-  uint32_t wrp1213data = 0U, wrp1415data = 0U;
-
-  uint32_t tmp1 = 0U, tmp2 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP(WRP4));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));
-    wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415)));
-    tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data);
-    OB->WRP1213 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data);
-    OB->WRP1415 = tmp2;
-  }
-  else
-  {
-    wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213));
-    wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415)));
-
-    tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data);
-    OB->WRP1213 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data);
-    OB->WRP1415 = tmp2;
-  }
-}
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  OB_IWDG Selects the WDG mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_IWDG_SW Software WDG selected
-  *     @arg @ref OB_IWDG_HW Hardware WDG selected
-  * @param  OB_STOP Reset event when entering STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_STOP_NORST No reset generated when entering in STOP
-  *     @arg @ref OB_STOP_RST Reset generated when entering in STOP
-  * @param  OB_STDBY Reset event when entering Standby mode.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY
-  *     @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0U, tmp1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~(FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U);
-
-  /* Calculate the user option byte to write */
-  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U);
-  tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the User Option Byte */
-    OB->USER = tmp;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#if defined(FLASH_OBR_nRST_BFB2)
-/**
-  * @brief  Configures to boot from Bank1 or Bank2.
-  * @param  OB_BOOT select the FLASH Bank to boot from.
-  *   This parameter can be one of the following values:
-  *     @arg @ref OB_BOOT_BANK2 At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
-  *        depending on the activation of the bank. The active banks are checked in
-  *        the following order: Bank2, followed by Bank1.
-  *        The active bank is recognized by the value programmed at the base address
-  *        of the respective bank (corresponding to the initial stack pointer value
-  *        in the interrupt vector table).
-  *     @arg @ref OB_BOOT_BANK1 At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank1(Default).
-  *        For more information, please refer to AN2606 from www.st.com.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0U, tmp1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT_BANK(OB_BOOT));
-
-  /* Get the User Option byte register  and BOR Level*/
-  tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U);
-
-  /* Calculate the option byte to write */
-  tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U;
-  tmp |= (OB_BOOT | tmp1);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clean the error context */
-    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-    /* Write the BOOT Option Byte */
-    OB->USER = tmp;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#endif /* FLASH_OBR_nRST_BFB2 */
-
-/*
-==============================================================================
-              DATA
-==============================================================================
-*/
-
-/**
-  * @brief  Write a Byte at a specified address in data memory.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0U, tmpaddr = 0U;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    /* Possible only on Cat1 devices */
-    if(Data != (uint8_t)0x00U)
-    {
-      /* If the previous operation is completed, proceed to write the new Data */
-      *(__IO uint8_t *)Address = Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      tmpaddr = Address & 0xFFFFFFFCU;
-      tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
-      tmp &= ~tmpaddr;
-      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
-      /* Process Locked */
-      __HAL_LOCK(&pFlash);
-    }
-#else /*!Cat1*/
-    /* If the previous operation is completed, proceed to write the new Data */
-    *(__IO uint8_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Writes a half word at a specified address in data memory.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0U, tmpaddr = 0U;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    /* Possible only on Cat1 devices */
-    if(Data != (uint16_t)0x0000U)
-    {
-      /* If the previous operation is completed, proceed to write the new data */
-      *(__IO uint16_t *)Address = Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      if((Address & 0x3U) != 0x3U)
-      {
-        tmpaddr = Address & 0xFFFFFFFCU;
-        tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
-        tmp &= ~tmpaddr;
-        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
-        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
-      }
-      else
-      {
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
-      }
-      /* Process Locked */
-      __HAL_LOCK(&pFlash);
-    }
-#else /* !Cat1 */
-    /* If the previous operation is completed, proceed to write the new data */
-    *(__IO uint16_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address in data memory.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-
-    /* If the previous operation is completed, proceed to program the new data */
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Write a Byte at a specified address in data memory without erase.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0U, tmpaddr = 0U;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    if(Data != (uint8_t) 0x00U)
-    {
-      *(__IO uint8_t *)Address = Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-    }
-    else
-    {
-      tmpaddr = Address & 0xFFFFFFFCU;
-      tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
-      tmp &= ~tmpaddr;
-      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
-      /* Process Locked */
-      __HAL_LOCK(&pFlash);
-    }
-#else /* Not Cat1*/
-    *(__IO uint8_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Writes a half word at a specified address in data memory without erase.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0U, tmpaddr = 0U;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    if(Data != (uint16_t)0x0000U)
-    {
-      *(__IO uint16_t *)Address = Data;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&pFlash);
-      if((Address & 0x3U) != 0x3U)
-      {
-        tmpaddr = Address & 0xFFFFFFFCU;
-        tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
-        tmp &= ~tmpaddr;
-        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
-        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
-      }
-      else
-      {
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
-      }
-      /* Process Locked */
-      __HAL_LOCK(&pFlash);
-    }
-#else /* Not Cat1*/
-    *(__IO uint16_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address in data memory without erase.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-  if(status == HAL_OK)
-  {
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
-  * @brief  Erases a specified page in program memory.
-  * @param  PageAddress The page address in program memory to be erased.
-  * @note   A Page is erased in the Program memory only if the address to load
-  *         is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
-  * @retval None
-  */
-void FLASH_PageErase(uint32_t PageAddress)
-{
-  /* Clean the error context */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-  /* Set the ERASE bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-  /* Set PROG bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-  /* Write 00000000h to the first word of the program page to erase */
-  *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c
deleted file mode 100644
index 5b0bf983bfa..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ramfunc.c
-  * @author  MCD Application Team
-  * @brief   FLASH RAMFUNC driver.
-  *          This file provides a Flash firmware functions which should be 
-  *          executed from internal SRAM
-  *
-  *  @verbatim
-
-    *** ARM Compiler ***
-    --------------------
-    [..] RAM functions are defined using the toolchain options. 
-         Functions that are be executed in RAM should reside in a separate
-         source module. Using the 'Options for File' dialog you can simply change
-         the 'Code / Const' area of a module to a memory space in physical RAM.
-         Available memory areas are declared in the 'Target' tab of the 
-         Options for Target' dialog.
-
-    *** ICCARM Compiler ***
-    -----------------------
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
-    *** GNU Compiler ***
-    --------------------
-    [..] RAM functions are defined using a specific toolchain attribute
-         "__attribute__((section(".RamFunc")))".
-
-@endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
-  * @{
-  */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
-  * @brief FLASH functions executed from RAM
-  * @{
-  */ 
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
- * @{
- */
-
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
- 
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
- *
-@verbatim  
- ===============================================================================
-                      ##### ramfunc functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions that should be executed from RAM 
-    transfers.
-
-@endverbatim
-  * @{
-  */ 
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 
-  * @{
-  */  
-
-/**
-  * @brief  Enable  the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
-{
-  /* Enable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_ENABLE();
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
-{
-  /* Disable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_DISABLE();
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions 
- *
-@verbatim  
-@endverbatim
-  * @{
-  */
-
-#if defined(FLASH_PECR_PARALLBANK)
-/**
-  * @brief  Erases a specified 2 pages in program memory in parallel.
-  * @note   This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5  devices.
-  *         To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
-  *        (recommended to protect the FLASH memory against possible unwanted operation).
-  * @param  Page_Address1: The page address in program memory to be erased in 
-  *         the first Bank (BANK1). This parameter should be between FLASH_BASE
-  *         and FLASH_BANK1_END.
-  * @param  Page_Address2: The page address in program memory to be erased in 
-  *         the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
-  *         and FLASH_BANK2_END.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Proceed to erase the page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-    SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-  
-    /* Write 00000000h to the first word of the first program page to erase */
-    *(__IO uint32_t *)Page_Address1 = 0x00000000U;
-    /* Write 00000000h to the first word of the second program page to erase */    
-    *(__IO uint32_t *)Page_Address2 = 0x00000000U;
- 
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
-    /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-  }     
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Program 2 half pages in program memory in parallel (half page size is 32 Words).
-  * @note   This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5  devices.
-  * @param  Address1: specifies the first address to be written in the first bank 
-  *        (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer1: pointer to the buffer  containing the data to be  written 
-  *         to the first half page in the first bank.
-  * @param  Address2: specifies the second address to be written in the second bank
-  *        (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer2: pointer to the buffer containing the data to be  written 
-  *         to the second half page in the second bank.
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  * @note   Half page write is possible only from SRAM.
-  * @note   If there are more than 32 words to write, after 32 words another 
-  *         Half Page programming operation starts and has to be finished.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 128 
-  *         bytes) and the 31 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
-{
-  uint32_t primask_bit;
-  uint32_t count = 0U; 
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Disable all IRQs */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-    
-    /* Proceed to program the new half page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-    SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-    /* Write the first half page directly with 32 different words */
-    while(count < 32U)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
-      pBuffer1++;
-      count ++;  
-    }
-    
-    /* Write the second half page directly with 32 different words */
-    count = 0U;
-    while(count < 32U)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
-      pBuffer2++;
-      count ++;  
-    }
-    
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    
-    /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
-
-    /* Enable IRQs */
-    __set_PRIMASK(primask_bit);    
-  }
-
-  /* Return the Write Status */
-  return status;
-}
-#endif /* FLASH_PECR_PARALLBANK */
-
-/**
-  * @brief  Program a half page in program memory.
-  * @param  Address specifies the address to be written.
-  * @param  pBuffer pointer to the buffer  containing the data to be  written to 
-  *         the half page.
-  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @note   Half page write is possible only from SRAM.
-  * @note   If there are more than 32 words to write, after 32 words another 
-  *         Half Page programming operation starts and has to be finished.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 128 
-  *         bytes) and the 31 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
-{
-  uint32_t primask_bit;
-  uint32_t count = 0U; 
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Disable all IRQs */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* Proceed to program the new half page */
-    SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    
-    /* Write one half page directly with 32 different words */
-    while(count < 32U)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
-      pBuffer++;
-      count ++;  
-    }
-
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
- 
-    /* If the write operation is completed, disable the PROG and FPRG bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-
-    /* Enable IRQs */
-    __set_PRIMASK(primask_bit);
-  }
-   
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions 
- *  @brief    Peripheral errors functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time errors of  the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH errors flag.
-  * @param  Error pointer is the error value. It can be a mixed of:
-@if STM32L100xB
-@elif STM32L100xBA
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-@elif STM32L151xB
-@elif STM32L151xBA
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-@elif STM32L152xB
-@elif STM32L152xBA
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-@elif STM32L100xC
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-  *            @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
-@elif STM32L151xC
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-  *            @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
-@elif STM32L152xC
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-  *            @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
-@elif STM32L162xC
-  *            @arg @ref HAL_FLASH_ERROR_RD      FLASH Read Protection error flag (PCROP)
-  *            @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
-@else
-  *            @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
-@endif
-  *            @arg @ref HAL_FLASH_ERROR_PGA     FLASH Programming Alignment error flag
-  *            @arg @ref HAL_FLASH_ERROR_WRP     FLASH Write protected error flag
-  *            @arg @ref HAL_FLASH_ERROR_OPTV    FLASH Option valid error flag 
-  * @retval HAL Status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
-{ 
-  *Error = pFlash.ErrorCode;
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions
-  *
-  * @{
-  */
-
-/**
-  * @brief  Erase a double word in data memory.
-  * @param  Address specifies the address to be erased.
-  * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   Data memory double word erase is possible only from SRAM.
-  * @note   A double word is erased to the data memory only if the first address 
-  *         to load is the start address of a double word (multiple of 8 bytes).
-  * @note   During the Data memory double word erase, all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @retval HAL status
-  */
-
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
-{
-  uint32_t primask_bit;
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Disable all IRQs */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* If the previous operation is completed, proceed to erase the next double word */
-    /* Set the ERASE bit */
-    SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-    /* Set DATA bit */
-    SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
-   
-    /* Write 00000000h to the 2 words to erase */
-    *(__IO uint32_t *)Address = 0x00000000U;
-    Address += 4U;
-    *(__IO uint32_t *)Address = 0x00000000U;
-   
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    
-    /* If the erase operation is completed, disable the ERASE and DATA bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
-
-    /* Enable IRQs */
-    __set_PRIMASK(primask_bit);
- 
-  }  
-      
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Write a double word in data memory without erase.
-  * @param  Address specifies the address to be written.
-  * @param  Data specifies the data to be written.
-  * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   Data memory double word write is possible only from SRAM.
-  * @note   A data memory double word is written to the data memory only if the 
-  *         first address to load is the start address of a double word (multiple 
-  *         of double word).
-  * @note   During the Data memory double word write, all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @retval HAL status
-  */ 
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
-  uint32_t primask_bit;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Disable all IRQs */
-    primask_bit = __get_PRIMASK();
-    __disable_irq();
-
-    /* If the previous operation is completed, proceed to program the new data*/
-    SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
-    
-    /* Write the 2 words */  
-     *(__IO uint32_t *)Address = (uint32_t) Data;
-     Address += 4U;
-     *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
-     
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    
-    /* If the write operation is completed, disable the FPRG and DATA bits */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);     
-
-    /* Enable IRQs */
-    __set_PRIMASK(primask_bit);
-  }
-      
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_RAMFUNC_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval HAL Status
-  */
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
-{
-  uint32_t flags = 0U;
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-    flags |= FLASH_FLAG_WRPERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-    flags |= FLASH_FLAG_PGAERR;
-  }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
-    flags |= FLASH_FLAG_OPTVERR;
-  }
-
-#if defined(FLASH_SR_RDERR)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    flags |= FLASH_FLAG_RDERR;
-  }
-#endif /* FLASH_SR_RDERR */
-#if defined(FLASH_SR_OPTVERRUSR)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
-    flags |= FLASH_FLAG_OPTVERRUSR;
-  }
-#endif /* FLASH_SR_OPTVERRUSR */
-
-  /* Clear FLASH error pending bits */
-  __HAL_FLASH_CLEAR_FLAG(flags);
-
-  return HAL_OK;
-}  
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout maximum flash operationtimeout
-  * @retval HAL status
-  */
-static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
-{ 
-    /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-       Even if the FLASH operation fails, the BUSY flag will be reset and an error
-       flag will be set */
-       
-    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) 
-    { 
-      Timeout--;
-    }
-    
-    if(Timeout == 0x00U)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
-#if defined(FLASH_SR_RDERR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || 
-#endif /* FLASH_SR_RDERR */
-#if defined(FLASH_SR_OPTVERRUSR)
-      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || 
-#endif /* FLASH_SR_OPTVERRUSR */
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
-  {
-    /*Save the error code*/
-    FLASHRAM_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* There is no error flag set */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-     
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c
deleted file mode 100644
index ae06f5f2356..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c
+++ /dev/null
@@ -1,547 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..]
-  Each port bit of the general-purpose I/O (GPIO) ports can be individually
-  configured by software in several modes:
-  (+) Input mode
-  (+) Analog mode
-  (+) Output mode
-  (+) Alternate function mode
-  (+) External interrupt/event lines
-
-  [..]
-  During and just after reset, the alternate functions and external interrupt
-  lines are not active and the I/O ports are configured in input floating mode.
-
-  [..]
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
-  activated or not.
-
-  [..]
-  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-
-  [..]
-  The microcontroller IO pins are connected to onboard peripherals/modules through a
-  multiplexer that allows only one peripheral s alternate function (AF) connected
-  to an IO pin at a time. In this way, there can be no conflict between peripherals
-  sharing the same IO pin.
-
-  [..]
-  All ports have external interrupt/event capability. To use external interrupt
-  lines, the port must be configured in input mode. All available GPIO pins are
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
-  [..]
-  The external interrupt/event controller consists of up to 28 edge detectors
-  (depending on products 16 lines are connected to GPIO) for generating event/interrupt
-  requests (each input line can be independently configured to select the type
-  (interrupt or event) and the corresponding trigger event (rising or falling or both).
-  Each line can also be masked independently.
-
-            ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
-
-   (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-       (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-       (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
-            structure.
-       (++) In case of Output or alternate function mode selection: the speed is
-            configured through "Speed" member from GPIO_InitTypeDef structure,
-            the speed is configurable: Low, Medium and High.
-       (++) If alternate mode is selected, the alternate function connected to the IO
-            is configured through "Alternate" member from GPIO_InitTypeDef structure
-       (++) Analog mode is required when a pin is to be used as ADC channel
-            or DAC output.
-       (++) In case of external interrupt/event selection the "Mode" member from
-            GPIO_InitTypeDef structure select the type (interrupt or event) and
-            the corresponding trigger event (rising or falling or both).
-
-   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
-       mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-       HAL_NVIC_EnableIRQ().
-
-   (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
-       recommended to use it to unconfigure pin which was used as an external interrupt
-       or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
-       registers.
-
-   (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
-   (#) To set/reset the level of a pin configured in output mode use
-       HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
-   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-   (#) During and just after reset, the alternate functions are not
-       active and the GPIO pins are configured in input floating mode (except JTAG
-       pins).
-
-   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
-       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
-       priority over the GPIO function.
-
-   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
-       general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
-       The HSE has priority over the GPIO function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants
-  * @{
-  */
-#define GPIO_NUMBER           (16U)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t temp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
-  /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != 0)
-  {
-    /* Get current io position */
-    iocurrent = (GPIO_Init->Pin) & (1U << position);
-
-    if (iocurrent)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Output or Alternate function mode selection */
-      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
-          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
-        CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-        SET_BIT(temp, GPIO_Init->Speed << (position * 2));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
-        SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
-      {
-        /* Check the Pull parameter */
-        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
-        /* Activate the Pull-up or Pull down resistor for the current IO */
-        temp = GPIOx->PUPDR;
-        CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
-        SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
-        GPIOx->PUPDR = temp;
-      }
-
-      /* In case of Alternate function mode selection */
-      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
-      {
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
-        /* Configure Alternate function mapped with the current IO */
-        /* Identify AFRL or AFRH register based on IO position*/
-        temp = GPIOx->AFR[position >> 3];
-        CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
-        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
-        GPIOx->AFR[position >> 3] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
-      SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
-      GPIOx->MODER = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2];
-        CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
-        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
-        SYSCFG->EXTICR[position >> 2] = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
-        {
-          SET_BIT(temp, iocurrent);
-        }
-        EXTI->IMR = temp;
-
-        temp = EXTI->EMR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
-        {
-          SET_BIT(temp, iocurrent);
-        }
-        EXTI->EMR = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
-        {
-          SET_BIT(temp, iocurrent);
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);
-        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
-        {
-          SET_BIT(temp, iocurrent);
-        }
-        EXTI->FTSR = temp;
-      }
-    }
-
-    position++;
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t tmp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Configure the port pins */
-  while ((GPIO_Pin >> position) != 0)
-  {
-    /* Get current io position */
-    iocurrent = (GPIO_Pin) & (1U << position);
-
-    if (iocurrent)
-    {
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      /* Clear the External Interrupt or Event for the current IO */
-
-      tmp = SYSCFG->EXTICR[position >> 2];
-      tmp &= ((0x0FU) << (4 * (position & 0x03)));
-      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
-      {
-        /* Clear EXTI line configuration */
-        CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
-        CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
-
-        /* Clear Rising Falling edge configuration */
-        CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
-        CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
-
-        tmp = (0x0FU) << (4 * (position & 0x03));
-        CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
-      }
-
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floting Mode */
-      CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
-
-      /* Configure the default Alternate Function in current IO */
-      CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
-      /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
-      CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
-
-      /* Configure the default value IO Output Type */
-      CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
-
-      /* Configure the default value for IO Speed */
-      CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-    }
-
-    position++;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
- *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  * @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState specifies the value to be written to the selected bit.
-  *          This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if (PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pin
-  * @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  uint32_t odr;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* get current Ouput Data Register value */
-  odr = GPIOx->ODR;
-
-  /* Set selected pins that were at low level, and reset ones that were high */
-  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
-* @brief  Locks GPIO Pins configuration registers.
-* @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-*         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-* @note   The configuration of the locked GPIO pins can no longer be modified
-*         until the next reset.
-* @note   Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8
-*         depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i].
-*         GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8].
-*         It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also
-*         GPIOx_OTYPER[i-8].
-*         Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15,
-*         you must call also HAL_GPIO_LockPin with GPIO_Pin - 8.
-*         (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding
-*         GPIO_PIN_0 to GPIO_PIN_7).
-* @param  GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-* @param  GPIO_Pin Specifies the port bit to be locked.
-*         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-* @retval None
-*/
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  SET_BIT(tmp, GPIO_Pin);
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  tmp = GPIOx->LCKR;
-
-  /* Read again in order to confirm lock is active */
-  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c
deleted file mode 100644
index 5d25efd0bfd..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2c.c
+++ /dev/null
@@ -1,7498 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State, Mode and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx channel
-            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
-                  the DMA Tx or Rx channel
-
-    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
-        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
-        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.
-
-    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-
-    *** Interrupt mode or DMA mode IO sequential operation ***
-    ==========================================================
-    [..]
-      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
-          when a direction change during transfer
-    [..]
-      (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
-      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition
-      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
-                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
-                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
-      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and without a final stop condition in both cases
-      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
-                            if no direction change and with a final stop condition in both cases
-      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
-                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
-                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
-                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
-                              without stopping the communication and so generate a restart condition.
-      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
-                            interface.
-                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
-                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
-
-      (+) Different sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
-            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
-            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
-            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
-            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-          @ref HAL_I2C_Mem_Write_IT()
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-          @ref HAL_I2C_Mem_Read_IT()
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-          @ref HAL_I2C_Mem_Write_DMA()
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
-      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-          @ref HAL_I2C_Mem_Read_DMA()
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) @ref __HAL_I2C_ENABLE:     Enable the I2C peripheral
-      (+) @ref __HAL_I2C_DISABLE:    Disable the I2C peripheral
-      (+) @ref __HAL_I2C_GET_FLAG:   Checks whether the specified I2C flag is set or not
-      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
-      (+) @ref __HAL_I2C_ENABLE_IT:  Enable the specified I2C interrupt
-      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     *** Callback registration ***
-     =============================================
-    [..]
-     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
-     to register an interrupt callback.
-    [..]
-     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
-       (+) ErrorCallback        : callback for error detection.
-       (+) AbortCpltCallback    : callback for abort completion process.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
-    [..]
-     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
-     weak function.
-     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
-       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
-       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
-       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
-       (+) ListenCpltCallback   : callback for end of listen mode.
-       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
-       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
-       (+) ErrorCallback        : callback for error detection.
-       (+) AbortCpltCallback    : callback for abort completion process.
-       (+) MspInitCallback      : callback for Msp Init.
-       (+) MspDeInitCallback    : callback for Msp DeInit.
-    [..]
-     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
-    [..]
-     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
-     these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-    [..]
-     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
-     or @ref HAL_I2C_Init() function.
-    [..]
-     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
-
-
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup I2C_Private_Define
-  * @{
-  */
-#define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */
-#define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */
-#define I2C_TIMEOUT_STOP_FLAG     5U          /*!< Timeout 5 ms              */
-#define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-static void I2C_ITError(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-
-/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
-
-/* Private functions for I2C transfer IRQ handler */
-static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
-static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
-static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
-
-static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
-static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-
-static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
-
-/* Private function to Convert Specific options */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Communication Speed
-        (++) Duty cycle
-        (++) Addressing mode
-        (++) Own Address 1
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and initialize the associated handle.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t freqrange;
-  uint32_t pclk1;
-
-  /* Check the I2C handle allocation */
-  if (hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
-  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if (hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2c->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    /* Init the I2C Callback settings */
-    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
-    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
-    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
-    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
-    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
-    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
-    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
-    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
-
-    if (hi2c->MspInitCallback == NULL)
-    {
-      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    hi2c->MspInitCallback(hi2c);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_I2C_MspInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /*Reset I2C*/
-  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
-  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
-
-  /* Get PCLK1 frequency */
-  pclk1 = HAL_RCC_GetPCLK1Freq();
-
-  /* Check the minimum allowed PCLK1 frequency */
-  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Calculate frequency range */
-  freqrange = I2C_FREQRANGE(pclk1);
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Frequency range */
-  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
-
-  /*---------------------------- I2Cx TRISE Configuration --------------------*/
-  /* Configure I2Cx: Rise Time */
-  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
-
-  /*---------------------------- I2Cx CCR Configuration ----------------------*/
-  /* Configure I2Cx: Speed */
-  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Configure I2Cx: Own Address1 and addressing mode */
-  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode = HAL_I2C_MODE_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the I2C peripheral.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if (hi2c == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  if (hi2c->MspDeInitCallback == NULL)
-  {
-    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  hi2c->MspDeInitCallback(hi2c);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
-  hi2c->State         = HAL_I2C_STATE_RESET;
-  hi2c->PreviousState = I2C_STATE_NONE;
-  hi2c->Mode          = HAL_I2C_MODE_NONE;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the I2C MSP.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User I2C Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
-        hi2c->MasterTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
-        hi2c->MasterRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
-        hi2c->SlaveTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
-        hi2c->SlaveRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
-        hi2c->ListenCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
-        hi2c->MemTxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
-        hi2c->MemRxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_ERROR_CB_ID :
-        hi2c->ErrorCallback = pCallback;
-        break;
-
-      case HAL_I2C_ABORT_CB_ID :
-        hi2c->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2C_STATE_RESET == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  Unregister an I2C Callback
-  *         I2C callback is redirected to the weak predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
-  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
-  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
-  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
-  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
-        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
-        break;
-
-      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
-        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
-        break;
-
-      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
-        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
-        break;
-
-      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
-        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
-        break;
-
-      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
-        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
-        break;
-
-      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
-        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
-        break;
-
-      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
-        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
-        break;
-
-      case HAL_I2C_ERROR_CB_ID :
-        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_I2C_ABORT_CB_ID :
-        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
-        break;
-
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2C_STATE_RESET == hi2c->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2C_MSPINIT_CB_ID :
-        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2C_MSPDEINIT_CB_ID :
-        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  Register the Slave Address Match I2C Callback
-  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pCallback pointer to the Address Match Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    hi2c->AddrCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-/**
-  * @brief  UnRegister the Slave Address Match I2C Callback
-  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
-  if (HAL_I2C_STATE_READY == hi2c->State)
-  {
-    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-  return status;
-}
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-        (++) HAL_I2C_Master_Seq_Transmit_IT()
-        (++) HAL_I2C_Master_Seq_Receive_IT()
-        (++) HAL_I2C_Slave_Seq_Transmit_IT()
-        (++) HAL_I2C_Slave_Seq_Receive_IT()
-        (++) HAL_I2C_EnableListen_IT()
-        (++) HAL_I2C_DisableListen_IT()
-        (++) HAL_I2C_Master_Abort_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-        (++) HAL_I2C_Master_Seq_Transmit_DMA()
-        (++) HAL_I2C_Master_Seq_Receive_DMA()
-        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
-        (++) HAL_I2C_Slave_Seq_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_AddrCallback()
-        (++) HAL_I2C_ListenCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-        (++) HAL_I2C_AbortCpltCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Send Slave Address */
-    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while (hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-        }
-        return HAL_ERROR;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferCount--;
-        hi2c->XferSize--;
-      }
-
-      /* Wait until BTF flag is set */
-      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-        }
-        return HAL_ERROR;
-      }
-    }
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Send Slave Address */
-    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    if (hi2c->XferSize == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else if (hi2c->XferSize == 1U)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else if (hi2c->XferSize == 2U)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while (hi2c->XferSize > 0U)
-    {
-      if (hi2c->XferSize <= 3U)
-      {
-        /* One byte */
-        if (hi2c->XferSize == 1U)
-        {
-          /* Wait until RXNE flag is set */
-          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* Two bytes */
-        else if (hi2c->XferSize == 2U)
-        {
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Read data from DR */
-        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-
-        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* If 10bit addressing mode is selected */
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while (hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        return HAL_ERROR;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-      hi2c->XferSize--;
-
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferCount--;
-        hi2c->XferSize--;
-      }
-    }
-
-    /* Wait until AF flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Address Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == (uint16_t)0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while (hi2c->XferSize > 0U)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        /* Disable Address Acknowledge */
-        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        return HAL_ERROR;
-      }
-
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
-      {
-        /* Read data from DR */
-        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-      }
-    }
-
-    /* Wait until STOP flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      return HAL_ERROR;
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-    /* Disable Address Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Enable Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmatx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;
-        hi2c->hdmatx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-
-        /* Enable EVT and ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-        /* Enable DMA Request */
-        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        /* Generate Start */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmarx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;
-        hi2c->hdmarx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        /* Generate Start */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-
-        /* Enable EVT and ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-        /* Enable DMA Request */
-        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    if (hi2c->hdmatx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    if (hi2c->hdmarx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    while (hi2c->XferSize > 0U)
-    {
-      /* Wait until TXE flag is set */
-      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-      {
-        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-        {
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-        }
-        return HAL_ERROR;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferSize--;
-      hi2c->XferCount--;
-
-      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-      }
-    }
-
-    /* Wait until BTF flag is set */
-    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-      }
-      return HAL_ERROR;
-    }
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    if (hi2c->XferSize == 0U)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else if (hi2c->XferSize == 1U)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else if (hi2c->XferSize == 2U)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while (hi2c->XferSize > 0U)
-    {
-      if (hi2c->XferSize <= 3U)
-      {
-        /* One byte */
-        if (hi2c->XferSize == 1U)
-        {
-          /* Wait until RXNE flag is set */
-          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* Two bytes */
-        else if (hi2c->XferSize == 2U)
-        {
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Wait until BTF flag is set */
-          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        /* Read data from DR */
-        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferSize--;
-        hi2c->XferCount--;
-
-        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-
-          /* Update counter */
-          hi2c->XferSize--;
-          hi2c->XferCount--;
-        }
-      }
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-    hi2c->Memaddress  = MemAddress;
-    hi2c->MemaddSize  = MemAddSize;
-    hi2c->EventCount  = 0U;
-
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->Devaddress  = DevAddress;
-    hi2c->Memaddress  = MemAddress;
-    hi2c->MemaddSize  = MemAddSize;
-    hi2c->EventCount  = 0U;
-
-    /* Enable Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    if (hi2c->XferSize > 0U)
-    {
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  __IO uint32_t count = 0U;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmatx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;
-        hi2c->hdmatx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address and Memory Address */
-        if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-        {
-          /* Abort the ongoing DMA */
-          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
-
-          /* Prevent unused argument(s) compilation and MISRA warning */
-          UNUSED(dmaxferstatus);
-
-          /* Set the unused I2C DMA transfer complete callback to NULL */
-          hi2c->hdmatx->XferCpltCallback = NULL;
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          hi2c->XferSize = 0U;
-          hi2c->XferCount = 0U;
-
-          /* Disable I2C peripheral to prevent dummy data in buffer */
-          __HAL_I2C_DISABLE(hi2c);
-
-          return HAL_ERROR;
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-        /* Enable ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
-        /* Enable DMA Request */
-        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  /* Init tickstart for timeout management*/
-  uint32_t tickstart = HAL_GetTick();
-  __IO uint32_t count = 0U;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-    do
-    {
-      count--;
-      if (count == 0U)
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MEM;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmarx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;
-        hi2c->hdmarx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Send Slave Address and Memory Address */
-        if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-        {
-          /* Abort the ongoing DMA */
-          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
-
-          /* Prevent unused argument(s) compilation and MISRA warning */
-          UNUSED(dmaxferstatus);
-
-          /* Set the unused I2C DMA transfer complete callback to NULL */
-          hi2c->hdmarx->XferCpltCallback = NULL;
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          hi2c->XferSize = 0U;
-          hi2c->XferCount = 0U;
-
-          /* Disable I2C peripheral to prevent dummy data in buffer */
-          __HAL_I2C_DISABLE(hi2c);
-
-          return HAL_ERROR;
-        }
-
-        if (hi2c->XferSize == 1U)
-        {
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-        }
-        else
-        {
-          /* Enable Last DMA bit */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-        /* Enable ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
-        /* Enable DMA Request */
-        hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Send Slave Address and Memory Address */
-      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  Trials Number of trials
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
-  /* Get tick */
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t I2C_Trials = 1U;
-  FlagStatus tmp1;
-  FlagStatus tmp2;
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Wait until BUSY flag is reset */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    do
-    {
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-      /* Wait until SB flag is set */
-      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
-      {
-        if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-        {
-          hi2c->ErrorCode = HAL_I2C_WRONG_START;
-        }
-        return HAL_TIMEOUT;
-      }
-
-      /* Send slave address */
-      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-      /* Wait until ADDR or AF flag are set */
-      /* Get tick */
-      tickstart = HAL_GetTick();
-
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          hi2c->State = HAL_I2C_STATE_TIMEOUT;
-        }
-        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-      }
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Check if the ADDR flag has been set */
-      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-        /* Clear ADDR Flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Wait until BUSY flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-        /* Clear AF Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Wait until BUSY flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
-      }
-
-      /* Increment Trials */
-      I2C_Trials++;
-    }
-    while (I2C_Trials < Trials);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t Prev_State = 0x00U;
-  __IO uint32_t count      = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-      do
-      {
-        count--;
-        if (count == 0U)
-        {
-          hi2c->PreviousState       = I2C_STATE_NONE;
-          hi2c->State               = HAL_I2C_STATE_READY;
-          hi2c->Mode                = HAL_I2C_MODE_NONE;
-          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_ERROR;
-        }
-      }
-      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->Devaddress  = DevAddress;
-
-    Prev_State = hi2c->PreviousState;
-
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-    {
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t Prev_State = 0x00U;
-  __IO uint32_t count      = 0x00U;
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-      do
-      {
-        count--;
-        if (count == 0U)
-        {
-          hi2c->PreviousState       = I2C_STATE_NONE;
-          hi2c->State               = HAL_I2C_STATE_READY;
-          hi2c->Mode                = HAL_I2C_MODE_NONE;
-          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_ERROR;
-        }
-      }
-      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->Devaddress  = DevAddress;
-
-    Prev_State = hi2c->PreviousState;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if (hi2c->hdmatx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmatx->XferHalfCpltCallback = NULL;
-        hi2c->hdmatx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-        /* Mean Previous state is same as current state */
-        if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-        {
-          /* Generate Start */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-        }
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-
-        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
-        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
-        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
-        {
-          /* Enable DMA Request */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-        }
-
-        /* Enable EVT and ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-      if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-      {
-        /* Generate Start */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-      }
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable EVT, BUF and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t Prev_State = 0x00U;
-  __IO uint32_t count = 0U;
-  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-      do
-      {
-        count--;
-        if (count == 0U)
-        {
-          hi2c->PreviousState       = I2C_STATE_NONE;
-          hi2c->State               = HAL_I2C_STATE_READY;
-          hi2c->Mode                = HAL_I2C_MODE_NONE;
-          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_ERROR;
-        }
-      }
-      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->Devaddress  = DevAddress;
-
-    Prev_State = hi2c->PreviousState;
-
-    if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
-    {
-      if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
-      {
-        /* Disable Acknowledge */
-        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        /* Enable Pos */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-        /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
-        enableIT &= ~I2C_IT_BUF;
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-      }
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-    /* Mean Previous state is same as current state */
-    if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-    {
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-    to avoid the risk of I2C interrupt handle execution before current
-    process unlock */
-
-    /* Enable interrupts */
-    __HAL_I2C_ENABLE_IT(hi2c, enableIT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  __IO uint32_t Prev_State = 0x00U;
-  __IO uint32_t count = 0U;
-  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    /* Check Busy Flag only if FIRST call of Master interface */
-    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
-    {
-      /* Wait until BUSY flag is reset */
-      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
-      do
-      {
-        count--;
-        if (count == 0U)
-        {
-          hi2c->PreviousState       = I2C_STATE_NONE;
-          hi2c->State               = HAL_I2C_STATE_READY;
-          hi2c->Mode                = HAL_I2C_MODE_NONE;
-          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_ERROR;
-        }
-      }
-      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    /* Clear Last DMA bit */
-    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
-    hi2c->Mode      = HAL_I2C_MODE_MASTER;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-    hi2c->Devaddress  = DevAddress;
-
-    Prev_State = hi2c->PreviousState;
-
-    if (hi2c->XferSize > 0U)
-    {
-      if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
-      {
-        if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
-        {
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Enable Pos */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-          /* Enable Last DMA bit */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-        }
-        else
-        {
-          /* Enable Acknowledge */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-        }
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
-        {
-          /* Enable Last DMA bit */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-        }
-      }
-      if (hi2c->hdmarx != NULL)
-      {
-        /* Set the I2C DMA transfer complete callback */
-        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-        /* Set the DMA error callback */
-        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-        /* Set the unused DMA callbacks to NULL */
-        hi2c->hdmarx->XferHalfCpltCallback = NULL;
-        hi2c->hdmarx->XferAbortCallback = NULL;
-
-        /* Enable the DMA channel */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-      if (dmaxferstatus == HAL_OK)
-      {
-        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-        /* Mean Previous state is same as current state */
-        if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-        {
-          /* Generate Start */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-          /* Update interrupt for only EVT and ERR */
-          enableIT = (I2C_IT_EVT | I2C_IT_ERR);
-        }
-        else
-        {
-          /* Update interrupt for only ERR */
-          enableIT = I2C_IT_ERR;
-        }
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        /* Note : The I2C interrupts must be enabled after unlocking current process
-        to avoid the risk of I2C interrupt handle execution before current
-        process unlock */
-
-        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
-        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
-        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
-        {
-          /* Enable DMA Request */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-        }
-
-        /* Enable EVT and ERR interrupt */
-        __HAL_I2C_ENABLE_IT(hi2c, enableIT);
-      }
-      else
-      {
-        /* Update I2C state */
-        hi2c->State     = HAL_I2C_STATE_READY;
-        hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-        /* Update I2C error code */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
-      /* Mean Previous state is same as current state */
-      if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
-      {
-        /* Generate Start */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-      }
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-
-      /* Enable interrupts */
-      __HAL_I2C_ENABLE_IT(hi2c, enableIT);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave RX state to TX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-      {
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmarx != NULL)
-        {
-          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA RX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-          }
-        }
-      }
-    }
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-      {
-        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmatx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA TX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-
-    if (hi2c->hdmatx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with DMA
-  * @note   This interface allow to manage repeated start condition when a direction change during transfer
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  pData Pointer to data buffer
-  * @param  Size Amount of data to be sent
-  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
-  HAL_StatusTypeDef dmaxferstatus;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
-    /* and then toggle the HAL slave RX state to TX state */
-    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-      {
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmarx != NULL)
-        {
-          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA RX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-          }
-        }
-      }
-    }
-    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-      {
-        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-        /* Abort DMA Xfer if any */
-        if (hi2c->hdmatx != NULL)
-        {
-          /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-          /* Abort DMA TX */
-          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-          {
-            /* Call Directly XferAbortCallback function in case of error */
-            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
-    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Prepare transfer parameters */
-    hi2c->pBuffPtr    = pData;
-    hi2c->XferCount   = Size;
-    hi2c->XferSize    = hi2c->XferCount;
-    hi2c->XferOptions = XferOptions;
-
-    if (hi2c->hdmarx != NULL)
-    {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
-      /* Set the DMA error callback */
-      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmarx->XferHalfCpltCallback = NULL;
-      hi2c->hdmarx->XferAbortCallback = NULL;
-
-      /* Enable the DMA channel */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
-    {
-      /* Enable Address Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      /* Enable DMA Request */
-      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-      /* Note : The I2C interrupts must be enabled after unlocking current process
-      to avoid the risk of I2C interrupt handle execution before current
-      process unlock */
-      /* Enable EVT and ERR interrupt */
-      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_READY;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Enable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->State == HAL_I2C_STATE_READY)
-  {
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-
-    /* Check if the I2C is already enabled */
-    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
-    {
-      /* Enable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-    }
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Enable EVT and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Disable the Address listen mode with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of tmp to prevent undefined behavior of volatile usage */
-  uint32_t tmp;
-
-  /* Disable Address listen mode only if a transfer is not ongoing */
-  if (hi2c->State == HAL_I2C_STATE_LISTEN)
-  {
-    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
-    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->Mode = HAL_I2C_MODE_NONE;
-
-    /* Disable Address Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for the specified I2C.
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(DevAddress);
-
-  /* Abort Master transfer during Receive or Transmit process    */
-  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_ABORT;
-
-    /* Disable Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-    hi2c->XferCount = 0U;
-
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Wrong usage of abort function */
-    /* This function should be used only in case of abort monitored by master device */
-    /* Or periphal is not in busy state, mean there is no active sequence to be abort */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t sr1itflags;
-  uint32_t sr2itflags               = 0U;
-  uint32_t itsources                = READ_REG(hi2c->Instance->CR2);
-  uint32_t CurrentXferOptions       = hi2c->XferOptions;
-  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  /* Master or Memory mode selected */
-  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
-  {
-    sr2itflags   = READ_REG(hi2c->Instance->SR2);
-    sr1itflags   = READ_REG(hi2c->Instance->SR1);
-
-    /* Exit IRQ event until Start Bit detected in case of Other frame requested */
-    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
-    {
-      return;
-    }
-
-    /* SB Set ----------------------------------------------------------------*/
-    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-    {
-      /* Convert OTHER_xxx XferOptions if any */
-      I2C_ConvertOtherXferOptions(hi2c);
-
-      I2C_Master_SB(hi2c);
-    }
-    /* ADD10 Set -------------------------------------------------------------*/
-    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-    {
-      I2C_Master_ADD10(hi2c);
-    }
-    /* ADDR Set --------------------------------------------------------------*/
-    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-    {
-      I2C_Master_ADDR(hi2c);
-    }
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
-    {
-      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
-      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
-      {
-        /* TXE set and BTF reset -----------------------------------------------*/
-        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
-        {
-          I2C_MasterTransmit_TXE(hi2c);
-        }
-        /* BTF set -------------------------------------------------------------*/
-        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-        {
-          if (CurrentState == HAL_I2C_STATE_BUSY_TX)
-          {
-            I2C_MasterTransmit_BTF(hi2c);
-          }
-          else /* HAL_I2C_MODE_MEM */
-          {
-            if (CurrentMode == HAL_I2C_MODE_MEM)
-            {
-              I2C_MemoryTransmit_TXE_BTF(hi2c);
-            }
-          }
-        }
-        else
-        {
-          /* Do nothing */
-        }
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
-      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
-      {
-        /* RXNE set and BTF reset -----------------------------------------------*/
-        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
-        {
-          I2C_MasterReceive_RXNE(hi2c);
-        }
-        /* BTF set -------------------------------------------------------------*/
-        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-        {
-          I2C_MasterReceive_BTF(hi2c);
-        }
-        else
-        {
-          /* Do nothing */
-        }
-      }
-    }
-  }
-  /* Slave mode selected */
-  else
-  {
-    /* If an error is detected, read only SR1 register to prevent */
-    /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
-    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-      sr1itflags   = READ_REG(hi2c->Instance->SR1);
-    }
-    else
-    {
-      sr2itflags   = READ_REG(hi2c->Instance->SR2);
-      sr1itflags   = READ_REG(hi2c->Instance->SR1);
-    }
-
-    /* ADDR set --------------------------------------------------------------*/
-    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-    {
-      /* Now time to read SR2, this will clear ADDR flag automatically */
-      if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-      {
-        sr2itflags   = READ_REG(hi2c->Instance->SR2);
-      }
-      I2C_Slave_ADDR(hi2c, sr2itflags);
-    }
-    /* STOPF set --------------------------------------------------------------*/
-    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-    {
-      I2C_Slave_STOPF(hi2c);
-    }
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
-    {
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-      {
-        I2C_SlaveTransmit_BTF(hi2c);
-      }
-      else
-      {
-        /* Do nothing */
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* RXNE set and BTF reset ----------------------------------------------*/
-      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
-      {
-        I2C_SlaveReceive_BTF(hi2c);
-      }
-      else
-      {
-        /* Do nothing */
-      }
-    }
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  HAL_I2C_ModeTypeDef tmp1;
-  uint32_t tmp2;
-  HAL_I2C_StateTypeDef tmp3;
-  uint32_t tmp4;
-  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
-  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
-  uint32_t error      = HAL_I2C_ERROR_NONE;
-  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
-
-  /* I2C Bus error interrupt occurred ----------------------------------------*/
-  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
-  {
-    error |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
-  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
-  {
-    error |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
-  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
-  {
-    tmp1 = CurrentMode;
-    tmp2 = hi2c->XferCount;
-    tmp3 = hi2c->State;
-    tmp4 = hi2c->PreviousState;
-    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
-        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
-         ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
-    {
-      I2C_Slave_AF(hi2c);
-    }
-    else
-    {
-      /* Clear AF flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      error |= HAL_I2C_ERROR_AF;
-
-      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
-      if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-      }
-    }
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
-  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
-  {
-    error |= HAL_I2C_ERROR_OVR;
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  /* Call the Error Callback in case of Error detected -----------------------*/
-  if (error != HAL_I2C_ERROR_NONE)
-  {
-    hi2c->ErrorCode |= error;
-    I2C_ITError(hi2c);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Address Match callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
-  * @param  AddrMatchCode Address Match Code
-  * @retval None
-  */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-  UNUSED(TransferDirection);
-  UNUSED(AddrMatchCode);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AddrCallback() could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Listen Complete callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C abort callback.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval None
-  */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2c);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_AbortCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- *  @brief   Peripheral State, Mode and Error functions
-  *
-@verbatim
- ===============================================================================
-            ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2C handle state.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  /* Return I2C handle state */
-  return hi2c->State;
-}
-
-/**
-  * @brief  Returns the I2C Master, Slave, Memory or no mode.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL mode
-  */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->Mode;
-}
-
-/**
-  * @brief  Return the I2C error code.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-  * @retval I2C Error Code
-  */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Handle TXE flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
-  uint32_t CurrentXferOptions       = hi2c->XferOptions;
-
-  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
-  {
-    /* Call TxCpltCallback() directly if no stop mode is set */
-    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
-    {
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MasterTxCpltCallback(hi2c);
-#else
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else /* Generate Stop condition then Call TxCpltCallback() */
-    {
-      /* Disable EVT, BUF and ERR interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      if (hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->MemTxCpltCallback(hi2c);
-#else
-        HAL_I2C_MemTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->MasterTxCpltCallback(hi2c);
-#else
-        HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-    }
-  }
-  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
-           ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
-  {
-    if (hi2c->XferCount == 0U)
-    {
-      /* Disable BUF interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-    }
-    else
-    {
-      if (hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        I2C_MemoryTransmit_TXE_BTF(hi2c);
-      }
-      else
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferCount--;
-      }
-    }
-  }
-  else
-  {
-    /* Do nothing */
-  }
-}
-
-/**
-  * @brief  Handle BTF flag for Master transmitter
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-  {
-    if (hi2c->XferCount != 0U)
-    {
-      /* Write data to DR */
-      hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-    }
-    else
-    {
-      /* Call TxCpltCallback() directly if no stop mode is set */
-      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
-      {
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->MasterTxCpltCallback(hi2c);
-#else
-        HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-      else /* Generate Stop condition then Call TxCpltCallback() */
-      {
-        /* Disable EVT, BUF and ERR interrupt */
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        if (hi2c->Mode == HAL_I2C_MODE_MEM)
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-          hi2c->MemTxCpltCallback(hi2c);
-#else
-          HAL_I2C_MemTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-          hi2c->MasterTxCpltCallback(hi2c);
-#else
-          HAL_I2C_MasterTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Do nothing */
-  }
-}
-
-/**
-  * @brief  Handle TXE and BTF flag for Memory transmitter
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  if (hi2c->EventCount == 0U)
-  {
-    /* If Memory address size is 8Bit */
-    if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
-    {
-      /* Send Memory Address */
-      hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
-      hi2c->EventCount += 2U;
-    }
-    /* If Memory address size is 16Bit */
-    else
-    {
-      /* Send MSB of Memory Address */
-      hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
-
-      hi2c->EventCount++;
-    }
-  }
-  else if (hi2c->EventCount == 1U)
-  {
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
-    hi2c->EventCount++;
-  }
-  else if (hi2c->EventCount == 2U)
-  {
-    if (CurrentState == HAL_I2C_STATE_BUSY_RX)
-    {
-      /* Generate Restart */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
-
-      hi2c->EventCount++;
-    }
-    else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
-    {
-      /* Write data to DR */
-      hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-    }
-    else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
-    {
-      /* Generate Stop condition then Call TxCpltCallback() */
-      /* Disable EVT, BUF and ERR interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MemTxCpltCallback(hi2c);
-#else
-      HAL_I2C_MemTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Do nothing */
-    }
-  }
-  else
-  {
-    /* Do nothing */
-  }
-}
-
-/**
-  * @brief  Handle RXNE flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    uint32_t tmp;
-
-    tmp = hi2c->XferCount;
-    if (tmp > 3U)
-    {
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-
-      if (hi2c->XferCount == (uint16_t)3)
-      {
-        /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
-        on BTF subroutine */
-        /* Disable BUF interrupt */
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-      }
-    }
-    else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
-    {
-      if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
-      {
-        /* Disable Acknowledge */
-        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        /* Disable EVT, BUF and ERR interrupt */
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-        /* Read data from DR */
-        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferCount--;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        if (hi2c->Mode == HAL_I2C_MODE_MEM)
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-          hi2c->PreviousState = I2C_STATE_NONE;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-          hi2c->MemRxCpltCallback(hi2c);
-#else
-          HAL_I2C_MemRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          hi2c->Mode = HAL_I2C_MODE_NONE;
-          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-          hi2c->MasterRxCpltCallback(hi2c);
-#else
-          HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Disable EVT, BUF and ERR interrupt */
-        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-        /* Read data from DR */
-        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-        /* Increment Buffer pointer */
-        hi2c->pBuffPtr++;
-
-        /* Update counter */
-        hi2c->XferCount--;
-
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-        /* Call user error callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->ErrorCallback(hi2c);
-#else
-        HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-    }
-    else
-    {
-      /* Do nothing */
-    }
-  }
-}
-
-/**
-  * @brief  Handle BTF flag for Master receiver
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  if (hi2c->XferCount == 4U)
-  {
-    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
-       on BTF subroutine if there is a reception delay between N-1 and N byte */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-  }
-  else if (hi2c->XferCount == 3U)
-  {
-    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
-       on BTF subroutine if there is a reception delay between N-1 and N byte */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
-    if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-  }
-  else if (hi2c->XferCount == 2U)
-  {
-    /* Prepare next transfer or stop current transfer */
-    if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-    else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-    else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else
-    {
-      /* Do nothing */
-    }
-
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-    if (hi2c->Mode == HAL_I2C_MODE_MEM)
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      hi2c->PreviousState = I2C_STATE_NONE;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MemRxCpltCallback(hi2c);
-#else
-      HAL_I2C_MemRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->MasterRxCpltCallback(hi2c);
-#else
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-  }
-}
-
-/**
-  * @brief  Handle SB flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->Mode == HAL_I2C_MODE_MEM)
-  {
-    if (hi2c->EventCount == 0U)
-    {
-      /* Send slave address */
-      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
-    }
-    else
-    {
-      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
-    }
-  }
-  else
-  {
-    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-    {
-      /* Send slave 7 Bits address */
-      if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
-      {
-        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
-      }
-      else
-      {
-        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
-      }
-
-      if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
-          || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
-      {
-        /* Enable DMA Request */
-        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-      }
-    }
-    else
-    {
-      if (hi2c->EventCount == 0U)
-      {
-        /* Send header of slave address */
-        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
-      }
-      else if (hi2c->EventCount == 1U)
-      {
-        /* Send header of slave address */
-        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
-      }
-      else
-      {
-        /* Do nothing */
-      }
-    }
-  }
-}
-
-/**
-  * @brief  Handle ADD10 flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
-{
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
-
-  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
-      || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
-  {
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-  }
-}
-
-/**
-  * @brief  Handle ADDR flag for Master
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  HAL_I2C_ModeTypeDef CurrentMode       = hi2c->Mode;
-  uint32_t CurrentXferOptions           = hi2c->XferOptions;
-  uint32_t Prev_State                   = hi2c->PreviousState;
-
-  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
-  {
-    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Restart */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-      hi2c->EventCount++;
-    }
-    else
-    {
-      if (hi2c->XferCount == 0U)
-      {
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-      }
-      else if (hi2c->XferCount == 1U)
-      {
-        if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
-        {
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-          {
-            /* Disable Acknowledge */
-            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-            /* Clear ADDR flag */
-            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-          }
-          else
-          {
-            /* Clear ADDR flag */
-            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-            /* Generate Stop */
-            SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-          }
-        }
-        /* Prepare next transfer or stop current transfer */
-        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
-                 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
-        {
-          if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
-          {
-            /* Disable Acknowledge */
-            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-          }
-          else
-          {
-            /* Enable Acknowledge */
-            SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-          }
-
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-        }
-        else
-        {
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Clear ADDR flag */
-          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-        }
-      }
-      else if (hi2c->XferCount == 2U)
-      {
-        if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
-        {
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Enable Pos */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-        }
-        else
-        {
-          /* Enable Acknowledge */
-          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-        }
-
-        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
-        {
-          /* Enable Last DMA bit */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      }
-      else
-      {
-        /* Enable Acknowledge */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
-        {
-          /* Enable Last DMA bit */
-          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-        }
-
-        /* Clear ADDR flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-      }
-
-      /* Reset Event counter  */
-      hi2c->EventCount = 0U;
-    }
-  }
-  else
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-  }
-}
-
-/**
-  * @brief  Handle TXE flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  if (hi2c->XferCount != 0U)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-
-    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
-    {
-      /* Last Byte is received, disable Interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->SlaveTxCpltCallback(hi2c);
-#else
-      HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  Handle BTF flag for Slave transmitter
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->XferCount != 0U)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = *hi2c->pBuffPtr;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-  }
-}
-
-/**
-  * @brief  Handle RXNE flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  if (hi2c->XferCount != 0U)
-  {
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-
-    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      /* Last Byte is received, disable Interrupt */
-      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->SlaveRxCpltCallback(hi2c);
-#else
-      HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  Handle BTF flag for Slave receiver
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if (hi2c->XferCount != 0U)
-  {
-    /* Read data from DR */
-    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
-
-    /* Update counter */
-    hi2c->XferCount--;
-  }
-}
-
-/**
-  * @brief  Handle ADD flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  IT2Flags Interrupt2 flags to handle.
-  * @retval None
-  */
-static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
-{
-  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
-  uint16_t SlaveAddrCode;
-
-  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
-    __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
-
-    /* Transfer Direction requested by Master */
-    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
-    {
-      TransferDirection = I2C_DIRECTION_TRANSMIT;
-    }
-
-    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
-    {
-      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
-    }
-    else
-    {
-      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Call Slave Addr callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-#else
-    HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-  }
-}
-
-/**
-  * @brief  Handle STOPF flag for Slave
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* If a DMA is ongoing, Update handle size context */
-  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-  {
-    if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
-    {
-      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
-
-      if (hi2c->XferCount != 0U)
-      {
-        /* Set ErrorCode corresponding to a Non-Acknowledge */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-
-      /* Disable, stop the current DMA */
-      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-      /* Abort DMA Xfer if any */
-      if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
-      {
-        /* Set the I2C DMA Abort callback :
-        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-        hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-        /* Abort DMA RX */
-        if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-        {
-          /* Call Directly XferAbortCallback function in case of error */
-          hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-        }
-      }
-    }
-    else
-    {
-      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
-
-      if (hi2c->XferCount != 0U)
-      {
-        /* Set ErrorCode corresponding to a Non-Acknowledge */
-        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      }
-
-      /* Disable, stop the current DMA */
-      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-      /* Abort DMA Xfer if any */
-      if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
-      {
-        /* Set the I2C DMA Abort callback :
-        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-        hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-        /* Abort DMA TX */
-        if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-        {
-          /* Call Directly XferAbortCallback function in case of error */
-          hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-        }
-      }
-    }
-  }
-
-  /* All data are not transferred, so set error code accordingly */
-  if (hi2c->XferCount != 0U)
-  {
-    /* Store Last receive data if any */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-    {
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-    }
-
-    /* Store Last receive data if any */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-
-      /* Update counter */
-      hi2c->XferCount--;
-    }
-
-    if (hi2c->XferCount != 0U)
-    {
-      /* Set ErrorCode corresponding to a Non-Acknowledge */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-    }
-  }
-
-  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-    I2C_ITError(hi2c);
-  }
-  else
-  {
-    if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->SlaveRxCpltCallback(hi2c);
-#else
-      HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-
-    if (hi2c->State == HAL_I2C_STATE_LISTEN)
-    {
-      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->ListenCpltCallback(hi2c);
-#else
-      HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      if ((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
-      {
-        hi2c->PreviousState = I2C_STATE_NONE;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->SlaveRxCpltCallback(hi2c);
-#else
-        HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-    }
-  }
-}
-
-/**
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-  uint32_t CurrentXferOptions       = hi2c->XferOptions;
-
-  if (((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
-      (CurrentState == HAL_I2C_STATE_LISTEN))
-  {
-    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->Mode          = HAL_I2C_MODE_NONE;
-
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ListenCpltCallback(hi2c);
-#else
-    HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
-  {
-    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->Mode          = HAL_I2C_MODE_NONE;
-
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->SlaveTxCpltCallback(hi2c);
-#else
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Clear AF flag only */
-    /* State Listen, but XferOptions == FIRST or NEXT */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-  }
-}
-
-/**
-  * @brief  I2C interrupts error process
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
-  uint32_t CurrentError;
-
-  if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
-  {
-    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-  }
-
-  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-  {
-    /* keep HAL_I2C_STATE_LISTEN */
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State = HAL_I2C_STATE_LISTEN;
-  }
-  else
-  {
-    /* If state is an abort treatment on going, don't change state */
-    /* This change will be do later */
-    if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-    }
-    hi2c->PreviousState = I2C_STATE_NONE;
-  }
-
-  /* Abort DMA transfer */
-  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
-  {
-    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
-    {
-      /* Set the DMA Abort callback :
-      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
-      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
-      {
-        /* Disable I2C peripheral to prevent dummy data in buffer */
-        __HAL_I2C_DISABLE(hi2c);
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Call Directly XferAbortCallback function in case of error */
-        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
-      }
-    }
-    else
-    {
-      /* Set the DMA Abort callback :
-      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
-      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
-      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
-      {
-        /* Store Last receive data if any */
-        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-        {
-          /* Read data from DR */
-          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-          /* Increment Buffer pointer */
-          hi2c->pBuffPtr++;
-        }
-
-        /* Disable I2C peripheral to prevent dummy data in buffer */
-        __HAL_I2C_DISABLE(hi2c);
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
-        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
-      }
-    }
-  }
-  else if (hi2c->State == HAL_I2C_STATE_ABORT)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Store Last receive data if any */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-    }
-
-    /* Disable I2C peripheral to prevent dummy data in buffer */
-    __HAL_I2C_DISABLE(hi2c);
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->AbortCpltCallback(hi2c);
-#else
-    HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Store Last receive data if any */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
-    {
-      /* Read data from DR */
-      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
-
-      /* Increment Buffer pointer */
-      hi2c->pBuffPtr++;
-    }
-
-    /* Call user error callback */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ErrorCallback(hi2c);
-#else
-    HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-
-  /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
-  CurrentError = hi2c->ErrorCode;
-
-  if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
-      ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
-      ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)     || \
-      ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
-  {
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-  }
-
-  /* So may inform upper layer that listen phase is stopped */
-  /* during NACK error treatment */
-  CurrentState = hi2c->State;
-  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
-  {
-    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
-    hi2c->PreviousState = I2C_STATE_NONE;
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->Mode          = HAL_I2C_MODE_NONE;
-
-    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ListenCpltCallback(hi2c);
-#else
-    HAL_I2C_ListenCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  /* Generate Start condition if first transfer */
-  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
-  {
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-  }
-  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
-  {
-    /* Generate ReStart */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  /* Wait until SB flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-    {
-      hi2c->ErrorCode = HAL_I2C_WRONG_START;
-    }
-    return HAL_TIMEOUT;
-  }
-
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  uint32_t CurrentXferOptions = hi2c->XferOptions;
-
-  /* Enable Acknowledge */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Generate Start condition if first transfer */
-  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
-  {
-    /* Generate Start */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-  }
-  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
-  {
-    /* Generate ReStart */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-  }
-  else
-  {
-    /* Do nothing */
-  }
-
-  /* Wait until SB flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-    {
-      hi2c->ErrorCode = HAL_I2C_WRONG_START;
-    }
-    return HAL_TIMEOUT;
-  }
-
-  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-
-    /* Wait until ADDR flag is set */
-    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Generate Restart */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    /* Wait until SB flag is set */
-    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-      {
-        hi2c->ErrorCode = HAL_I2C_WRONG_START;
-      }
-      return HAL_TIMEOUT;
-    }
-
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-    {
-      hi2c->ErrorCode = HAL_I2C_WRONG_START;
-    }
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    return HAL_ERROR;
-  }
-
-  /* If Memory address size is 8Bit */
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-      }
-      return HAL_ERROR;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress Target device address: The device 7 bits address value
-  *         in datasheet must be shifted to the left before calling the interface
-  * @param  MemAddress Internal memory address
-  * @param  MemAddSize Size of internal memory address
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Enable Acknowledge */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-    {
-      hi2c->ErrorCode = HAL_I2C_WRONG_START;
-    }
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    return HAL_ERROR;
-  }
-
-  /* If Memory address size is 8Bit */
-  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-      }
-      return HAL_ERROR;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TXE flag is set */
-  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
-  {
-    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    return HAL_ERROR;
-  }
-
-  /* Generate Restart */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
-  {
-    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
-    {
-      hi2c->ErrorCode = HAL_I2C_WRONG_START;
-    }
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DMA I2C process complete callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
-  uint32_t CurrentXferOptions       = hi2c->XferOptions;
-
-  /* Disable EVT and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-  /* Clear Complete callback */
-  if (hi2c->hdmatx != NULL)
-  {
-    hi2c->hdmatx->XferCpltCallback = NULL;
-  }
-  if (hi2c->hdmarx != NULL)
-  {
-    hi2c->hdmarx->XferCpltCallback = NULL;
-  }
-
-  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
-  {
-    /* Disable DMA Request */
-    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    hi2c->XferCount = 0U;
-
-    if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
-    {
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->SlaveTxCpltCallback(hi2c);
-#else
-      HAL_I2C_SlaveTxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
-    {
-      /* Set state at HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-
-      /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->SlaveRxCpltCallback(hi2c);
-#else
-      HAL_I2C_SlaveRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Do nothing */
-    }
-
-    /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-  }
-  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
-  else if (hi2c->Mode != HAL_I2C_MODE_NONE)
-  {
-    if (hi2c->XferCount == (uint16_t)1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* Prepare next transfer or stop current transfer */
-    if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-
-    /* Disable Last DMA */
-    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
-    /* Disable DMA Request */
-    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    hi2c->XferCount = 0U;
-
-    /* Check if Errors has been detected during transfer */
-    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-    {
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-      hi2c->ErrorCallback(hi2c);
-#else
-      HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      if (hi2c->Mode == HAL_I2C_MODE_MEM)
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        hi2c->PreviousState = I2C_STATE_NONE;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->MemRxCpltCallback(hi2c);
-#else
-        HAL_I2C_MemRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        hi2c->Mode = HAL_I2C_MODE_NONE;
-        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-        hi2c->MasterRxCpltCallback(hi2c);
-#else
-        HAL_I2C_MasterRxCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-      }
-    }
-  }
-  else
-  {
-    /* Do nothing */
-  }
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param  hdma DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Clear Complete callback */
-  if (hi2c->hdmatx != NULL)
-  {
-    hi2c->hdmatx->XferCpltCallback = NULL;
-  }
-  if (hi2c->hdmarx != NULL)
-  {
-    hi2c->hdmarx->XferCpltCallback = NULL;
-  }
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  hi2c->XferCount       = 0U;
-  hi2c->State           = HAL_I2C_STATE_READY;
-  hi2c->Mode            = HAL_I2C_MODE_NONE;
-  hi2c->ErrorCode       |= HAL_I2C_ERROR_DMA;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  hi2c->ErrorCallback(hi2c);
-#else
-  HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA I2C communication abort callback
-  *        (To be called at end of DMA Abort procedure).
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
-  __IO uint32_t count = 0U;
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
-  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
-
-  /* During abort treatment, check that there is no pending STOP request */
-  /* Wait until STOP flag is reset */
-  count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
-  do
-  {
-    if (count == 0U)
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      break;
-    }
-    count--;
-  }
-  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
-
-  /* Clear Complete callback */
-  if (hi2c->hdmatx != NULL)
-  {
-    hi2c->hdmatx->XferCpltCallback = NULL;
-  }
-  if (hi2c->hdmarx != NULL)
-  {
-    hi2c->hdmarx->XferCpltCallback = NULL;
-  }
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  hi2c->XferCount = 0U;
-
-  /* Reset XferAbortCallback */
-  if (hi2c->hdmatx != NULL)
-  {
-    hi2c->hdmatx->XferAbortCallback = NULL;
-  }
-  if (hi2c->hdmarx != NULL)
-  {
-    hi2c->hdmarx->XferAbortCallback = NULL;
-  }
-
-  /* Disable I2C peripheral to prevent dummy data in buffer */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* Check if come from abort from user */
-  if (hi2c->State == HAL_I2C_STATE_ABORT)
-  {
-    hi2c->State         = HAL_I2C_STATE_READY;
-    hi2c->Mode          = HAL_I2C_MODE_NONE;
-    hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->AbortCpltCallback(hi2c);
-#else
-    HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
-    {
-      /* Renable I2C peripheral */
-      __HAL_I2C_ENABLE(hi2c);
-
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* keep HAL_I2C_STATE_LISTEN */
-      hi2c->PreviousState = I2C_STATE_NONE;
-      hi2c->State = HAL_I2C_STATE_LISTEN;
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-    }
-
-    /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-    hi2c->ErrorCallback(hi2c);
-#else
-    HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag specifies the I2C flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Wait until flag is set */
-  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->PreviousState     = I2C_STATE_NONE;
-        hi2c->State             = HAL_I2C_STATE_READY;
-        hi2c->Mode              = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag specifies the I2C flag to check.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
-  {
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
-      /* Clear AF Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      hi2c->PreviousState       = I2C_STATE_NONE;
-      hi2c->State               = HAL_I2C_STATE_READY;
-      hi2c->Mode                = HAL_I2C_MODE_NONE;
-      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hi2c->PreviousState       = I2C_STATE_NONE;
-        hi2c->State               = HAL_I2C_STATE_READY;
-        hi2c->Mode                = HAL_I2C_MODE_NONE;
-        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_ERROR;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-    {
-      hi2c->PreviousState       = I2C_STATE_NONE;
-      hi2c->State               = HAL_I2C_STATE_READY;
-      hi2c->Mode                = HAL_I2C_MODE_NONE;
-      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
-{
-  __IO uint32_t count = 0U;
-
-  /* Wait until STOP flag is reset */
-  count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
-  do
-  {
-    count--;
-    if (count == 0U)
-    {
-      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-      return HAL_ERROR;
-    }
-  }
-  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
-  {
-    /* Check if a STOPF is detected */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
-    {
-      /* Clear STOP Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
-      hi2c->PreviousState       = I2C_STATE_NONE;
-      hi2c->State               = HAL_I2C_STATE_READY;
-      hi2c->Mode                = HAL_I2C_MODE_NONE;
-      hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-    {
-      hi2c->PreviousState       = I2C_STATE_NONE;
-      hi2c->State               = HAL_I2C_STATE_READY;
-      hi2c->Mode                = HAL_I2C_MODE_NONE;
-      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
-{
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-  {
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    hi2c->PreviousState       = I2C_STATE_NONE;
-    hi2c->State               = HAL_I2C_STATE_READY;
-    hi2c->Mode                = HAL_I2C_MODE_NONE;
-    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
-  * @param  hi2c I2C handle.
-  * @retval None
-  */
-static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
-{
-  /* if user set XferOptions to I2C_OTHER_FRAME            */
-  /* it request implicitly to generate a restart condition */
-  /* set XferOptions to I2C_FIRST_FRAME                    */
-  if (hi2c->XferOptions == I2C_OTHER_FRAME)
-  {
-    hi2c->XferOptions = I2C_FIRST_FRAME;
-  }
-  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
-  /* it request implicitly to generate a restart condition    */
-  /* then generate a stop condition at the end of transfer    */
-  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
-  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
-  {
-    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c
deleted file mode 100644
index 8e975e8d8b4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_i2s.c
+++ /dev/null
@@ -1,1857 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2s.c
-  * @author  MCD Application Team
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  @verbatim
- ===============================================================================
-                  ##### How to use this driver #####
- ===============================================================================
- [..]
-    The I2S HAL driver can be used as follow:
-
-    (#) Declare a I2S_HandleTypeDef handle structure.
-    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.
-        (##) I2S pins configuration:
-            (+++) Enable the clock for the I2S GPIOs.
-            (+++) Configure these I2S pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
-             and HAL_I2S_Receive_IT() APIs).
-            (+++) Configure the I2Sx interrupt priority.
-            (+++) Enable the NVIC I2S IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
-             and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Stream/Channel.
-            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
-                  DMA Tx/Rx Stream/Channel.
-
-   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_I2S_Init() function.
-
-   -@- The specific I2S interrupts (Transmission complete interrupt,
-       RXNE interrupt and Error Interrupts) will be managed using the macros
-       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-   -@- Make sure that either:
-        (+@) External clock source is configured after setting correctly
-             the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file.
-
-    (#) Three mode of operations are available within this driver :
-
-   *** Polling mode IO operation ***
-   =================================
-   [..]
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
-     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..]
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-         In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
-         HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
-         In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
-         inside DR register and avoid using DeInit/Init process for the next transfer.
-
-   *** I2S HAL driver macros list ***
-   ===================================
-   [..]
-     Below the list of most used macros in I2S HAL driver.
-
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
-      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
-      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-      (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
-
-    [..]
-      (@) You can refer to the I2S HAL driver header file for more useful macros
-
-   *** I2S HAL driver macros list ***
-   ===================================
-   [..]
-       Callback registration:
-
-      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
-          allows the user to configure dynamically the driver callbacks.
-          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
-
-          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
-            (++) TxCpltCallback        : I2S Tx Completed callback
-            (++) RxCpltCallback        : I2S Rx Completed callback
-            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
-            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
-            (++) ErrorCallback         : I2S Error callback
-            (++) MspInitCallback       : I2S Msp Init callback
-            (++) MspDeInitCallback     : I2S Msp DeInit callback
-          This function takes as parameters the HAL peripheral handle, the Callback ID
-          and a pointer to the user callback function.
-
-
-      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
-          weak function.
-          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
-          and the Callback ID.
-          This function allows to reset following callbacks:
-            (++) TxCpltCallback        : I2S Tx Completed callback
-            (++) RxCpltCallback        : I2S Rx Completed callback
-            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
-            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
-            (++) ErrorCallback         : I2S Error callback
-            (++) MspInitCallback       : I2S Msp Init callback
-            (++) MspDeInitCallback     : I2S Msp DeInit callback
-
-       [..]
-       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
-       all callbacks are set to the corresponding weak functions:
-       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
-       Exception done for MspInit and MspDeInit functions that are
-       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
-       these callbacks are null (not registered beforehand).
-       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
-       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
-       [..]
-       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
-       Exception done MspInit/MspDeInit functions that can be registered/unregistered
-       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
-       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-       Then, the user first registers the MspInit/MspDeInit user callbacks
-       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
-       or HAL_I2S_Init() function.
-
-       [..]
-       When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
-       not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_I2S_MODULE_ENABLED
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2S I2S
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define I2S_TIMEOUT_FLAG          100U         /*!< Timeout 100 ms            */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
-                                                        uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the I2Sx peripheral in simplex mode:
-
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2S_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Standard
-        (++) Data Format
-        (++) MCLK Output
-        (++) Audio frequency
-        (++) Polarity
-
-     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
-          of the selected I2Sx peripheral.
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2S according to the specified parameters
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t i2sdiv;
-  uint32_t i2sodd;
-  uint32_t packetlength;
-  uint32_t tmp;
-  uint32_t i2sclk;
-
-  /* Check the I2S handle allocation */
-  if (hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-
-  if (hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hi2s->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    /* Init the I2S Callback settings */
-    hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
-    hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
-    hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
-    hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
-    hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
-
-    if (hi2s->MspInitCallback == NULL)
-    {
-      hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    hi2s->MspInitCallback(hi2s);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2S_MspInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                                      SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                                      SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
-  hi2s->Instance->I2SPR = 0x0002U;
-
-  /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
-  {
-    /* Check the frame length (For the Prescaler computing) ********************/
-    if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 16U;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 32U;
-    }
-
-    /* I2S standard */
-    if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
-    {
-      /* In I2S standard packet length is multiplied by 2 */
-      packetlength = packetlength * 2U;
-    }
-
-    /* Get the source clock value: based on System Clock value */
-    i2sclk = HAL_RCC_GetSysClockFreq();
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
-      {
-        tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-      }
-      else
-      {
-        tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-      }
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10U;
-
-    /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t)(i2sodd << 8U);
-  }
-  else
-  {
-    /* Set the default values */
-    i2sdiv = 2U;
-    i2sodd = 0U;
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-  {
-    /* Set the error code and execute error callback*/
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
-    return  HAL_ERROR;
-  }
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  /* And configure the I2S with the I2S_InitStruct values                      */
-  MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
-                                       SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
-                                       SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                                       SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD), \
-             (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
-              hi2s->Init.Standard | hi2s->Init.DataFormat | \
-              hi2s->Init.CPOL));
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
-  if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
-  {
-    /* Write to SPIx I2SCFGR */
-    SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-  }
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State     = HAL_I2S_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DeInitializes the I2S peripheral
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Check the I2S handle allocation */
-  if (hi2s == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /* Disable the I2S Peripheral Clock */
-  __HAL_I2S_DISABLE(hi2s);
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  if (hi2s->MspDeInitCallback == NULL)
-  {
-    hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  hi2s->MspDeInitCallback(hi2s);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_I2S_MspDeInit(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State     = HAL_I2S_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2S MSP Init
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S MSP DeInit
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User I2S Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2S.
-  * @param  CallbackID ID of the callback to be registered
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
-  if (HAL_I2S_STATE_READY == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_TX_COMPLETE_CB_ID :
-        hi2s->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_RX_COMPLETE_CB_ID :
-        hi2s->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
-        hi2s->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
-        hi2s->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_I2S_ERROR_CB_ID :
-        hi2s->ErrorCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2S_STATE_RESET == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = pCallback;
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-  return status;
-}
-
-/**
-  * @brief  Unregister an I2S Callback
-  *         I2S callback is redirected to the weak predefined callback
-  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2S.
-  * @param  CallbackID ID of the callback to be unregistered
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
-  if (HAL_I2S_STATE_READY == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_TX_COMPLETE_CB_ID :
-        hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
-        break;
-
-      case HAL_I2S_RX_COMPLETE_CB_ID :
-        hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
-        break;
-
-      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
-        hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
-        break;
-
-      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
-        hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
-        break;
-
-      case HAL_I2S_ERROR_CB_ID :
-        hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_I2S_STATE_RESET == hi2s->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_I2S_MSPINIT_CB_ID :
-        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
-        break;
-
-      case HAL_I2S_MSPDEINIT_CB_ID :
-        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-  return status;
-}
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
-  *  @brief Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_Transmit()
-        (++) HAL_I2S_Receive()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_Transmit_IT()
-        (++) HAL_I2S_Receive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_Transmit_DMA()
-        (++) HAL_I2S_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @param  Timeout Timeout duration
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR;
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Wait until TXE flag is set */
-  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
-  {
-    /* Set the error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-    hi2s->State = HAL_I2S_STATE_READY;
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  while (hi2s->TxXferCount > 0U)
-  {
-    hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
-    hi2s->pTxBuffPtr++;
-    hi2s->TxXferCount--;
-
-    /* Wait until TXE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-
-    /* Check if an underrun occurs */
-    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
-    {
-      /* Clear underrun flag */
-      __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
-    }
-  }
-
-  /* Check if Slave mode is selected */
-  if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
-      || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
-  {
-    /* Wait until Busy flag is reset */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @param  Timeout Timeout duration
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if Master Receiver mode is selected */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-  {
-    /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-    access to the SPI_SR register. */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-  }
-
-  /* Receive data */
-  while (hi2s->RxXferCount > 0U)
-  {
-    /* Wait until RXNE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
-    }
-
-    (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
-    hi2s->pRxBuffPtr++;
-    hi2s->RxXferCount--;
-
-    /* Check if an overrun occurs */
-    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
-    {
-      /* Clear overrun flag */
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Receive data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
-  * between Master and Slave otherwise the I2S interrupt should be optimized.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Enable RXNE and ERR interrupt */
-  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-  /* Check if the I2S is already enabled */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Transmit data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_TX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->TxXferSize = (Size << 1U);
-    hi2s->TxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->TxXferSize = Size;
-    hi2s->TxXferCount = Size;
-  }
-
-  /* Set the I2S Tx DMA Half transfer complete callback */
-  hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-  /* Set the I2S Tx DMA transfer complete callback */
-  hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-  /* Set the DMA error callback */
-  hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-  /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
-                                 (uint32_t)hi2s->pTxBuffPtr,
-                                 (uint32_t)&hi2s->Instance->DR,
-                                 hi2s->TxXferSize))
-  {
-    /* Update SPI error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  /* Check if the I2S is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if the I2S Tx request is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Enable Tx DMA Request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  pData a 16-bit pointer to the Receive data buffer.
-  * @param  Size number of data sample to be sent:
-  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *         configuration phase, the Size parameter means the number of 16-bit data length
-  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
-  *         the Size parameter means the number of 24-bit or 32-bit data length.
-  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
-  *         between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  uint32_t tmpreg_cfgr;
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
-  /* Set state and reset error code */
-  hi2s->State = HAL_I2S_STATE_BUSY_RX;
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->pRxBuffPtr = pData;
-
-  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
-  {
-    hi2s->RxXferSize = (Size << 1U);
-    hi2s->RxXferCount = (Size << 1U);
-  }
-  else
-  {
-    hi2s->RxXferSize = Size;
-    hi2s->RxXferCount = Size;
-  }
-
-  /* Set the I2S Rx DMA Half transfer complete callback */
-  hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
-  /* Set the I2S Rx DMA transfer complete callback */
-  hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
-  /* Set the DMA error callback */
-  hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
-  /* Check if Master Receiver mode is selected */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-  {
-    /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-    access to the SPI_SR register. */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-  }
-
-  /* Enable the Rx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
-                                 hi2s->RxXferSize))
-  {
-    /* Update SPI error code */
-    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
-  }
-
-  /* Check if the I2S is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Check if the I2S Rx request is already enabled */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Enable Rx DMA Request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-
-  __HAL_UNLOCK(hi2s);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-  /* If the I2S peripheral is still not enabled, enable it */
-  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-  {
-    /* Enable I2S peripheral */
-    __HAL_I2S_ENABLE(hi2s);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the audio DMA Stream/Channel playing from the Media.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
-     when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
-     */
-
-  if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
-  {
-    /* Abort the I2S DMA tx Stream/Channel */
-    if (hi2s->hdmatx != NULL)
-    {
-      /* Disable the I2S DMA tx Stream/Channel */
-      if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
-      {
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-        errorcode = HAL_ERROR;
-      }
-    }
-
-    /* Wait until TXE flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode   = HAL_ERROR;
-    }
-
-    /* Wait until BSY flag is Reset */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode   = HAL_ERROR;
-    }
-
-    /* Disable I2S peripheral */
-    __HAL_I2S_DISABLE(hi2s);
-
-    /* Clear UDR flag */
-    __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
-    /* Disable the I2S Tx DMA requests */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-  }
-
-  else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
-  {
-    /* Abort the I2S DMA rx Stream/Channel */
-    if (hi2s->hdmarx != NULL)
-    {
-      /* Disable the I2S DMA rx Stream/Channel */
-      if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
-      {
-        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-        errorcode = HAL_ERROR;
-      }
-    }
-
-    /* Disable I2S peripheral */
-    __HAL_I2S_DISABLE(hi2s);
-
-    /* Clear OVR flag */
-    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
-    /* Disable the I2S Rx DMA request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
-    {
-      /* Set the error code */
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
-
-      /* Set the I2S State ready */
-      hi2s->State = HAL_I2S_STATE_READY;
-      errorcode = HAL_ERROR;
-    }
-    else
-    {
-      /* Read DR to Flush RX Data */
-      READ_REG((hi2s->Instance)->DR);
-    }
-  }
-
-  hi2s->State = HAL_I2S_STATE_READY;
-
-  return errorcode;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t itsource = hi2s->Instance->CR2;
-  uint32_t itflag   = hi2s->Instance->SR;
-
-  /* I2S in mode Receiver ------------------------------------------------*/
-  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
-      (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
-  {
-    I2S_Receive_IT(hi2s);
-    return;
-  }
-
-  /* I2S in mode Tramitter -----------------------------------------------*/
-  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
-  {
-    I2S_Transmit_IT(hi2s);
-    return;
-  }
-
-  /* I2S interrupt error -------------------------------------------------*/
-  if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
-  {
-    /* I2S Overrun error interrupt occurred ---------------------------------*/
-    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
-    }
-
-    /* I2S Underrun error interrupt occurred --------------------------------*/
-    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
-    }
-
-    /* Set the I2S State ready */
-    hi2s->State = HAL_I2S_STATE_READY;
-
-    /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->ErrorCallback(hi2s);
-#else
-    HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Tx Transfer Half completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer half completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2S error callbacks
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hi2s);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2S state
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL state
-  */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->State;
-}
-
-/**
-  * @brief  Return the I2S error code
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Error Code
-  */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/**
-  * @brief  DMA I2S transmit process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* if DMA is configured in DMA_NORMAL Mode */
-  if (hdma->Init.Mode == DMA_NORMAL)
-  {
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    hi2s->TxXferCount = 0U;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->TxCpltCallback(hi2s);
-#else
-  HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S transmit process half complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Tx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->TxHalfCpltCallback(hi2s);
-#else
-  HAL_I2S_TxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S receive process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* if DMA is configured in DMA_NORMAL Mode */
-  if (hdma->Init.Mode == DMA_NORMAL)
-  {
-    /* Disable Rx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-    hi2s->RxXferCount = 0U;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->RxCpltCallback(hi2s);
-#else
-  HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S receive process half complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Rx half complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->RxHalfCpltCallback(hi2s);
-#else
-  HAL_I2S_RxHalfCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA I2S communication error callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Disable Rx and Tx DMA Request */
-  CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-  hi2s->TxXferCount = 0U;
-  hi2s->RxXferCount = 0U;
-
-  hi2s->State = HAL_I2S_STATE_READY;
-
-  /* Set the error code and execute error callback*/
-  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-  /* Call user error callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  hi2s->ErrorCallback(hi2s);
-#else
-  HAL_I2S_ErrorCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Transmit data */
-  hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
-  hi2s->pTxBuffPtr++;
-  hi2s->TxXferCount--;
-
-  if (hi2s->TxXferCount == 0U)
-  {
-    /* Disable TXE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    /* Call user Tx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->TxCpltCallback(hi2s);
-#else
-    HAL_I2S_TxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Receive data */
-  (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
-  hi2s->pRxBuffPtr++;
-  hi2s->RxXferCount--;
-
-  if (hi2s->RxXferCount == 0U)
-  {
-    /* Disable RXNE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    /* Call user Rx complete callback */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-    hi2s->RxCpltCallback(hi2s);
-#else
-    HAL_I2S_RxCpltCallback(hi2s);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  This function handles I2S Communication Timeout.
-  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param  Flag Flag checked
-  * @param  State Value of the flag expected
-  * @param  Timeout Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set to status*/
-  while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
-      {
-        /* Set the I2S State ready */
-        hi2s->State = HAL_I2S_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2s);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c
deleted file mode 100644
index dc3048a70cd..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_irda.c
+++ /dev/null
@@ -1,2658 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_irda.c
-  * @author  MCD Application Team
-  * @brief   IRDA HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the IrDA SIR ENDEC block (IrDA):
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The IRDA HAL driver can be used as follows:
-
-    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
-    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) IRDA pins configuration:
-            (+++) Enable the clock for the IRDA GPIOs.
-            (+++) Configure IRDA pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
-             and HAL_IRDA_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
-             and HAL_IRDA_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-            (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
-                  (used for last byte sending completion detection in DMA non circular mode)
-
-    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
-        and Mode(Receiver/Transmitter) in the hirda Init structure.
-
-    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
-        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_IRDA_MspInit() API.
-
-         -@@- The specific IRDA interrupts (Transmission complete interrupt,
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
-    (#) Three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
-      (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
-      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
-      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
-      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
-    *** DMA mode IO operation ***
-    =============================
-    [..]
-      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
-      (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
-      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
-      (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
-      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
-      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-      (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
-      (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
-      (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
-
-    *** IRDA HAL driver macros list ***
-    ===================================
-    [..]
-      Below the list of most used macros in IRDA HAL driver.
-
-       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
-       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
-       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
-       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
-       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
-       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
-       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
-
-    [..]
-     (@) You can refer to the IRDA HAL driver header file for more useful macros
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-      The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-    [..]
-      Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
-      Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
-       (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-       (+) TxCpltCallback            : Tx Complete Callback.
-       (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-       (+) RxCpltCallback            : Rx Complete Callback.
-       (+) ErrorCallback             : Error Callback.
-       (+) AbortCpltCallback         : Abort Complete Callback.
-       (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-       (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-       (+) MspInitCallback           : IRDA MspInit.
-       (+) MspDeInitCallback         : IRDA MspDeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-    [..]
-      Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function.
-      @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-      and the Callback ID.
-      This function allows to reset following callbacks:
-       (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-       (+) TxCpltCallback            : Tx Complete Callback.
-       (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-       (+) RxCpltCallback            : Rx Complete Callback.
-       (+) ErrorCallback             : Error Callback.
-       (+) AbortCpltCallback         : Abort Complete Callback.
-       (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-       (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-       (+) MspInitCallback           : IRDA MspInit.
-       (+) MspDeInitCallback         : IRDA MspDeInit.
-
-    [..]
-      By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
-      all callbacks are set to the corresponding weak (surcharged) functions:
-      examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
-      Exception done for MspInit and MspDeInit functions that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
-      and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-      Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
-      Exception done MspInit/MspDeInit that can be registered/unregistered
-      in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
-      MspInit/DeInit callbacks can be used during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
-      or @ref HAL_IRDA_Init() function.
-
-    [..]
-      When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registration feature is not available
-      and weak (surcharged) callbacks are used.
-
-  @endverbatim
-     [..]
-       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible IRDA frame formats are as listed in the following table:
-    +-------------------------------------------------------------+
-    |   M bit |  PCE bit  |            IRDA frame                 |
-    |---------------------|---------------------------------------|
-    |    0    |    0      |    | SB | 8 bit data | 1 STB |        |
-    |---------|-----------|---------------------------------------|
-    |    0    |    1      |    | SB | 7 bit data | PB | 1 STB |   |
-    |---------|-----------|---------------------------------------|
-    |    1    |    0      |    | SB | 9 bit data | 1 STB |        |
-    |---------|-----------|---------------------------------------|
-    |    1    |    1      |    | SB | 8 bit data | PB | 1 STB |   |
-    +-------------------------------------------------------------+
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IRDA IRDA
-  * @brief HAL IRDA module driver
-  * @{
-  */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions
-  * @{
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
-  * @{
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-
-  ==============================================================================
-            ##### Initialization and Configuration functions #####
-  ==============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous IrDA mode.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) BaudRate
-        (++) WordLength
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible IRDA frame formats.
-        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
-             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
-             specification specifies a minimum of 10 ms delay between transmission and
-             reception (IrDA is a half duplex protocol).
-        (++) Mode: Receiver/transmitter modes
-        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
-    [..]
-    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
-    are available in reference manual).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the IRDA mode according to the specified
-  *         parameters in the IRDA_InitTypeDef and create the associated handle.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if (hirda == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the IRDA instance parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-  /* Check the IRDA mode parameter in the IRDA handle */
-  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
-
-  if (hirda->gState == HAL_IRDA_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hirda->Lock = HAL_UNLOCKED;
-
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-    IRDA_InitCallbacksToDefault(hirda);
-
-    if (hirda->MspInitCallback == NULL)
-    {
-      hirda->MspInitCallback = HAL_IRDA_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hirda->MspInitCallback(hirda);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_IRDA_MspInit(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-  }
-
-  hirda->gState = HAL_IRDA_STATE_BUSY;
-
-  /* Disable the IRDA peripheral */
-  __HAL_IRDA_DISABLE(hirda);
-
-  /* Set the IRDA communication parameters */
-  IRDA_SetConfig(hirda);
-
-  /* In IrDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
-  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-
-  /* Enable the IRDA peripheral */
-  __HAL_IRDA_ENABLE(hirda);
-
-  /* Set the prescaler */
-  MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-
-  /* Configure the IrDA mode */
-  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
-
-  /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-  SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
-
-  /* Initialize the IRDA state*/
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-  hirda->gState = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the IRDA peripheral
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if (hirda == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
-  hirda->gState = HAL_IRDA_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_IRDA_DISABLE(hirda);
-
-  /* DeInit the low level hardware */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-  if (hirda->MspDeInitCallback == NULL)
-  {
-    hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hirda->MspDeInitCallback(hirda);
-#else
-  HAL_IRDA_MspDeInit(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  hirda->gState = HAL_IRDA_STATE_RESET;
-  hirda->RxState = HAL_IRDA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  IRDA MSP Init.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  IRDA MSP DeInit.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User IRDA Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hirda irda handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hirda);
-
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
-        hirda->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_TX_COMPLETE_CB_ID :
-        hirda->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
-        hirda->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_RX_COMPLETE_CB_ID :
-        hirda->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ERROR_CB_ID :
-        hirda->ErrorCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
-        hirda->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hirda->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hirda->AbortReceiveCpltCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hirda->gState == HAL_IRDA_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = pCallback;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an IRDA callback
-  *         IRDA callback is redirected to the weak predefined callback
-  * @param  hirda irda handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hirda);
-
-  if (HAL_IRDA_STATE_READY == hirda->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
-        hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
-        break;
-
-      case HAL_IRDA_TX_COMPLETE_CB_ID :
-        hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
-        break;
-
-      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
-        hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
-        break;
-
-      case HAL_IRDA_RX_COMPLETE_CB_ID :
-        hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
-        break;
-
-      case HAL_IRDA_ERROR_CB_ID :
-        hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback             */
-        break;
-
-      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
-        hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
-        break;
-
-      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-        break;
-
-      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
-        break;
-
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback           */
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_IRDA_STATE_RESET == hirda->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_IRDA_MSPINIT_CB_ID :
-        hirda->MspInitCallback = HAL_IRDA_MspInit;
-        break;
-
-      case HAL_IRDA_MSPDEINIT_CB_ID :
-        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return status;
-}
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
-  *  @brief   IRDA Transmit and Receive functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the IRDA data transfers.
-    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
-    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
-    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
-    While receiving data, transmission should be avoided as the data to be transmitted
-    could be corrupted.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) Non-Blocking mode: The communication is performed using Interrupts
-           or DMA, these API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the Transmit or Receive process
-           The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_IRDA_Transmit()
-        (++) HAL_IRDA_Receive()
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_IRDA_Transmit_IT()
-        (++) HAL_IRDA_Receive_IT()
-        (++) HAL_IRDA_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_IRDA_Transmit_DMA()
-        (++) HAL_IRDA_Receive_DMA()
-        (++) HAL_IRDA_DMAPause()
-        (++) HAL_IRDA_DMAResume()
-        (++) HAL_IRDA_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
-        (++) HAL_IRDA_TxHalfCpltCallback()
-        (++) HAL_IRDA_TxCpltCallback()
-        (++) HAL_IRDA_RxHalfCpltCallback()
-        (++) HAL_IRDA_RxCpltCallback()
-        (++) HAL_IRDA_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_IRDA_Abort()
-        (+) HAL_IRDA_AbortTransmit()
-        (+) HAL_IRDA_AbortReceive()
-        (+) HAL_IRDA_Abort_IT()
-        (+) HAL_IRDA_AbortTransmit_IT()
-        (+) HAL_IRDA_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_IRDA_AbortCpltCallback()
-        (+) HAL_IRDA_AbortTransmitCpltCallback()
-        (+) HAL_IRDA_AbortReceiveCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
-            If user wants to abort it, Abort services should be called by user.
-        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Sends an amount of data in blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be sent.
-  * @param Timeout Specify timeout value.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t *tmp;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-    while (hirda->TxXferCount > 0U)
-    {
-      hirda->TxXferCount--;
-      if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-      {
-        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t *) pData;
-        hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if (hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          pData += 2U;
-        }
-        else
-        {
-          pData += 1U;
-        }
-      }
-      else
-      {
-        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
-      }
-    }
-
-    if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore hirda->gState to Ready */
-    hirda->gState = HAL_IRDA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be received.
-  * @param Timeout Specify timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t *tmp;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-
-    /* Check the remain data to be received */
-    while (hirda->RxXferCount > 0U)
-    {
-      hirda->RxXferCount--;
-
-      if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-      {
-        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t *) pData ;
-        if (hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
-          pData += 2U;
-        }
-        else
-        {
-          *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
-          pData += 1U;
-        }
-      }
-      else
-      {
-        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if (hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
-        }
-      }
-    }
-
-    /* At end of Rx process, restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in non blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Transmit Data Register Empty Interrupt */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non blocking mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-    /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in DMA mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Tx process is not already ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
-    /* Set the IRDA DMA half transfer complete callback */
-    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
-    /* Set the DMA abort callback */
-    hirda->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the IRDA transmit DMA channel */
-    tmp = (uint32_t *)&pData;
-    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the USART CR3 register */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receives an amount of data in DMA mode.
-  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *        the received data is handled as a set of u16. In this case, Size must reflect the number
-  *        of u16 available through pData.
-  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA module.
-  * @param pData Pointer to data buffer (u8 or u16 data elements).
-  * @param Size  Amount of data elements (u8 or u16) to be received.
-  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Rx process is not already ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
-    /* Set the IRDA DMA half transfer complete callback */
-    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
-    /* Set the DMA abort callback */
-    hirda->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t *)&pData;
-    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size);
-
-    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Parity Error Interrupt */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-    in the USART CR3 register */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t dmarequest = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
-  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
-  {
-    /* Disable the IRDA DMA Tx request */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
-  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
-  {
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the IRDA DMA Rx request */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    /* Enable the IRDA DMA Tx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer */
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the IRDA DMA Rx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t dmarequest = 0x00U;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
-  */
-
-  /* Stop IRDA DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
-  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel */
-    if (hirda->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(hirda->hdmatx);
-    }
-    IRDA_EndTxTransfer(hirda);
-  }
-
-  /* Stop IRDA DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
-  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel */
-    if (hirda->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(hirda->hdmarx);
-    }
-    IRDA_EndRxTransfer(hirda);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hirda->hdmatx);
-    }
-  }
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hirda->hdmarx);
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  hirda->TxXferCount = 0x00U;
-  hirda->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Restore hirda->RxState and hirda->gState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hirda->hdmatx);
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  hirda->TxXferCount = 0x00U;
-
-  /* Restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hirda->hdmarx);
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  hirda->RxXferCount = 0x00U;
-
-  /* Restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t AbortCplt = 0x01U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hirda->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-    {
-      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
-    }
-    else
-    {
-      hirda->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hirda->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-    {
-      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
-    }
-    else
-    {
-      hirda->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at IRDA level */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* IRDA Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
-      {
-        hirda->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* IRDA Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-      {
-        hirda->hdmarx->XferAbortCallback = NULL;
-        AbortCplt = 0x01U;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (AbortCplt == 0x01U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hirda->TxXferCount = 0x00U;
-    hirda->RxXferCount = 0x00U;
-
-    /* Reset ErrorCode */
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-    /* Restore hirda->gState and hirda->RxState to Ready */
-    hirda->gState  = HAL_IRDA_STATE_READY;
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    hirda->AbortCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable IRDA Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the IRDA DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmatx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
-      {
-        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
-        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      hirda->TxXferCount = 0x00U;
-
-      /* Restore hirda->gState to Ready */
-      hirda->gState = HAL_IRDA_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      hirda->AbortTransmitCpltCallback(hirda);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    hirda->TxXferCount = 0x00U;
-
-    /* Restore hirda->gState to Ready */
-    hirda->gState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    hirda->AbortTransmitCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  hirda IRDA handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the IRDA DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (hirda->hdmarx != NULL)
-    {
-      /* Set the IRDA DMA Abort callback :
-         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-      {
-        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
-        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      hirda->RxXferCount = 0x00U;
-
-      /* Restore hirda->RxState to Ready */
-      hirda->RxState = HAL_IRDA_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      hirda->AbortReceiveCpltCallback(hirda);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    hirda->RxXferCount = 0x00U;
-
-    /* Restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    hirda->AbortReceiveCpltCallback(hirda);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles IRDA interrupt request.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t isrflags   = READ_REG(hirda->Instance->SR);
-  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
-  uint32_t cr3its     = READ_REG(hirda->Instance->CR3);
-  uint32_t errorflags = 0x00U;
-  uint32_t dmarequest = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if (errorflags == RESET)
-  {
-    /* IRDA in mode Receiver -----------------------------------------------*/
-    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      IRDA_Receive_IT(hirda);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* IRDA parity error interrupt occurred -------------------------------*/
-    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
-    }
-
-    /* IRDA noise error interrupt occurred --------------------------------*/
-    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
-    }
-
-    /* IRDA frame error interrupt occurred --------------------------------*/
-    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
-    }
-
-    /* IRDA Over-Run interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
-    }
-    /* Call IRDA Error Call back function if need be -----------------------*/
-    if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
-    {
-      /* IRDA in mode Receiver ---------------------------------------------*/
-      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        IRDA_Receive_IT(hirda);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
-      if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Blocking error : transfer is aborted
-           Set the IRDA state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        IRDA_EndRxTransfer(hirda);
-
-        /* Disable the IRDA DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the IRDA DMA Rx channel */
-          if (hirda->hdmarx != NULL)
-          {
-            /* Set the IRDA DMA Abort callback :
-            will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
-            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
-
-            /* Abort DMA RX */
-            if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
-            }
-          }
-          else
-          {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-            /* Call registered user error callback */
-            hirda->ErrorCallback(hirda);
-#else
-            /* Call legacy weak user error callback */
-            HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-          }
-        }
-        else
-        {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-          /* Call registered user error callback */
-          hirda->ErrorCallback(hirda);
-#else
-          /* Call legacy weak user error callback */
-          HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-        /* Call registered user error callback */
-        hirda->ErrorCallback(hirda);
-#else
-        /* Call legacy weak user error callback */
-        HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-
-        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-      }
-    }
-    return;
-  } /* End if some error occurs */
-
-  /* IRDA in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    IRDA_Transmit_IT(hirda);
-    return;
-  }
-
-  /* IRDA in mode Transmitter end --------------------------------------------*/
-  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    IRDA_EndTransmit_IT(hirda);
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer complete callback.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Transfer complete callback.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer complete callback.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA error callback.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Transmit Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  IRDA Abort Receive Complete callback.
-  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hirda);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   IRDA State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to return the State of IrDA
-    communication process and also return Peripheral Errors occurred during communication process
-     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
-     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the IRDA state.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA.
-  * @retval HAL state
-  */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t temp1 = 0x00U, temp2 = 0x00U;
-  temp1 = hirda->gState;
-  temp2 = hirda->RxState;
-
-  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the IRDA error code
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *              the configuration information for the specified IRDA.
-  * @retval IRDA Error Code
-  */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
-  return hirda->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
-  * @{
-  */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  hirda IRDA handle.
-  * @retval none
-  */
-void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
-{
-  /* Init the IRDA Callback settings */
-  hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-
-}
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @brief  DMA IRDA transmit process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA.
-  * @retval None
-  */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    hirda->TxXferCount = 0U;
-
-    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the IRDA Transmit Complete Interrupt */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-  }
-  /* DMA Circular mode */
-  else
-  {
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-    /* Call registered Tx complete callback */
-    hirda->TxCpltCallback(hirda);
-#else
-    /* Call legacy weak Tx complete callback */
-    HAL_IRDA_TxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-  }
-}
-
-/**
-  * @brief DMA IRDA receive process half complete callback
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA.
-  * @retval None
-  */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx Half complete callback */
-  hirda->TxHalfCpltCallback(hirda);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_IRDA_TxHalfCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA receive process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA.
-  * @retval None
-  */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* DMA Normal mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    hirda->RxXferCount = 0U;
-
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* At end of Rx process, restore hirda->RxState to Ready */
-    hirda->RxState = HAL_IRDA_STATE_READY;
-  }
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx complete callback */
-  hirda->RxCpltCallback(hirda);
-#else
-  /* Call legacy weak Rx complete callback */
-  HAL_IRDA_RxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief DMA IRDA receive process half complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA.
-  * @retval None
-  */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /*Call registered Rx Half complete callback*/
-  hirda->RxHalfCpltCallback(hirda);
-#else
-  /* Call legacy weak Rx Half complete callback */
-  HAL_IRDA_RxHalfCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA communication error callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA.
-  * @retval None
-  */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Stop IRDA DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
-  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
-  {
-    hirda->TxXferCount = 0U;
-    IRDA_EndTxTransfer(hirda);
-  }
-
-  /* Stop IRDA DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
-  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
-  {
-    hirda->RxXferCount = 0U;
-    IRDA_EndRxTransfer(hirda);
-  }
-
-  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hirda->ErrorCallback(hirda);
-#else
-  /* Call legacy weak user error callback */
-  HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  This function handles IRDA Communication Timeout.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA.
-  * @param  Flag specifies the IRDA flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-        hirda->gState  = HAL_IRDA_STATE_READY;
-        hirda->RxState = HAL_IRDA_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hirda);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
-  * @param  hirda IRDA handle.
-  * @retval None
-  */
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-}
-
-/**
-  * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
-  * @param  hirda IRDA handle.
-  * @retval None
-  */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-/**
-  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  hirda->RxXferCount = 0x00U;
-  hirda->TxXferCount = 0x00U;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hirda->ErrorCallback(hirda);
-#else
-  /* Call legacy weak user error callback */
-  HAL_IRDA_ErrorCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hirda->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hirda->hdmarx != NULL)
-  {
-    if (hirda->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hirda->TxXferCount = 0x00U;
-  hirda->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Restore hirda->gState and hirda->RxState to Ready */
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hirda->AbortCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hirda->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (hirda->hdmatx != NULL)
-  {
-    if (hirda->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hirda->TxXferCount = 0x00U;
-  hirda->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-  /* Restore hirda->gState and hirda->RxState to Ready */
-  hirda->gState  = HAL_IRDA_STATE_READY;
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hirda->AbortCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_IRDA_AbortCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
-  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hirda->TxXferCount = 0x00U;
-
-  /* Restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  hirda->AbortTransmitCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_IRDA_AbortTransmitCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
-  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  hirda->RxXferCount = 0x00U;
-
-  /* Restore hirda->RxState to Ready */
-  hirda->RxState = HAL_IRDA_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  hirda->AbortReceiveCpltCallback(hirda);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_IRDA_AbortReceiveCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-}
-
-/**
- * @brief  Send an amount of data in non blocking mode.
- * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
- *                the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t *tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
-  {
-    if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t *) hirda->pTxBuffPtr;
-      hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      if (hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        hirda->pTxBuffPtr += 2U;
-      }
-      else
-      {
-        hirda->pTxBuffPtr += 1U;
-      }
-    }
-    else
-    {
-      hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
-    }
-
-    if (--hirda->TxXferCount == 0U)
-    {
-      /* Disable the IRDA Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the IRDA Transmit Complete Interrupt */
-      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable the IRDA Transmit Complete Interrupt */
-  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
-  /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-  /* Tx process is ended, restore hirda->gState to Ready */
-  hirda->gState = HAL_IRDA_STATE_READY;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx complete callback */
-  hirda->TxCpltCallback(hirda);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_IRDA_TxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t *tmp;
-  uint16_t  uhdata;
-
-  /* Check that a Rx process is ongoing */
-  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
-  {
-    uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
-    if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t *) hirda->pRxBuffPtr;
-      if (hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
-        hirda->pRxBuffPtr += 2U;
-      }
-      else
-      {
-        *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
-        hirda->pRxBuffPtr += 1U;
-      }
-    }
-    else
-    {
-      if (hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
-      }
-    }
-
-    if (--hirda->RxXferCount == 0U)
-    {
-      /* Disable the IRDA Data Register not empty Interrupt */
-      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
-
-      /* Disable the IRDA Parity Error Interrupt */
-      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
-      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore hirda->RxState to Ready */
-      hirda->RxState = HAL_IRDA_STATE_READY;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx complete callback */
-      hirda->RxCpltCallback(hirda);
-#else
-      /* Call legacy weak Rx complete callback */
-      HAL_IRDA_RxCpltCallback(hirda);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configures the IRDA peripheral.
-  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
-  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
-  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
-  assert_param(IS_IRDA_MODE(hirda->Init.Mode));
-  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
-
-  /*-------------------------- USART CR2 Configuration ------------------------*/
-  /* Clear STOP[13:12] bits */
-  CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE and RE bits */
-  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE));
-
-  /* Configure the USART Word Length, Parity and mode:
-     Set the M bits according to hirda->Init.WordLength value
-     Set PCE and PS bits according to hirda->Init.Parity value
-     Set TE and RE bits according to hirda->Init.Mode value */
-  /* Write to USART CR1 */
-  SET_BIT(hirda->Instance->CR1, (hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode));
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if (hirda->Instance == USART1)
-  {
-    pclk = HAL_RCC_GetPCLK2Freq();
-    hirda->Instance->BRR = IRDA_BRR(pclk, hirda->Init.BaudRate);
-  }
-  else
-  {
-    pclk = HAL_RCC_GetPCLK1Freq();
-    hirda->Instance->BRR = IRDA_BRR(pclk, hirda->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c
deleted file mode 100644
index e98aaa5dfeb..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_iwdg.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_iwdg.c
-  * @author  MCD Application Team
-  * @brief   IWDG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Independent Watchdog (IWDG) peripheral:
-  *           + Initialization and Start functions
-  *           + IO operation functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### IWDG Generic features #####
-  ==============================================================================
-  [..]
-    (+) The IWDG can be started by either software or hardware (configurable
-        through option byte).
-
-    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
-        active even if the main clock fails.
-
-    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
-        disabled. The counter starts counting down from the reset value (0xFFF).
-        When it reaches the end of count value (0x000) a reset signal is
-        generated (IWDG reset).
-
-    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
-        the IWDG_RLR value is reloaded into the counter and the watchdog reset
-        is prevented.
-
-    (+) The IWDG is implemented in the VDD voltage domain that is still functional
-        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
-        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
-        reset occurs.
-
-    (+) Debug mode: When the microcontroller enters debug mode (core halted),
-        the IWDG counter either continues to work normally or stops, depending
-        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
-        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
-
-    [..] Min-max timeout value @37KHz (LSI): ~108.1us / ~28.28s
-         The IWDG timeout may vary due to LSI clock frequency dispersion.
-         STM32L1xx devices provide the capability to measure the LSI clock
-         frequency (LSI clock is internally connected to TIM10 CH1 input capture).
-         The measured value can be used to have an IWDG timeout with an
-         acceptable accuracy.
-
-    [..] Default timeout value (necessary for IWDG_SR status register update):
-         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
-         This frequency being subject to variations as mentioned above, the
-         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
-         below) may become too short or too long.
-         In such cases, this default timeout value can be tuned by redefining
-         the constant LSI_VALUE at user-application level (based, for instance,
-         on the measured LSI clock frequency as explained above).
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (#) Use IWDG using HAL_IWDG_Init() function to :
-      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
-           clock is forced ON and IWDG counter starts counting down.
-      (++) Enable write access to configuration registers:
-          IWDG_PR and IWDG_RLR.
-      (++) Configure the IWDG prescaler and counter reload value. This reload
-           value will be loaded in the IWDG counter each time the watchdog is
-           reloaded, then the IWDG will start counting down from this value.
-      (++) Wait for status flags to be reset.
-
-    (#) Then the application program must refresh the IWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
-        HAL_IWDG_Refresh() function.
-
-     *** IWDG HAL driver macros list ***
-     ====================================
-     [..]
-       Below the list of most used macros in IWDG HAL driver:
-      (+) __HAL_IWDG_START: Enable the IWDG peripheral
-      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
-          the reload register
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-/** @addtogroup IWDG
-  * @brief IWDG HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
-  * @{
-  */
-/* Status register needs up to 5 LSI clock periods divided by the clock
-   prescaler to be updated. The number of LSI clock periods is upper-rounded to
-   6 for the timeout value calculation.
-   The timeout value is calculated using the highest prescaler (256) and
-   the LSI_VALUE constant. The value of this constant can be changed by the user
-   to take into account possible LSI clock period variations.
-   The timeout value is multiplied by 1000 to be converted in milliseconds.
-   LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
-   converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
-#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_RVU | IWDG_SR_PVU)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
-  *  @brief    Initialization and Start functions.
-  *
-@verbatim
- ===============================================================================
-          ##### Initialization and Start functions #####
- ===============================================================================
- [..]  This section provides functions allowing to:
-      (+) Initialize the IWDG according to the specified parameters in the
-          IWDG_InitTypeDef of associated handle.
-      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
-          is reloaded in order to exit function with correct time base.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the IWDG according to the specified parameters in the
-  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
-  *         watchdog is refreshed in order to have correct time base.
-  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
-  uint32_t tickstart;
-
-  /* Check the IWDG handle allocation */
-  if (hiwdg == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
-  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
-  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-
-  /* Enable IWDG. LSI is turned on automatically */
-  __HAL_IWDG_START(hiwdg);
-
-  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing
-  0x5555 in KR */
-  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
-  /* Write to IWDG registers the Prescaler & Reload values to work with */
-  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
-  hiwdg->Instance->RLR = hiwdg->Init.Reload;
-
-  /* Check pending flag, if previous update not done, return timeout */
-  tickstart = HAL_GetTick();
-
-  /* Wait for register to be updated */
-  while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
-  {
-    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
-    {
-      if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Reload IWDG counter with value defined in the reload register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup IWDG_Exported_Functions_Group2
-  *  @brief   IO operation functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]  This section provides functions allowing to:
-      (+) Refresh the IWDG.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Refresh the IWDG.
-  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Reload IWDG counter with value defined in the reload register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c
deleted file mode 100644
index 27b2b37d2c6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_lcd.c
+++ /dev/null
@@ -1,615 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_lcd.c
-  * @author  MCD Application Team
-  * @brief   LCD Controller HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the LCD Controller (LCD) peripheral:
-  *           + Initialization/de-initialization methods
-  *           + I/O operation methods
-  *           + Peripheral State methods
-  *           
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================   
-      [..] The LCD HAL driver can be used as follows:
-    
-      (#) Declare a LCD_HandleTypeDef handle structure.
-
-      (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API:
-          (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
-               (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and 
-                     selected clock source (HSE, LSI or LSE)
-               (+++) The frequency generator allows you to achieve various LCD frame rates 
-                     starting from an LCD input clock frequency (LCDCLK) which can vary 
-                     from 32 kHz up to 1 MHz.
-          (##) LCD pins configuration:
-               (+++) Enable the clock for the LCD GPIOs.
-               (+++) Configure these LCD pins as alternate function no-pull.
-          (##) Enable the LCD interface clock.
-
-      (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
-           Voltage Source, Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
-
-      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
-
-      -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
-          by calling the custumed HAL_LCD_MspInit() API.
-      -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
-
-      (#) Optionally you can update the LCD configuration using these macros:
-          (++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
-          (++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
-          (++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro  
-          (++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
-          (++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro  
-
-      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
-          more time to update the different LCD RAM registers before calling 
-          HAL_LCD_UpdateDisplayRequest() API.
-
-      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
-
-      (#) When LCD RAM memory is updated enable the update display request using
-          the HAL_LCD_UpdateDisplayRequest() API.
-
-      [..] LCD and low power modes:
-           (#) The LCD remain active during STOP mode.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_LCD_MODULE_ENABLED
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
-
-/** @defgroup LCD LCD
-  * @brief LCD HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup LCD_Private_Defines LCD Private Defines
-  * @{
-  */
-
-#define LCD_TIMEOUT_VALUE             1000
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Functions LCD Exported Functions
-  * @{
-  */
-
-/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-    [..]
-
-@endverbatim
-  * @{
-  */
- 
-/**
-  * @brief  DeInitializes the LCD peripheral. 
-  * @param  hlcd LCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Check the LCD handle allocation */
-  if(hlcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-
-  /* Check the LCD peripheral state */
-  if(hlcd->State == HAL_LCD_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-
-  hlcd->State = HAL_LCD_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_LCD_DISABLE(hlcd);
-
-  /*Disable Highdrive by default*/
-  __HAL_LCD_HIGHDRIVER_DISABLE(hlcd);
-  
-  /* DeInit the low level hardware */
-  HAL_LCD_MspDeInit(hlcd);
-  
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State = HAL_LCD_STATE_RESET;
-    
-  /* Release Lock */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Initializes the LCD peripheral according to the specified parameters 
-  *         in the LCD_InitStruct.
-  * @note   This function can be used only when the LCD is disabled.  
-  *         The LCD HighDrive can be enabled/disabled using related macros up to user.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00;
-  uint8_t counter = 0;
-    
-  /* Check the LCD handle allocation */
-  if(hlcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check function parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-  assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
-  assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
-  assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
-  assert_param(IS_LCD_BIAS(hlcd->Init.Bias));  
-  assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
-  assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
-  assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive));
-  assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
-  assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); 
-  assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); 
-  assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); 
-  assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment));
-  
-  if(hlcd->State == HAL_LCD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hlcd->Lock = HAL_UNLOCKED;
-
-    /* Initialize the low level hardware (MSP) */
-    HAL_LCD_MspInit(hlcd);
-  }
-  
-  hlcd->State = HAL_LCD_STATE_BUSY;
-  
-  /* Disable the peripheral */
-  __HAL_LCD_DISABLE(hlcd);
-  
-  /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
-     in the LCD_SR register */
-  for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-  {
-    hlcd->Instance->RAM[counter] = 0;
-  }
-  /* Enable the display request */
-  SET_BIT(hlcd->Instance->SR, LCD_SR_UDR);
-  
-  /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: 
-     Set PS[3:0] bits according to hlcd->Init.Prescaler value 
-     Set DIV[3:0] bits according to hlcd->Init.Divider value
-     Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
-     Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
-     Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
-     Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value 
-     Set CC[2:0] bits according to hlcd->Init.Contrast value
-     Set HD[0] bit according to hlcd->Init.HighDrive value */
-   MODIFY_REG(hlcd->Instance->FCR, \
-      (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
-       LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \
-      (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
-             hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
-
-  /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register 
-     This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
-     domain. It is cleared by hardware when writing to the LCD_FCR register.*/
-  LCD_WaitForSynchro(hlcd);
-  
-  /* Configure the LCD Duty, Bias, Voltage Source, Dead Time:
-     Set DUTY[2:0] bits according to hlcd->Init.Duty value 
-     Set BIAS[1:0] bits according to hlcd->Init.Bias value
-     Set VSEL bit according to hlcd->Init.VoltageSource value
-     Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
-  MODIFY_REG(hlcd->Instance->CR, \
-    (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
-    (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
-  
-  /* Enable the peripheral */
-  __HAL_LCD_ENABLE(hlcd);
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-      
-  /* Wait Until the LCD is enabled */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_ENS;     
-      return HAL_TIMEOUT;
-    } 
-  }
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD Booster is ready */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    {   
-      hlcd->ErrorCode = HAL_LCD_ERROR_RDY;  
-      return HAL_TIMEOUT;
-    } 
-  }
- 
-  /* Initialize the LCD state */
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State= HAL_LCD_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  LCD MSP DeInit.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlcd);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  LCD MSP Init.
-  * @param  hlcd LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hlcd);
-
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group2 IO operation methods 
-  *  @brief LCD RAM functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
- [..] Using its double buffer memory the LCD controller ensures the coherency of the 
- displayed information without having to use interrupts to control LCD_RAM 
- modification.
- (+)The application software can access the first buffer level (LCD_RAM) through 
- the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
- it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
- This UDR flag (update display request) requests the updated information to be 
- moved into the second buffer level (LCD_DISPLAY).
- (+)This operation is done synchronously with the frame (at the beginning of the 
- next frame), until the update is completed, the LCD_RAM is write protected and 
- the UDR flag stays high.
- (+)Once the update is completed another flag (UDD - Update Display Done) is set and
- generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
- The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one 
- even frame.
- (+)The update will not occur (UDR = 1 and UDD = 0) until the display is 
- enabled (LCDEN = 1).
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a word in the specific LCD RAM.
-  * @param  hlcd LCD handle
-  * @param  RAMRegisterIndex specifies the LCD RAM Register.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
-  *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
-  *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
-  *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
-  *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
-  *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
-  *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6 
-  *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7  
-  *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
-  *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
-  *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
-  *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
-  *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12 
-  *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13 
-  *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14 
-  *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
-  * @param  RAMRegisterMask specifies the LCD RAM Register Data Mask.
-  * @param  Data specifies LCD Data Value to be written.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
-{
-  uint32_t tickstart = 0x00; 
-  
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Check the parameters */
-    assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
-    
-    if(hlcd->State == HAL_LCD_STATE_READY)
-    {
-      /* Process Locked */
-      __HAL_LOCK(hlcd);
-      hlcd->State = HAL_LCD_STATE_BUSY;
-      
-      /* Get timeout */
-      tickstart = HAL_GetTick();
-      
-      /*!< Wait Until the LCD is ready */
-      while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-        { 
-          hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hlcd);
-          
-          return HAL_TIMEOUT;
-        } 
-      }
-    }
-    
-    /* Copy the new Data bytes to LCD RAM register */
-    MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief Clears the LCD RAM registers.
-  * @param hlcd: LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00; 
-  uint32_t counter = 0;
-  
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hlcd);
-    
-    hlcd->State = HAL_LCD_STATE_BUSY;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    /*!< Wait Until the LCD is ready */
-    while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-      { 
-        hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hlcd);
-        
-        return HAL_TIMEOUT;
-      } 
-    }
-    /* Clear the LCD_RAM registers */
-    for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-    {
-      hlcd->Instance->RAM[counter] = 0;
-    }
-    
-    /* Update the LCD display */
-    HAL_LCD_UpdateDisplayRequest(hlcd);     
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enables the Update Display Request.
-  * @param  hlcd LCD handle
-  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to 
-  *         transfer the updated data to the second level buffer. 
-  *         The UDR bit stays set until the end of the update and during this 
-  *         time the LCD_RAM is write protected. 
-  * @note   When the display is disabled, the update is performed for all 
-  *         LCD_DISPLAY locations.
-  *         When the display is enabled, the update is performed only for locations 
-  *         for which commons are active (depending on DUTY). For example if 
-  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.    
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00;
-  
-  /* Clear the Update Display Done flag before starting the update display request */
-  __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
-  
-  /* Enable the display request */
-  hlcd->Instance->SR |= LCD_SR_UDR;
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD display is done */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hlcd);
-  
-      return HAL_TIMEOUT;
-    }
-  }
-
-  hlcd->State = HAL_LCD_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods 
-  *  @brief   LCD State functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-     This subsection provides a set of functions allowing to control the LCD:
-      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. 
-      (+) HAL_LCD_GetError() API to return the LCD error code. 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Returns the LCD state.
-  * @param hlcd: LCD handle
-  * @retval HAL state
-  */
-HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->State;
-}
-
-/**
-  * @brief Return the LCD error code
-  * @param hlcd: LCD handle
-  * @retval LCD Error Code
-  */
-uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Private_Functions LCD Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
-  *   This function must be called after any write operation to LCD_FCR register.
-  * @retval None
-  */
-HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00; 
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-
-  /* Loop until FCRSF flag is set */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    {
-      hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE || STM32L162xDX */
-
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_msp_template.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_msp_template.c
deleted file mode 100644
index 15c142d7076..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_msp_template.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_msp_template.c
-  * @author  MCD Application Team
-  * @brief   HAL MSP module.
-  *          This file template is located in the HAL folder and should be copied
-  *          to the user folder.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL_MSP HAL_MSP
-  * @brief HAL MSP module.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the Global MSP.
-  * @retval None
-  */
-void HAL_MspInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually
-            modified by the user
-   */
-}
-
-/**
-  * @brief  DeInitializes the Global MSP.
-  * @retval None
-  */
-void HAL_MspDeInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually
-            modified by the user
-   */
-}
-
-/**
-  * @brief  Initializes the PPP MSP.
-  * @retval None
-  */
-void HAL_PPP_MspInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually
-            modified by the user
-   */
-}
-
-/**
-  * @brief  DeInitializes the PPP MSP.
-  * @retval None
-  */
-void HAL_PPP_MspDeInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually
-            modified by the user
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c
deleted file mode 100644
index 2cc0aed8032..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c
+++ /dev/null
@@ -1,1512 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_nor.c
-  * @author  MCD Application Team
-  * @brief   NOR HAL module driver.
-  *          This file provides a generic firmware to drive NOR memories mounted
-  *          as external device.
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a generic layered driver which contains a set of APIs used to
-      control NOR flash memories. It uses the FSMC layer functions to interface
-      with NOR devices. This driver is used as follows:
-
-      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
-          with control and timing parameters for both normal and extended mode.
-
-      (+) Read NOR flash memory manufacturer code and device IDs using the function
-          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
-          structure declared by the function caller.
-
-      (+) Access NOR flash memory by read/write data unit operations using the functions
-          HAL_NOR_Read(), HAL_NOR_Program().
-
-      (+) Perform NOR flash erase block/chip operations using the functions
-          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-
-      (+) Read the NOR flash CFI (common flash interface) IDs using the function
-          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
-          structure declared by the function caller.
-
-      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
-          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
-
-      (+) You can monitor the NOR device HAL state by calling the function
-          HAL_NOR_GetState()
-    [..]
-     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
-         If a NOR flash device contains different operations and/or implementations,
-         it should be implemented separately.
-
-     *** NOR HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in NOR HAL driver.
-
-      (+) NOR_WRITE : NOR memory write data to specified address
-
-    *** Callback registration ***
-    =============================================
-    [..]
-      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-      Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
-      it allows to register following callbacks:
-        (+) MspInitCallback    : NOR MspInit.
-        (+) MspDeInitCallback  : NOR MspDeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-      Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
-        (+) MspInitCallback    : NOR MspInit.
-        (+) MspDeInitCallback  : NOR MspDeInit.
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-      By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-      Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
-      and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-      Callbacks can be registered/unregistered in READY state only.
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-      during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
-      or @ref HAL_NOR_Init function.
-
-      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#if defined(FSMC_BANK1)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-
-/** @defgroup NOR NOR
-  * @brief NOR driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Defines NOR Private Defines
-  * @{
-  */
-
-/* Constants to define address to set to write a command */
-#define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
-#define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
-
-/* Constants to define data to program a command */
-#define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
-#define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
-#define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
-#define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
-#define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
-#define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
-#define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
-
-#define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
-#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
-#define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
-
-#define NOR_CMD_READ_ARRAY                    (uint16_t)0x00FF
-#define NOR_CMD_WORD_PROGRAM                  (uint16_t)0x0040
-#define NOR_CMD_BUFFERED_PROGRAM              (uint16_t)0x00E8
-#define NOR_CMD_CONFIRM                       (uint16_t)0x00D0
-#define NOR_CMD_BLOCK_ERASE                   (uint16_t)0x0020
-#define NOR_CMD_BLOCK_UNLOCK                  (uint16_t)0x0060
-#define NOR_CMD_READ_STATUS_REG               (uint16_t)0x0070
-#define NOR_CMD_CLEAR_STATUS_REG              (uint16_t)0x0050
-
-/* Mask on NOR STATUS REGISTER */
-#define NOR_MASK_STATUS_DQ4                   (uint16_t)0x0010
-#define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
-#define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
-#define NOR_MASK_STATUS_DQ7                   (uint16_t)0x0080
-
-/* Address of the primary command set */
-#define NOR_ADDRESS_COMMAND_SET               (uint16_t)0x0013
-
-/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
-#define NOR_INTEL_SHARP_EXT_COMMAND_SET       (uint16_t)0x0001 /* Supported in this driver */
-#define NOR_AMD_FUJITSU_COMMAND_SET           (uint16_t)0x0002 /* Supported in this driver */
-#define NOR_INTEL_STANDARD_COMMAND_SET        (uint16_t)0x0003 /* Not Supported in this driver */
-#define NOR_AMD_FUJITSU_EXT_COMMAND_SET       (uint16_t)0x0004 /* Not Supported in this driver */
-#define NOR_WINDBOND_STANDARD_COMMAND_SET     (uint16_t)0x0006 /* Not Supported in this driver */
-#define NOR_MITSUBISHI_STANDARD_COMMAND_SET   (uint16_t)0x0100 /* Not Supported in this driver */
-#define NOR_MITSUBISHI_EXT_COMMAND_SET        (uint16_t)0x0101 /* Not Supported in this driver */
-#define NOR_PAGE_WRITE_COMMAND_SET            (uint16_t)0x0102 /* Not Supported in this driver */
-#define NOR_INTEL_PERFORMANCE_COMMAND_SET     (uint16_t)0x0200 /* Not Supported in this driver */
-#define NOR_INTEL_DATA_COMMAND_SET            (uint16_t)0x0210 /* Not Supported in this driver */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup NOR_Private_Variables NOR Private Variables
-  * @{
-  */
-
-static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup NOR_Exported_Functions NOR Exported Functions
-  * @{
-  */
-
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-  @verbatim
-  ==============================================================================
-           ##### NOR Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to initialize/de-initialize
-    the NOR memory
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Perform the NOR memory Initialization sequence
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Timing pointer to NOR control timing structure
-  * @param  ExtTiming pointer to NOR extended mode timing structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
-                               FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
-  uint32_t deviceaddress;
-
-  /* Check the NOR handle parameter */
-  if (hnor == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if (hnor->State == HAL_NOR_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hnor->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-    if (hnor->MspInitCallback == NULL)
-    {
-      hnor->MspInitCallback = HAL_NOR_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hnor->MspInitCallback(hnor);
-#else
-    /* Initialize the low level hardware (MSP) */
-    HAL_NOR_MspInit(hnor);
-#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
-  }
-
-  /* Initialize NOR control Interface */
-  (void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
-
-  /* Initialize NOR timing Interface */
-  (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
-
-  /* Initialize NOR extended mode timing Interface */
-  (void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
-
-  /* Enable the NORSRAM device */
-  __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
-
-  /* Initialize NOR Memory Data Width*/
-  if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
-  {
-    uwNORMemoryDataWidth = NOR_MEMORY_8B;
-  }
-  else
-  {
-    uwNORMemoryDataWidth = NOR_MEMORY_16B;
-  }
-
-  /* Initialize the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
-  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-
-  /* Get the value of the command set */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-  hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
-
-  return HAL_NOR_ReturnToReadMode(hnor);
-}
-
-/**
-  * @brief  Perform NOR memory De-Initialization sequence
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
-{
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-  if (hnor->MspDeInitCallback == NULL)
-  {
-    hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
-  }
-
-  /* DeInit the low level hardware */
-  hnor->MspDeInitCallback(hnor);
-#else
-  /* De-Initialize the low level hardware (MSP) */
-  HAL_NOR_MspDeInit(hnor);
-#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
-
-  /* Configure the NOR registers with their reset values */
-  (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-
-  /* Reset the NOR controller state */
-  hnor->State = HAL_NOR_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  NOR MSP Init
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval None
-  */
-__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hnor);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  NOR MSP DeInit
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval None
-  */
-__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hnor);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  NOR MSP Wait for Ready/Busy signal
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Timeout Maximum timeout value
-  * @retval None
-  */
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hnor);
-  UNUSED(Timeout);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_MspWait could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
-  * @brief    Input Output and memory control functions
-  *
-  @verbatim
-  ==============================================================================
-                ##### NOR Input and Output functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to use and control the NOR memory
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read NOR flash IDs
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pNOR_ID  pointer to NOR ID structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
-{
-  uint32_t deviceaddress;
-  HAL_NOR_StateTypeDef state;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  state = hnor->State;
-  if (state == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send read ID command */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_ERROR)
-    {
-      /* Read the NOR IDs */
-      pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
-      pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
-                                                                     DEVICE_CODE1_ADDR);
-      pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
-                                                                     DEVICE_CODE2_ADDR);
-      pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
-                                                                     DEVICE_CODE3_ADDR);
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Returns the NOR memory to Read mode.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
-{
-  uint32_t deviceaddress;
-  HAL_NOR_StateTypeDef state;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  state = hnor->State;
-  if (state == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Read data from NOR memory
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pAddress pointer to Device address
-  * @param  pData  pointer to read data
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
-  uint32_t deviceaddress;
-  HAL_NOR_StateTypeDef state;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  state = hnor->State;
-  if (state == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send read data command */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_ERROR)
-    {
-      /* Read the data */
-      *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Program data to NOR memory
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pAddress Device address
-  * @param  pData  pointer to the data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
-  uint32_t deviceaddress;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (hnor->State == HAL_NOR_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send program data command */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_ERROR)
-    {
-      /* Write the data */
-      NOR_WRITE(pAddress, *pData);
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = HAL_NOR_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Reads a half-word buffer from the NOR memory.
-  * @param  hnor pointer to the NOR handle
-  * @param  uwAddress NOR memory internal address to read from.
-  * @param  pData pointer to the buffer that receives the data read from the
-  *         NOR memory.
-  * @param  uwBufferSize  number of Half word to read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
-                                     uint32_t uwBufferSize)
-{
-  uint32_t deviceaddress;
-  uint32_t size = uwBufferSize;
-  uint32_t address = uwAddress;
-  uint16_t *data = pData;
-  HAL_NOR_StateTypeDef state;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  state = hnor->State;
-  if (state == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send read data command */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_ERROR)
-    {
-      /* Read buffer */
-      while (size > 0U)
-      {
-        *data = *(__IO uint16_t *)address;
-        data++;
-        address += 2U;
-        size--;
-      }
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Writes a half-word buffer to the NOR memory. This function must be used
-            only with S29GL128P NOR memory.
-  * @param  hnor pointer to the NOR handle
-  * @param  uwAddress NOR memory internal start write address
-  * @param  pData pointer to source data buffer.
-  * @param  uwBufferSize Size of the buffer to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
-                                        uint32_t uwBufferSize)
-{
-  uint16_t *p_currentaddress;
-  const uint16_t *p_endaddress;
-  uint16_t *data = pData;
-  uint32_t deviceaddress;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (hnor->State == HAL_NOR_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Initialize variables */
-    p_currentaddress  = (uint16_t *)(deviceaddress + uwAddress);
-    p_endaddress      = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
-
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      /* Issue unlock command sequence */
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
-      /* Write Buffer Load Command */
-      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
-      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      /* Write Buffer Load Command */
-      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
-      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    if (status != HAL_ERROR)
-    {
-      /* Load Data into NOR Buffer */
-      while (p_currentaddress <= p_endaddress)
-      {
-        NOR_WRITE(p_currentaddress, *data);
-
-        data++;
-        p_currentaddress ++;
-      }
-
-      if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-      {
-        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-      }
-      else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
-      {
-        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
-      }
-    }
-
-    /* Check the NOR controller state */
-    hnor->State = HAL_NOR_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-
-}
-
-/**
-  * @brief  Erase the specified block of the NOR memory
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  BlockAddress  Block to erase address
-  * @param  Address Device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
-{
-  uint32_t deviceaddress;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (hnor->State == HAL_NOR_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send block erase command sequence */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-      NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
-    }
-    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-    {
-      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
-      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
-      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
-      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    /* Check the NOR memory status and update the controller state */
-    hnor->State = HAL_NOR_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-
-}
-
-/**
-  * @brief  Erase the entire NOR chip.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Address  Device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
-{
-  uint32_t deviceaddress;
-  HAL_StatusTypeDef status = HAL_OK;
-  UNUSED(Address);
-
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (hnor->State == HAL_NOR_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send NOR chip erase command sequence */
-    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-    {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-    }
-    else
-    {
-      /* Primary command set not supported by the driver */
-      status = HAL_ERROR;
-    }
-
-    /* Check the NOR memory status and update the controller state */
-    hnor->State = HAL_NOR_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Read NOR flash CFI IDs
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pNOR_CFI  pointer to NOR CFI IDs structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
-{
-  uint32_t deviceaddress;
-  HAL_NOR_StateTypeDef state;
-
-  /* Check the NOR controller state */
-  state = hnor->State;
-  if (state == HAL_NOR_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Select the NOR device address */
-    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS1;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS2;
-    }
-    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-    {
-      deviceaddress = NOR_MEMORY_ADRESS3;
-    }
-    else /* FSMC_NORSRAM_BANK4 */
-    {
-      deviceaddress = NOR_MEMORY_ADRESS4;
-    }
-
-    /* Send read CFI query command */
-    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
-    /* read the NOR CFI information */
-    pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
-    pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
-    pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
-    pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
-
-    /* Check the NOR controller state */
-    hnor->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User NOR Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hnor : NOR handle
-  * @param CallbackId : ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
-  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
-  * @param pCallback : pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
-                                           pNOR_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_NOR_StateTypeDef state;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hnor);
-
-  state = hnor->State;
-  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    switch (CallbackId)
-    {
-      case HAL_NOR_MSP_INIT_CB_ID :
-        hnor->MspInitCallback = pCallback;
-        break;
-      case HAL_NOR_MSP_DEINIT_CB_ID :
-        hnor->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User NOR Callback
-  *         NOR Callback is redirected to the weak (surcharged) predefined callback
-  * @param hnor : NOR handle
-  * @param CallbackId : ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
-  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_NOR_StateTypeDef state;
-
-  /* Process locked */
-  __HAL_LOCK(hnor);
-
-  state = hnor->State;
-  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
-  {
-    switch (CallbackId)
-    {
-      case HAL_NOR_MSP_INIT_CB_ID :
-        hnor->MspInitCallback = HAL_NOR_MspInit;
-        break;
-      case HAL_NOR_MSP_DEINIT_CB_ID :
-        hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
-  return status;
-}
-#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
-
-/**
-  * @}
-  */
-
-/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
-  *  @brief   management functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### NOR Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the NOR interface.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables dynamically NOR write operation.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
-{
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_PROTECTED)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Enable write operation */
-    (void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables dynamically NOR write operation.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
-{
-  /* Check the NOR controller state */
-  if (hnor->State == HAL_NOR_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hnor);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_BUSY;
-
-    /* Disable write operation */
-    (void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
-
-    /* Update the NOR controller state */
-    hnor->State = HAL_NOR_STATE_PROTECTED;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hnor);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### NOR State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in run-time the status of the NOR controller
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the NOR controller state
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval NOR controller state
-  */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
-{
-  return hnor->State;
-}
-
-/**
-  * @brief  Returns the NOR operation status.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Address Device address
-  * @param  Timeout NOR programming Timeout
-  * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
-  *         or HAL_NOR_STATUS_TIMEOUT
-  */
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{
-  HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
-  uint16_t tmpsr1;
-  uint16_t tmpsr2;
-  uint32_t tickstart;
-
-  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
-  HAL_NOR_MspWait(hnor, Timeout);
-
-  /* Get the NOR memory operation status -------------------------------------*/
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
-  {
-    while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
-    {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          status = HAL_NOR_STATUS_TIMEOUT;
-        }
-      }
-
-      /* Read NOR status register (DQ6 and DQ5) */
-      tmpsr1 = *(__IO uint16_t *)Address;
-      tmpsr2 = *(__IO uint16_t *)Address;
-
-      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
-      {
-        return HAL_NOR_STATUS_SUCCESS ;
-      }
-
-      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
-      {
-        status = HAL_NOR_STATUS_ONGOING;
-      }
-
-      tmpsr1 = *(__IO uint16_t *)Address;
-      tmpsr2 = *(__IO uint16_t *)Address;
-
-      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
-      {
-        return HAL_NOR_STATUS_SUCCESS;
-      }
-      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
-      {
-        return HAL_NOR_STATUS_ERROR;
-      }
-    }
-  }
-  else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
-  {
-    do
-    {
-      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
-      tmpsr2 = *(__IO uint16_t *)(Address);
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          return HAL_NOR_STATUS_TIMEOUT;
-        }
-      }
-    } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
-
-    NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
-    tmpsr1 = *(__IO uint16_t *)(Address);
-    if ((tmpsr1  & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
-    {
-      /* Clear the Status Register  */
-      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
-      status = HAL_NOR_STATUS_ERROR;
-    }
-    else
-    {
-      status = HAL_NOR_STATUS_SUCCESS;
-    }
-  }
-  else
-  {
-    /* Primary command set not supported by the driver */
-    status = HAL_NOR_STATUS_ERROR;
-  }
-
-  /* Return the operation status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-#endif /* FSMC_BANK1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c
deleted file mode 100644
index 3610f55cc99..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp.c
+++ /dev/null
@@ -1,1282 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp.c
-  * @author  MCD Application Team
-  * @brief   OPAMP HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the operational amplifier(s) peripheral:
-  *           + OPAMP configuration
-  *           + OPAMP calibration
-  *          Thanks to
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *         
-  @verbatim
-================================================================================
-          ##### OPAMP Peripheral Features #####
-================================================================================
-  [..] The device integrates up to 3 operational amplifiers OPAMP1, OPAMP2,
-       OPAMP3 (OPAMP3 availability depends on device category)
-       
-       (#) The OPAMP(s) provide(s) several exclusive running modes.
-       (++) Standalone mode
-       (++) Follower mode
-
-       (#) All OPAMP (same for all OPAMPs) can operate in
-       (++) Either Low range (VDDA < 2.4V) power supply
-       (++) Or High range (VDDA > 2.4V) power supply
-
-       (#) Each OPAMP(s) can be configured in normal and low power mode.
-
-       (#) The OPAMP(s) provide(s) calibration capabilities.  
-       (++) Calibration aims at correcting some offset for running mode.
-       (++) The OPAMP uses either factory calibration settings OR user defined 
-           calibration (trimming) settings (i.e. trimming mode).
-       (++) The user defined settings can be figured out using self calibration 
-           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
-       (++) HAL_OPAMP_SelfCalibrate:
-       (+++) Runs automatically the calibration in 2 steps: for transistors 
-            differential pair high (PMOS) or low (NMOS)
-       (+++) Enables the user trimming mode
-       (+++) Updates the init structure with trimming values with fresh calibration 
-            results.
-            The user may store the calibration results for larger 
-            (ex monitoring the trimming as a function of temperature 
-            for instance)
-       (+++) For devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll
-            runs calibration of all OPAMPs in parallel to save search time.
-            
-       (#) Running mode: Standalone mode 
-       (++) Gain is set externally (gain depends on external loads).
-       (++) Follower mode also possible externally by connecting the inverting input to
-           the output.
-       
-       (#) Running mode: Follower mode
-       (++) No Inverting Input is connected.
-       (++) The OPAMP(s) output(s) are internally connected to inverting input.
-        
-            ##### How to use this driver #####
-================================================================================
-  [..] 
-
-    *** Power supply range ***
-    ============================================
-    [..] To run in low power mode:
-
-      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
-      (++) Select OPAMP_POWERSUPPLY_LOW (VDDA lower than 2.4V)
-      (++) Otherwise select OPAMP_POWERSUPPLY_HIGH (VDDA higher than 2.4V)
-
-    *** Low / normal power mode ***
-    ============================================
-    [..] To run in low power mode:
-
-      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
-      (++) Select OPAMP_POWERMODE_LOWPOWER
-      (++) Otherwise select OPAMP_POWERMODE_NORMAL
-
-    *** Calibration ***
-    ============================================
-    [..] To run the OPAMP calibration self calibration:
-
-      (#) Start calibration using HAL_OPAMP_SelfCalibrate. 
-           Store the calibration results.
-
-    *** Running mode ***
-    ============================================
-      
-    [..] To use the OPAMP, perform the following steps:
-            
-      (#) Fill in the HAL_OPAMP_MspInit() to
-      (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
-      (++) Configure the OPAMP input AND output in analog mode using
-           HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
-
-      (#) Registrate Callbacks
-      (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
-           allows the user to configure dynamically the driver callbacks.
-
-      (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
-           it allows to register following callbacks:
-      (+++) MspInitCallback         : OPAMP MspInit.
-      (+++) MspDeInitCallback       : OPAMP MspFeInit.
-           This function takes as parameters the HAL peripheral handle, the Callback ID
-           and a pointer to the user callback function.
-
-      (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
-           weak (surcharged) function. It allows to reset following callbacks:
-      (+++) MspInitCallback         : OPAMP MspInit.
-      (+++) MspDeInitCallback       : OPAMP MspdeInit.
-      (+++) All Callbacks
-  
-      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
-      (++) Select the mode
-      (++) Select the inverting input
-      (++) Select the non-inverting input 
-      (++) Select either factory or user defined trimming mode.
-      (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
-          (typically values set by HAL_OPAMP_SelfCalibrate function).
-      
-      (#) Enable the OPAMP using HAL_OPAMP_Start() function.
-           
-      (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
-      
-      (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
-          Caution: On STM32L1, HAL OPAMP lock is software lock only (not 
-          hardware lock as on some other STM32 devices)
-
-      (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
-
-    *** Running mode: change of configuration while OPAMP ON  ***
-    ============================================
-    [..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
-      (#) If needed, fill in the HAL_OPAMP_MspInit()
-      (++) This is the case for instance if you wish to use new OPAMP I/O
-
-      (#) Configure the OPAMP using HAL_OPAMP_Init() function:
-      (++) As in configure case, select first the parameters you wish to modify.
-      
-      (#) Change from low power mode to normal power mode (& vice versa) requires  
-          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). 
-          In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
-          alone.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************  
-  */
-
-/*
-  Additionnal remark:
-    The OPAMPs inverting input can be selected among the list shown by table below.
-    The OPAMPs non inverting input can be selected among the list shown by table below.
-       
-    Table 1.  OPAMPs inverting/non-inverting inputs for STM32L1 devices:
-    +--------------------------------------------------------------------------+
-    |                | HAL param  |    OPAMP1    |    OPAMP2    |   OPAMP3(4)  |
-    |                |   name     |              |              |              |
-    |----------------|------------|--------------|--------------|--------------|
-    |   Inverting    |    VM0     |     PA2      |     PA7      |     PC2      |
-    |    input (1)   |    VM1     | VINM pin (2) | VINM pin (2) | VINM pin (2) |
-    |----------------|------------|--------------|--------------|--------------|
-    |  Non Inverting |    VP0     |     PA1      |     PA6      |     PC1      |
-    |    input       | DAC_CH1 (3)|   DAC_CH1    |   DAC_CH1    |     ---      |
-    |                | DAC_CH2 (3)|     ---      |   DAC_CH2    |   DAC_CH2    |
-    +--------------------------------------------------------------------------+
-    (1): NA in follower mode.
-    (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability
-         depends on device package.
-    (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless,
-         I/O pins connected to DAC can still be used as DAC output (pins PA4 
-         and PA5).
-    (4): OPAMP3 availability depends on device category.
-
-    Table 2.  OPAMPs outputs for STM32L1 devices:
-    +--------------------------------------------------------+
-    |                 |   OPAMP1   |   OPAMP2   |  OPAMP3(4) |
-    |-----------------|------------|------------|------------|
-    | Output          |    PA3     |    PB0     |    PC3     |
-    +--------------------------------------------------------+
-    (4) : OPAMP3 availability depends on device category
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-    
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup OPAMP OPAMP
-  * @brief OPAMP module driver
-  * @{
-  */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
-  * @{
-  */
-
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-   [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the OPAMP according to the specified
-  *         parameters in the OPAMP_InitTypeDef and create the associated handle.
-  * @note   If the selected opamp is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp_csr;       /* Temporary variable to update register CSR, except bits ANAWSSELx, S7SEL2, OPA_RANGE, OPAxCALOUT */
-  
-  /* Check the OPAMP handle allocation and lock status */
-  /* Init not allowed if calibration is ongoing */
-  if(hopamp == NULL)
-  {
-    return HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-  {
-    return HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-       
-    /* Set OPAMP parameters */
-    assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange));
-    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-    assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
-    assert_param(IS_OPAMP_NONINVERTING_INPUT_CHECK_INSTANCE(hopamp, hopamp->Init.NonInvertingInput));
-    assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
-
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-    if(hopamp->State == HAL_OPAMP_STATE_RESET)
-    {
-      if(hopamp->MspInitCallback == NULL)
-      {
-        hopamp->MspInitCallback               = HAL_OPAMP_MspInit;
-      }
-    }
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-    if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE)
-    {
-      assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
-    }
-    
-    if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-    {
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
-      }
-      else
-      {
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
-      }
-    }
-    
-    if(hopamp->State == HAL_OPAMP_STATE_RESET)
-    {
-      /* Allocate lock resource and initialize it */
-      hopamp->Lock = HAL_UNLOCKED;
-    }
-
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-    hopamp->MspInitCallback(hopamp);    
-#else
-    /* Call MSP init function */
-    HAL_OPAMP_MspInit(hopamp);
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-    /* Set OPAMP parameters                                                   */
-    /* - Set internal switches in function of:                                */
-    /*   - OPAMP selected mode: standalone or follower.                       */
-    /*   - Non-inverting input connection                                     */
-    /*   - Inverting input connection                                         */
-    /* - Set power supply range                                               */
-    /* - Set power mode and associated calibration parameters                 */
-    
-    /* Get OPAMP CSR register into temporary variable */
-    /* Note: OPAMP register CSR is written directly, independently of OPAMP   */
-    /*       instance, because all OPAMP settings are dispatched in the same  */
-    /*       register.                                                        */
-    /*       Settings of bits for each OPAMP instances are managed case by    */
-    /*       case using macro (OPAMP_CSR_S3SELX(), OPAMP_CSR_ANAWSELX(), ...) */
-    tmp_csr = OPAMP->CSR;
-    
-    /* Open all switches on non-inverting input, inverting input and output   */
-    /* feedback.                                                              */
-    CLEAR_BIT(tmp_csr, OPAMP_CSR_ALL_SWITCHES(hopamp));
-    
-    /* Set internal switches in function of OPAMP mode selected: standalone   */
-    /* or follower.                                                           */
-    /* If follower mode is selected, feedback switch S3 is closed and         */
-    /* inverting inputs switches are let opened.                              */
-    /* If standalone mode is selected, feedback switch S3 is let opened and   */
-    /* the selected inverting inputs switch is closed.                        */
-    if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
-    {
-      /* Follower mode: Close switches S3 and SanB */
-      SET_BIT(tmp_csr, OPAMP_CSR_S3SELX(hopamp));
-    }
-    else
-    {
-      /* Set internal switches in function of inverting input selected:       */
-      /* Close switch to connect OPAMP inverting input to the selected        */
-      /* input: dedicated IO pin or alternative IO pin available on some      */
-      /* device packages.                                                     */
-      if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_IO0)
-      {
-        /* Close switch to connect OPAMP non-inverting input to               */
-        /* dedicated IO pin low-leakage.                                      */
-        SET_BIT(tmp_csr, OPAMP_CSR_S4SELX(hopamp));
-      }
-      else
-      {
-        /* Close switch to connect OPAMP inverting input to alternative       */
-        /* IO pin available on some device packages.                          */
-        SET_BIT(tmp_csr, OPAMP_CSR_ANAWSELX(hopamp));
-      }
-    }
-    
-    /* Set internal switches in function of non-inverting input selected:     */
-    /* Close switch to connect OPAMP non-inverting input to the selected      */
-    /* input: dedicated IO pin or DAC channel.                                */
-    if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_IO0)
-    {
-      /* Close switch to connect OPAMP non-inverting input to                 */
-      /* dedicated IO pin low-leakage.                                        */
-      SET_BIT(tmp_csr, OPAMP_CSR_S5SELX(hopamp));
-    }
-    else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1)
-    {
-      
-      /* Particular case for connection to DAC channel 1:                     */
-      /* OPAMP_NONINVERTINGINPUT_DAC_CH1 available on OPAMP1 and OPAMP2 only  */
-      /* (OPAMP3 availability depends on device category).                    */
-      if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2))
-      {
-        /* Close switch to connect OPAMP non-inverting input to               */
-        /* DAC channel 1.                                                     */
-        SET_BIT(tmp_csr, OPAMP_CSR_S6SELX(hopamp));
-      }
-      else
-      {
-        /* Set HAL status to error if another OPAMP instance as OPAMP1 or     */
-        /* OPAMP2 is intended to be connected to DAC channel 2.               */
-        status = HAL_ERROR;
-      }
-    }
-    else /* if (hopamp->Init.NonInvertingInput ==                             */
-         /*     OPAMP_NONINVERTINGINPUT_DAC_CH2  )                            */
-    {
-      /* Particular case for connection to DAC channel 2:                     */
-      /* OPAMP_NONINVERTINGINPUT_DAC_CH2 available on OPAMP2 and OPAMP3 only  */
-      /* (OPAMP3 availability depends on device category).                    */
-      if (hopamp->Instance == OPAMP2)
-      {
-        /* Close switch to connect OPAMP non-inverting input to               */
-        /* DAC channel 2.                                                     */
-        SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2);
-      }
-      /* If OPAMP3 is selected (if available) */
-      else if (hopamp->Instance != OPAMP1)
-      {
-        /* Close switch to connect OPAMP non-inverting input to               */
-        /* DAC channel 2.                                                     */
-        SET_BIT(tmp_csr, OPAMP_CSR_S6SELX(hopamp));
-      }
-      else
-      {
-        /* Set HAL status to error if another OPAMP instance as OPAMP2 or     */
-        /* OPAMP3 (if available) is intended to be connected to DAC channel 2.*/
-        status = HAL_ERROR;
-      }
-    }
-    
-    /* Continue OPAMP configuration if settings of switches are correct */
-    if (status != HAL_ERROR)
-    {
-      /* Set power mode and associated calibration parameters */
-      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Set normal mode */
-        CLEAR_BIT(tmp_csr, OPAMP_CSR_OPAXLPM(hopamp));
-        
-        if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-        {
-          /* Set calibration mode (factory or user) and values for            */
-          /* transistors differential pair high (PMOS) and low (NMOS) for     */
-          /* normal mode.                                                     */
-          MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER                                                                     |
-                                 OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK)       |
-                                 OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK)        ,
-                                 hopamp->Init.UserTrimming                                                             |
-                                 OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) |
-                                 OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP)  );
-        }
-        else
-        {
-          /* Set calibration mode to factory */
-          CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-        }
-        
-      }
-      else
-      {
-        /* Set low power mode */
-        SET_BIT(tmp_csr, OPAMP_CSR_OPAXLPM(hopamp));
-        
-        if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-        {
-          /* Set calibration mode to user trimming */
-          SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-          
-          /* Set values for transistors differential pair high (PMOS) and low */
-          /* (NMOS) for low power mode.                                       */
-          MODIFY_REG(OPAMP->LPOTR, OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK)               |
-                                   OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK)                ,
-                                   OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) |
-                                   OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower)  );
-        }
-        else
-        {
-          /* Set calibration mode to factory trimming */
-          CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-        }
-        
-      }
-      
-      
-      /* Configure the power supply range */
-      MODIFY_REG(tmp_csr, OPAMP_CSR_AOP_RANGE,
-                          hopamp->Init.PowerSupplyRange);
-      
-      /* Set OPAMP CSR register from temporary variable */
-      /* This allows to apply all changes on one time, in case of update on   */
-      /* the fly with OPAMP previously set and running:                       */
-      /*  - to avoid hazardous transient switches settings (risk of short     */
-      /*    circuit)                                                          */
-      /*  - to avoid interruption of input signal                             */
-      OPAMP->CSR = tmp_csr;
-
-                
-      /* Update the OPAMP state */
-      /* If coming from state reset: Update from state RESET to state READY */
-      if (hopamp->State == HAL_OPAMP_STATE_RESET)
-      {
-        hopamp->State = HAL_OPAMP_STATE_READY;
-      }
-      /* else: OPAMP state remains READY or BUSY state (no update) */
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  DeInitializes the OPAMP peripheral 
-  * @note   Deinitialization can be performed if the OPAMP configuration is locked.
-  *         (the OPAMP lock is SW in STM32L1)
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the OPAMP handle allocation */
-  /* DeInit not allowed if calibration is ongoing */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
-    /* Disable the selected opamp */
-    SET_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp));
-    
-    /* Open all switches on non-inverting input, inverting input and output   */
-    /* feedback.                                                              */
-    /* Note: OPAMP register CSR is written directly, independently of OPAMP   */
-    /*       instance, because all OPAMP settings are dispatched in the same  */
-    /*       register.                                                        */
-    /*       Settings of bits for each OPAMP instances are managed case by    */
-    /*       case using macro (OPAMP_CSR_S3SELX(), OPAMP_CSR_ANAWSELX(), ...) */
-    CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp));
-
-    /* Note: Registers and bits shared with other OPAMP instances are kept    */
-    /*       unchanged, to not impact other OPAMP while operating on the      */
-    /*       selected OPAMP.                                                  */
-    /*       Unchanged: bit OPAMP_OTR_OT_USER (parameter "UserTrimming")      */
-    /*                  bit OPAMP_CSR_AOP_RANGE (parameter "PowerSupplyRange")*/
-
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-  if(hopamp->MspDeInitCallback == NULL)
-  {
-    hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hopamp->MspDeInitCallback(hopamp);
-#else
-    /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
-    HAL_OPAMP_MspDeInit(hopamp);
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-    /* Update the OPAMP state*/
-    hopamp->State = HAL_OPAMP_STATE_RESET;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hopamp);
-  
-  return status;
-}
-
-/**
-  * @brief  Initialize the OPAMP MSP.
-  * @param  hopamp OPAMP handle
-  * @retval None
-  */
-__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hopamp);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  DeInitialize OPAMP MSP.
-  * @param  hopamp OPAMP handle
-  * @retval None
-  */
-__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hopamp);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
-  */
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions 
-  * @brief   IO operation functions 
-  *
-@verbatim   
- ===============================================================================
-                        ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the OPAMP
-    start, stop and calibration actions.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the OPAMP.
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
-    if(hopamp->State == HAL_OPAMP_STATE_READY)
-    {
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp));
-      
-      /* Update the OPAMP state */
-      /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
-      hopamp->State = HAL_OPAMP_STATE_BUSY;   
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-    
-   }
-  return status;
-}
-
-/**
-  * @brief  Stop the OPAMP.
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-    
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  /* Check if OPAMP calibration ongoing */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
-    if(hopamp->State == HAL_OPAMP_STATE_BUSY)
-    {
-      /* Disable the selected opamp */
-      SET_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp));
-      
-      /* Update the OPAMP state*/     
-      /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
-      hopamp->State = HAL_OPAMP_STATE_READY;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Run the self calibration of one OPAMP.
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled if calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms.
-  * @param  hopamp handle
-  * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp_trimmingvalue;
-  uint32_t opamp_trimmingvaluen = 0;
-  uint32_t opamp_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair;               /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp_reg_trimming;     /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  uint32_t tmp_opamp_otr_otuser;             /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-
-  uint32_t tmp_Opaxcalout_DefaultSate;       /* Bit OPAMP_CSR_OPAXCALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup;
-  
-  uint8_t trimming_diff_pair_iteration_count;          /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */
-  uint8_t delta;                                       /* For calibration loop algorithm: Variable for dichotomy steps value */
-  uint8_t final_step_check = 0x0U;                        /* For calibration loop algorithm: Flag for additional check of last trimming step */
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-  
-    /* Check if OPAMP in calibration mode and calibration not yet enable */
-    if(hopamp->State == HAL_OPAMP_STATE_READY)
-    {
-      /* Check the parameter */
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-      assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-      
-      /* Update OPAMP state */
-      hopamp->State = HAL_OPAMP_STATE_CALIBBUSY;
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp));
-  
-      /* Open all switches on non-inverting input, inverting input and output */
-      /* feedback.                                                            */
-      CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES(hopamp));
-
-      /* Set calibration mode to user programmed trimming values */
-      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-
-      
-      /* Select trimming settings depending on power mode */
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp_otr_otuser = 0x00000000U;
-        tmp_opamp_reg_trimming = &OPAMP->LPOTR;
-      }
-
-      
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD(hopamp));
-
-      /* Perform trimming for both differential transistors pair high and low */
-      for (trimming_diff_pair_iteration_count = 0U; trimming_diff_pair_iteration_count <=1U; trimming_diff_pair_iteration_count++)
-      {
-        if (trimming_diff_pair_iteration_count == 0U)
-        {
-          /* Calibration of transistors differential pair high (NMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-          opamp_trimmingvalue = &opamp_trimmingvaluen;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opaxcalout_DefaultSate = 0U;
-
-          /* Enable calibration for N differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L(hopamp),
-                                 OPAMP_CSR_OPAXCAL_H(hopamp) );
-        }
-        else /* (trimming_diff_pair_iteration_count == 1) */
-        {
-          /* Calibration of transistors differential pair low (PMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-          opamp_trimmingvalue = &opamp_trimmingvaluep;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opaxcalout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp);
-          
-          /* Enable calibration for P differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H(hopamp),
-                                 OPAMP_CSR_OPAXCAL_L(hopamp) );
-        }
-        
-      
-        /* Perform calibration parameter search by dichotomy sweep */
-        /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-        /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-        /*    can extend the search range to +/- 15 units.                    */
-        /*  - Trimming initial value 15: search range will go from 0 to 30    */
-        /*    (Trimming value 31 is forbidden).                               */
-        /* Note: After dichotomy sweep, the trimming result is determined.    */
-        /*       However, the final trimming step is deduced from previous    */
-        /*       trimming steps tested but is not effectively tested.         */
-        /*       An additional test step (using variable "final_step_check")  */
-        /*       allow to Test the final trimming step.                       */
-        *opamp_trimmingvalue = 15U;
-        delta = 16U;
-
-        while ((delta != 0U) || (final_step_check == 1U))
-        {
-          /* Set candidate trimming */
-          MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                              OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser);
-          
-          /* Offset trimming time: during calibration, minimum time needed    */
-          /* between two steps to have 1 mV accuracy.                         */
-          HAL_Delay(OPAMP_TRIMMING_DELAY);
-
-          /* Set flag for additional check of last trimming step equal to     */
-          /* dichotomy step before its division by 2 (equivalent to previous  */
-          /* value of dichotomy step).                                        */
-          final_step_check = delta;
-          
-          /* Divide range by 2 to continue dichotomy sweep */
-          delta >>= 1;
-            
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          /* Note: on the last trimming loop, delta is equal to 0 and         */
-          /*       therefore has no effect.                                   */
-          if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp_trimmingvalue += delta;
-          }
-
-        }
-        
-        /* Check trimming result of the selected step and perform final fine  */
-        /* trimming.                                                          */
-        /*  - If calibration output is has toggled: the current step is       */
-        /*    already optimized.                                              */
-        /*  - If calibration output is has not toggled: the current step can  */
-        /*    be optimized by incrementing it of one step.                    */
-        if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp)) == tmp_Opaxcalout_DefaultSate)
-        {
-          *opamp_trimmingvalue += 1U;
-          
-          /* Set final fine trimming */
-          MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                              OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser);
-        }
-        
-      }
-
-      
-      /* Disable calibration for P and N differential pairs */
-      /* Disable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H(hopamp) | 
-                              OPAMP_CSR_OPAXCAL_L(hopamp) |
-                              OPAMP_CSR_OPAXPD(hopamp))    );
-
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-      
-      /* Self calibration is successful */
-      /* Store calibration (user trimming) results in init structure. */
-      
-      /* Set user trimming mode */  
-      hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      
-      /* Check on unsupported value */
-      if(opamp_trimmingvaluep == 0x1FU)  /* 0x1F is not functional */
-      {
-        opamp_trimmingvaluep = 30U;
-      }
-        
-      if(opamp_trimmingvaluen == 0x1FU)  /* 0x1F is not functional */
-      {
-        opamp_trimmingvaluen = 30U;
-      }
-
-      /* Affect calibration parameters depending on mode normal/low power */
-      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp->Init.TrimmingValueN = opamp_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp->Init.TrimmingValueP = opamp_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp->Init.TrimmingValueNLowPower = opamp_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp->Init.TrimmingValuePLowPower = opamp_trimmingvaluep;
-      }
-      
-      /* Update OPAMP state */
-      hopamp->State = HAL_OPAMP_STATE_READY;
-
-    }
-    
-    else
-    {
-      /* OPAMP can not be calibrated from this mode */ 
-      status = HAL_ERROR;
-    }
-  }
-  
-  return status;
-
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-      
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the OPAMP data 
-    transfers.
-
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected opamp configuration.
-  *         Caution: On STM32L1, HAL OPAMP lock is software lock only
-  *         (not hardware lock as available on some other STM32 devices)
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  /* OPAMP can be locked when enabled and running in normal mode */ 
-  /*   It is meaningless otherwise */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSY)
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-  
-   /* OPAMP state changed to locked */
-    hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-  return status; 
-}
-
-/**
-  * @brief  Return the OPAMP factory trimming value
-  *         Caution: On STM32L1 OPAMP, user can retrieve factory trimming if 
-  *                  OPAMP has never been set to user trimming before.
-  *                  Therefore, this fonction must be called when OPAMP init  
-  *                  parameter "UserTrimming" is set to trimming factory, 
-  *                  and before OPAMP  calibration (function 
-  *                  "HAL_OPAMP_SelfCalibrate()").
-  *                  Otherwise, factory triming value cannot be retrieved and 
-  *                  error status is returned.
-  * @param  hopamp  OPAMP handle
-  * @param  trimmingoffset  Trimming offset (P or N)
-  *         This parameter must be a value of @ref OPAMP_FactoryTrimming
-  * @note   Calibration parameter retrieved is corresponding to the mode 
-  *         specified in OPAMP init structure (mode normal or low-power). 
-  *         To retrieve calibration parameters for both modes, repeat this 
-  *         function after OPAMP init structure accordingly updated.
-  * @retval Trimming value (P or N) range: 0->31
-  *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
-  *
-  */
-HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
-{ 
-  HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
-  __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  
-  /* Check the OPAMP handle allocation */
-  /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
-  if(hopamp == NULL)
-  {
-    return OPAMP_FACTORYTRIMMING_DUMMY;
-  }
-
-  /* Check the OPAMP handle allocation */
-  /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
-  if(hopamp->State == HAL_OPAMP_STATE_READY)
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
-    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-    
-    /* Check the trimming mode */
-    if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) 
-    {
-      /* This fonction must called when OPAMP init parameter "UserTrimming"   */
-      /* is set to trimming factory, and before OPAMP calibration (function   */
-      /* "HAL_OPAMP_SelfCalibrate()").                                        */
-      /* Otherwise, factory triming value cannot be retrieved and error       */
-      /* status is returned.                                                  */
-      trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
-    }
-    else
-    {
-      /* Select trimming settings depending on power mode */
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      /* Get factory trimming  */
-      trimmingvalue = ((*tmp_opamp_reg_trimming >> OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK);
-    }
-  }
-  else
-  {
-    return OPAMP_FACTORYTRIMMING_DUMMY;
-  }  
-  return trimmingvalue;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the OPAMP handle state.
-  * @param  hopamp OPAMP handle
-  * @retval HAL state
-  */
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp)
-{
-  /* Check the OPAMP handle allocation */
-  if(hopamp == NULL)
-  {
-    return HAL_OPAMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
-  return hopamp->State;
-}
-
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User OPAMP Callback
-  *         To be used instead of the weak (surcharged) predefined callback 
-  * @param hopamp OPAMP handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID       OPAMP MspInit callback ID 
-  *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID     OPAMP MspDeInit callback ID  
-  * @param pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hopamp);
-  
-  if(hopamp->State == HAL_OPAMP_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-    case HAL_OPAMP_MSPINIT_CB_ID :
-      hopamp->MspInitCallback = pCallback;
-      break;
-    case HAL_OPAMP_MSPDEINIT_CB_ID :
-      hopamp->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      // hopamp->ErrorCode |= HAL_OPAMP_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hopamp->State == HAL_OPAMP_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-    case HAL_OPAMP_MSPINIT_CB_ID :
-      hopamp->MspInitCallback = pCallback;
-      break;
-    case HAL_OPAMP_MSPDEINIT_CB_ID :
-      hopamp->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      // hopamp->ErrorCode |= HAL_OPAMP_ERROR_INVALID_CALLBACK; 
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hopamp);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User OPAMP Callback
-  *         OPAMP Callback is redirected to the weak (surcharged) predefined callback 
-  * @param hopamp OPAMP handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID              OPAMP MSP Init Callback ID
-  *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID            OPAMP MSP DeInit Callback ID
-  *          @arg @ref HAL_OPAMP_ALL_CB_ID                   OPAMP All Callbacks
-  * @retval status
-  */
-
-HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hopamp);
-  
-  if(hopamp->State == HAL_OPAMP_STATE_READY)
-  {
-    switch (CallbackID)
-    {     
-      case HAL_OPAMP_MSPINIT_CB_ID :
-      hopamp->MspInitCallback = HAL_OPAMP_MspInit;
-      break;
-    case HAL_OPAMP_MSPDEINIT_CB_ID :
-      hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
-      break;
-    case HAL_OPAMP_ALL_CB_ID :
-      hopamp->MspInitCallback = HAL_OPAMP_MspInit;
-      hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
-      break;
-    default :
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hopamp->State == HAL_OPAMP_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-    case HAL_OPAMP_MSPINIT_CB_ID :
-      hopamp->MspInitCallback = HAL_OPAMP_MspInit;
-      break;
-    case HAL_OPAMP_MSPDEINIT_CB_ID :
-      hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
-      break;
-    default :
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hopamp);
-  return status;
-}
-
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c
deleted file mode 100644
index bdf12fac411..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_opamp_ex.c
+++ /dev/null
@@ -1,800 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended OPAMP HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
-  *          peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup OPAMPEx OPAMPEx
-  * @brief OPAMP Extended HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
-  * @{
-  */
-
-/** @addtogroup OPAMPEx_Exported_Functions_Group1
-  * @brief    Extended operation functions
-  *
-@verbatim
- ===============================================================================
-              ##### Extended IO operation functions #####
- ===============================================================================
-  [..]
-      (+) OPAMP Self calibration. 
-
-@endverbatim
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/*  3 OPAMPS available */
-/*  3 OPAMPS can be calibrated in parallel */
-
-/**
-  * @brief  Run the self calibration of the 3 OPAMPs in parallel.
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled is calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P  
-  *         and N transistors: 10 steps with 1 ms for each step).
-  * @param  hopamp1 handle
-  * @param  hopamp2 handle
-  * @param  hopamp3 handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp1_trimmingvalue;
-  uint32_t opamp1_trimmingvaluen = 0;
-  uint32_t opamp1_trimmingvaluep = 0;
-  
-  uint32_t* opamp2_trimmingvalue;
-  uint32_t opamp2_trimmingvaluen = 0;
-  uint32_t opamp2_trimmingvaluep = 0;
-  
-  uint32_t* opamp3_trimmingvalue;
-  uint32_t opamp3_trimmingvaluen = 0;
-  uint32_t opamp3_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair;              /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp1_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  __IO uint32_t* tmp_opamp2_reg_trimming;
-  __IO uint32_t* tmp_opamp3_reg_trimming;
-  uint32_t tmp_opamp1_otr_otuser;           /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-  uint32_t tmp_opamp2_otr_otuser;
-  uint32_t tmp_opamp3_otr_otuser;
-  
-  uint32_t tmp_Opa1calout_DefaultSate;      /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa2calout_DefaultSate;      /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa3calout_DefaultSate;      /* Bit OPAMP_CSR_OPA3CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup = 0x0U;
-  
-  uint8_t trimming_diff_pair_iteration_count = 0x0U;    /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */
-  uint8_t delta;                                        /* For calibration loop algorithm: Variable for dichotomy steps value */
-  uint8_t final_step_check = 0x0U;                      /* For calibration loop algorithm: Flag for additional check of last trimming step */
-
-
-  if((hopamp1 == NULL) || (hopamp2 == NULL) || (hopamp3 == NULL))
-  {
-    status = HAL_ERROR;
-  } 
-  /* Check if OPAMP in calibration mode and calibration not yet enable */
-  else if(hopamp1->State !=  HAL_OPAMP_STATE_READY)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp2->State != HAL_OPAMP_STATE_READY)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp3->State != HAL_OPAMP_STATE_READY)
-  {
-    status = HAL_ERROR;
-  }
-
-  else
-  {
-      /* Check the parameter */
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
-      assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
-      assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
-      assert_param(IS_OPAMP_POWERMODE(hopamp3->Init.PowerMode));
-      
-      /* Update OPAMP state */
-      hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY;
-      hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY;
-      hopamp3->State = HAL_OPAMP_STATE_CALIBBUSY;
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Open all switches on non-inverting input, inverting input and output */
-      /* feedback.                                                            */
-      CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Set calibration mode to user programmed trimming values */
-      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-      
-      /* Select trimming settings depending on power mode */
-      if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp1_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp1_otr_otuser = 0x00000000;
-        tmp_opamp1_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp2_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp2_otr_otuser = 0x00000000;
-        tmp_opamp2_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      if (hopamp3->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp3_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp3_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp3_otr_otuser = 0x00000000;
-        tmp_opamp3_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL);
-      
-      /* Perform trimming for both differential transistors pair high and low */
-      for (trimming_diff_pair_iteration_count = 0U; trimming_diff_pair_iteration_count <= 1U; trimming_diff_pair_iteration_count++)
-      {
-        if (trimming_diff_pair_iteration_count == 0U)
-        {
-          /* Calibration of transistors differential pair high (NMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluen;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluen;
-          opamp3_trimmingvalue = &opamp3_trimmingvaluen;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = RESET;
-          tmp_Opa2calout_DefaultSate = RESET;
-          tmp_Opa3calout_DefaultSate = RESET;
-          
-          /* Enable calibration for N differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL,
-                                 OPAMP_CSR_OPAXCAL_H_ALL);
-        }
-        else /* (trimming_diff_pair_iteration_count == 1) */
-        {
-          /* Calibration of transistors differential pair low (PMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluep;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluep;
-          opamp3_trimmingvalue = &opamp3_trimmingvaluep;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp1);
-          tmp_Opa2calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp2);
-          tmp_Opa3calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp3);
-          
-          /* Enable calibration for P differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL,
-                                 OPAMP_CSR_OPAXCAL_L_ALL);
-        }
-        
-      
-        /* Perform calibration parameter search by dichotomy sweep */
-        /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-        /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-        /*    can extend the search range to +/- 15 units.                    */
-        /*  - Trimming initial value 15: search range will go from 0 to 30    */
-        /*    (Trimming value 31 is forbidden).                               */
-        /* Note: After dichotomy sweep, the trimming result is determined.    */
-        /*       However, the final trimming step is deduced from previous    */
-        /*       trimming steps tested but is not effectively tested.         */
-        /*       An additional test step (using variable "final_step_check")  */
-        /*       allow to Test the final trimming step.                       */
-        *opamp1_trimmingvalue = 15U;
-        *opamp2_trimmingvalue = 15U;
-        *opamp3_trimmingvalue = 15U;
-        delta = 16U;
-        
-        while ((delta != 0U) || (final_step_check == 1U))
-        {
-          /* Set candidate trimming */
-          MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-
-          MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-
-          MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser);
-          
-          /* Offset trimming time: during calibration, minimum time needed    */
-          /* between two steps to have 1 mV accuracy.                         */
-          HAL_Delay(OPAMP_TRIMMING_DELAY);
-          
-          /* Set flag for additional check of last trimming step equal to     */
-          /* dichotomy step before its division by 2 (equivalent to previous  */
-          /* value of dichotomy step).                                        */
-          final_step_check = delta;
-          
-          /* Divide range by 2 to continue dichotomy sweep */
-          delta >>= 1U;
-          
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          /* Trimming values update with dichotomy delta of previous          */
-          /* iteration.                                                       */
-          /* Note: on the last trimming loop, delta is equal to 0 and         */
-          /*       therefore has no effect.                                   */
-          if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp1_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp1_trimmingvalue += delta;
-          }
-          
-          if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp2_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp2_trimmingvalue += delta;
-          }
-
-        if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate)
-        {
-          /* If calibration output is has toggled, try lower trimming */
-          *opamp3_trimmingvalue -= delta;
-        }
-        else
-        {
-          /* If calibration output is has not toggled, try higher trimming */
-          *opamp3_trimmingvalue += delta;
-        }
-      }
-      
-      /* Check trimming result of the selected step and perform final fine  */
-      /* trimming.                                                          */
-      /*  - If calibration output is has toggled: the current step is       */
-      /*    already optimized.                                              */
-      /*  - If calibration output is has not toggled: the current step can  */
-      /*    be optimized by incrementing it of one step.                    */
-      if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) == tmp_Opa1calout_DefaultSate)
-      {
-        *opamp1_trimmingvalue += 1U;
-        
-        /* Set final fine trimming */
-        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-      }
-      if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) == tmp_Opa2calout_DefaultSate)
-      {
-        *opamp2_trimmingvalue += 1U;
-        
-        /* Set final fine trimming */
-        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-      }
-      if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp3)) == tmp_Opa3calout_DefaultSate)
-      {
-        *opamp3_trimmingvalue += 1U;
-        
-        /* Set final fine trimming */
-        MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser);
-      }
-      
-    }
-     
-
-    /* Disable calibration for P and N differential pairs */
-    /* Disable the selected opamp */
-    CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | 
-                            OPAMP_CSR_OPAXCAL_L_ALL |
-                            OPAMP_CSR_OPAXPD_ALL     ));
-    
-    /* Backup of switches configuration to restore it at the end of the     */
-    /* calibration.                                                         */
-    SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-    
-    /* Self calibration is successful */
-    /* Store calibration (user trimming) results in init structure. */
-    
-    /* Set user trimming mode */  
-    hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
-    hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
-    hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
-    
-    /* Affect calibration parameters depending on mode normal/low power */
-    if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-    {
-      /* Write calibration result N */
-      hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep;
-    }
-    else
-    {
-      /* Write calibration result N */
-      hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep;
-    }
-    
-    if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-    {
-      /* Write calibration result N */
-      hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep;
-    }
-    else
-    {
-      /* Write calibration result N */
-      hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep;
-    }
-    
-    if (hopamp3->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-    {
-      /* Write calibration result N */
-      hopamp3->Init.TrimmingValueN = opamp3_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp3->Init.TrimmingValueP = opamp3_trimmingvaluep;
-    }
-    else
-    {
-      /* Write calibration result N */
-      hopamp3->Init.TrimmingValueNLowPower = opamp3_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp3->Init.TrimmingValuePLowPower = opamp3_trimmingvaluep;
-    }
-
-    /* Update OPAMP state */
-    hopamp1->State = HAL_OPAMP_STATE_READY;
-    hopamp2->State = HAL_OPAMP_STATE_READY;
-    hopamp3->State = HAL_OPAMP_STATE_READY;
-  }
-  return status;
-}
-
-#else
-
-/*  2 OPAMPS available */
-/*  2 OPAMPS can be calibrated in parallel */
-
-/**
-  * @brief  Run the self calibration of the 2 OPAMPs in parallel.
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled is calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P  
-  *         and N transistors: 10 steps with 1 ms for each step).
-  * @param  hopamp1 handle
-  * @param  hopamp2 handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp1_trimmingvalue;
-  uint32_t opamp1_trimmingvaluen = 0;
-  uint32_t opamp1_trimmingvaluep = 0;
-  
-  uint32_t* opamp2_trimmingvalue;
-  uint32_t opamp2_trimmingvaluen = 0;
-  uint32_t opamp2_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair;          /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp1_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  __IO uint32_t* tmp_opamp2_reg_trimming;
-  uint32_t tmp_opamp1_otr_otuser;       /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-  uint32_t tmp_opamp2_otr_otuser;
-  
-  uint32_t tmp_Opa1calout_DefaultSate;  /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa2calout_DefaultSate;  /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup;
-  
-  uint8_t trimming_diff_pair_iteration_count;          /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */
-  uint8_t delta;                                       /* For calibration loop algorithm: Variable for dichotomy steps value */
-  uint8_t final_step_check = 0x0U;                     /* For calibration loop algorithm: Flag for additional check of last trimming step */
-
-
-  if((hopamp1 == NULL) || (hopamp2 == NULL))
-  {
-    status = HAL_ERROR;
-  }
-  /* Check if OPAMP in calibration mode and calibration not yet enable */
-  else if(hopamp1->State !=  HAL_OPAMP_STATE_READY)
-  {
-    status = HAL_ERROR;
-  }
-  else if(hopamp2->State != HAL_OPAMP_STATE_READY)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
-    assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
-    assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
-    
-    /* Update OPAMP state */
-    hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY;
-    hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY;
-    
-    /* Backup of switches configuration to restore it at the end of the     */
-    /* calibration.                                                         */
-    tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-    
-    /* Open all switches on non-inverting input, inverting input and output */
-    /* feedback.                                                            */
-    CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-    
-    /* Set calibration mode to user programmed trimming values */
-    SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-    
-    /* Select trimming settings depending on power mode */
-    if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-    {
-      tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER;
-      tmp_opamp1_reg_trimming = &OPAMP->OTR;
-    }
-    else
-    {
-      tmp_opamp1_otr_otuser = 0x00000000U;
-      tmp_opamp1_reg_trimming = &OPAMP->LPOTR;
-    }
-    
-    if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-    {
-      tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER;
-      tmp_opamp2_reg_trimming = &OPAMP->OTR;
-    }
-    else
-    {
-      tmp_opamp2_otr_otuser = 0x00000000U;
-      tmp_opamp2_reg_trimming = &OPAMP->LPOTR;
-    }
-    
-    /* Enable the selected opamp */
-    CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL);
-    
-    /* Perform trimming for both differential transistors pair high and low */
-    for (trimming_diff_pair_iteration_count = 0U; trimming_diff_pair_iteration_count <= 1U; trimming_diff_pair_iteration_count++)
-    {
-      if (trimming_diff_pair_iteration_count == 0U)
-      {
-        /* Calibration of transistors differential pair high (NMOS) */
-        trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-        opamp1_trimmingvalue = &opamp1_trimmingvaluen;
-        opamp2_trimmingvalue = &opamp2_trimmingvaluen;
-        
-        /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-        /* is 00000b. Used to detect the bit toggling during trimming.      */
-        tmp_Opa1calout_DefaultSate = 0U;
-        tmp_Opa2calout_DefaultSate = 0U;
-        
-        /* Enable calibration for N differential pair */
-        MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL,
-                               OPAMP_CSR_OPAXCAL_H_ALL);
-      }
-      else /* (trimming_diff_pair_iteration_count == 1) */
-      {
-        /* Calibration of transistors differential pair low (PMOS) */
-        trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-        opamp1_trimmingvalue = &opamp1_trimmingvaluep;
-        opamp2_trimmingvalue = &opamp2_trimmingvaluep;
-        
-        /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-        /* is 00000b. Used to detect the bit toggling during trimming.      */
-        tmp_Opa1calout_DefaultSate = (uint32_t) OPAMP_CSR_OPAXCALOUT(hopamp1);
-        tmp_Opa2calout_DefaultSate = OPAMP_CSR_OPAXCALOUT(hopamp2);
-        
-        /* Enable calibration for P differential pair */
-        MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL,
-                               OPAMP_CSR_OPAXCAL_L_ALL);
-      }
-      
-    
-      /* Perform calibration parameter search by dichotomy sweep */
-      /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-      /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-      /*    can extend the search range to +/- 15 units.                    */
-      /*  - Trimming initial value 15: search range will go from 0 to 30    */
-      /*    (Trimming value 31 is forbidden).                               */
-      /* Note: After dichotomy sweep, the trimming result is determined.    */
-      /*       However, the final trimming step is deduced from previous    */
-      /*       trimming steps tested but is not effectively tested.         */
-      /*       An additional test step (using variable "final_step_check")  */
-      /*       allow to Test the final trimming step.                       */
-      *opamp1_trimmingvalue = 15U;
-      *opamp2_trimmingvalue = 15U;
-      delta = 16U;
-      
-      while ((delta != 0U) || (final_step_check == 1U))
-      {
-        /* Set candidate trimming */
-        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-
-        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-
-        
-        /* Offset trimming time: during calibration, minimum time needed    */
-        /* between two steps to have 1 mV accuracy.                         */
-        HAL_Delay(OPAMP_TRIMMING_DELAY);
-        
-        /* Set flag for additional check of last trimming step equal to     */
-        /* dichotomy step before its division by 2 (equivalent to previous  */
-        /* value of dichotomy step).                                        */
-        final_step_check = delta;
-        
-        /* Divide range by 2 to continue dichotomy sweep */
-        delta >>= 1U;
-        
-        /* Set trimming values for next iteration in function of trimming   */
-        /* result toggle (versus initial state).                            */
-        /* Trimming values update with dichotomy delta of previous          */
-        /* iteration.                                                       */
-        /* Note: on the last trimming loop, delta is equal to 0 and         */
-        /*       therefore has no effect.                                   */
-        if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate)
-        {
-          /* If calibration output is has toggled, try lower trimming */
-          *opamp1_trimmingvalue -= delta;
-        }
-        else
-        {
-          /* If calibration output is has not toggled, try higher trimming */
-          *opamp1_trimmingvalue += delta;
-        }
-        
-        if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate)
-        {
-          /* If calibration output is has toggled, try lower trimming */
-          *opamp2_trimmingvalue -= delta;
-        }
-        else
-        {
-          /* If calibration output is has not toggled, try higher trimming */
-          *opamp2_trimmingvalue += delta;
-        }
-      }
-      
-      /* Check trimming result of the selected step and perform final fine  */
-      /* trimming.                                                          */
-      /*  - If calibration output is has toggled: the current step is       */
-      /*    already optimized.                                              */
-      /*  - If calibration output is has not toggled: the current step can  */
-      /*    be optimized by incrementing it of one step.                    */
-      if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp1)) == tmp_Opa1calout_DefaultSate)
-      {
-        *opamp1_trimmingvalue += 1U;
-        
-        /* Set final fine trimming */
-        MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-      }
-      if (READ_BIT(OPAMP->CSR, OPAMP_CSR_OPAXCALOUT(hopamp2)) == tmp_Opa2calout_DefaultSate)
-      {
-        *opamp2_trimmingvalue += 1U;
-        
-        /* Set final fine trimming */
-        MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                             OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-
-      }
-      
-    }
-     
-
-    /* Disable calibration for P and N differential pairs */
-    /* Disable the selected opamp */
-    CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | 
-                            OPAMP_CSR_OPAXCAL_L_ALL |
-                            OPAMP_CSR_OPAXPD_ALL     ));
-    
-    /* Backup of switches configuration to restore it at the end of the     */
-    /* calibration.                                                         */
-    SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-    
-    /* Self calibration is successful */
-    /* Store calibration (user trimming) results in init structure. */
-    
-    /* Set user trimming mode */  
-    hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
-    hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
-    
-    /* Affect calibration parameters depending on mode normal/low power */
-    if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-    {
-      /* Write calibration result N */
-      hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep;
-    }
-    else
-    {
-      /* Write calibration result N */
-      hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep;
-    }
-    
-    if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-    {
-      /* Write calibration result N */
-      hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep;
-    }
-    else
-    {
-      /* Write calibration result N */
-      hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen;
-      /* Write calibration result P */
-      hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep;
-    }
-
-    /* Update OPAMP state */
-    hopamp1->State = HAL_OPAMP_STATE_READY;
-    hopamp2->State = HAL_OPAMP_STATE_READY;
-  }
-  return status;
-}
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions 
- *  @brief   Extended peripheral control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-      (+) OPAMP unlock. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the selected OPAMP configuration.
-  *         This function must be called only when OPAMP is in state "locked".
-  * @param  hopamp OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if(hopamp == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-  
-   /* OPAMP state changed to locked */
-    hopamp->State = HAL_OPAMP_STATE_BUSY;
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  return status; 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c
deleted file mode 100644
index 11cd9529819..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd.c
+++ /dev/null
@@ -1,1997 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-
-     (#) Fill parameters of Init structure in HCD handle
-
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using
-              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
-
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable PCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined (USB)
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
-  * @{
-  */
-#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
-  uint8_t i;
-
-  /* Check the PCD handle allocation */
-  if (hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
-  if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hpcd->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SOFCallback = HAL_PCD_SOFCallback;
-    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
-    hpcd->ResetCallback = HAL_PCD_ResetCallback;
-    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
-    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
-    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
-    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
-
-    if (hpcd->MspInitCallback == NULL)
-    {
-      hpcd->MspInitCallback = HAL_PCD_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hpcd->MspInitCallback(hpcd);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_PCD_MspInit(hpcd);
-#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Disable the Interrupts */
-  __HAL_PCD_DISABLE(hpcd);
-
-  /* Init endpoints structures */
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
-  {
-    /* Init ep structure */
-    hpcd->IN_ep[i].is_in = 1U;
-    hpcd->IN_ep[i].num = i;
-    hpcd->IN_ep[i].tx_fifo_num = i;
-    /* Control until ep is activated */
-    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-    hpcd->IN_ep[i].maxpacket = 0U;
-    hpcd->IN_ep[i].xfer_buff = 0U;
-    hpcd->IN_ep[i].xfer_len = 0U;
-  }
-
-  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
-  {
-    hpcd->OUT_ep[i].is_in = 0U;
-    hpcd->OUT_ep[i].num = i;
-    /* Control until ep is activated */
-    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-    hpcd->OUT_ep[i].maxpacket = 0U;
-    hpcd->OUT_ep[i].xfer_buff = 0U;
-    hpcd->OUT_ep[i].xfer_len = 0U;
-  }
-
-  /* Init Device */
-  (void)USB_DevInit(hpcd->Instance, hpcd->Init);
-
-  hpcd->USB_Address = 0U;
-  hpcd->State = HAL_PCD_STATE_READY;
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if (hpcd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = HAL_PCD_STATE_BUSY;
-
-  /* Stop Device */
-  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  if (hpcd->MspDeInitCallback == NULL)
-  {
-    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware */
-  hpcd->MspDeInitCallback(hpcd);
-#else
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_PCD_MspDeInit(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-  hpcd->State = HAL_PCD_STATE_RESET;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User USB PCD Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hpcd USB PCD handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
-                                           HAL_PCD_CallbackIDTypeDef CallbackID,
-                                           pPCD_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_SOF_CB_ID :
-        hpcd->SOFCallback = pCallback;
-        break;
-
-      case HAL_PCD_SETUPSTAGE_CB_ID :
-        hpcd->SetupStageCallback = pCallback;
-        break;
-
-      case HAL_PCD_RESET_CB_ID :
-        hpcd->ResetCallback = pCallback;
-        break;
-
-      case HAL_PCD_SUSPEND_CB_ID :
-        hpcd->SuspendCallback = pCallback;
-        break;
-
-      case HAL_PCD_RESUME_CB_ID :
-        hpcd->ResumeCallback = pCallback;
-        break;
-
-      case HAL_PCD_CONNECT_CB_ID :
-        hpcd->ConnectCallback = pCallback;
-        break;
-
-      case HAL_PCD_DISCONNECT_CB_ID :
-        hpcd->DisconnectCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = pCallback;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-  return status;
-}
-
-/**
-  * @brief  Unregister an USB PCD Callback
-  *         USB PCD callabck is redirected to the weak predefined callback
-  * @param  hpcd USB PCD handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
-  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
-  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
-  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
-  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
-  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
-  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
-  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  /* Setup Legacy weak Callbacks  */
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_SOF_CB_ID :
-        hpcd->SOFCallback = HAL_PCD_SOFCallback;
-        break;
-
-      case HAL_PCD_SETUPSTAGE_CB_ID :
-        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
-        break;
-
-      case HAL_PCD_RESET_CB_ID :
-        hpcd->ResetCallback = HAL_PCD_ResetCallback;
-        break;
-
-      case HAL_PCD_SUSPEND_CB_ID :
-        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
-        break;
-
-      case HAL_PCD_RESUME_CB_ID :
-        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
-        break;
-
-      case HAL_PCD_CONNECT_CB_ID :
-        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
-        break;
-
-      case HAL_PCD_DISCONNECT_CB_ID :
-        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
-        break;
-
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = HAL_PCD_MspInit;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hpcd->State == HAL_PCD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_PCD_MSPINIT_CB_ID :
-        hpcd->MspInitCallback = HAL_PCD_MspInit;
-        break;
-
-      case HAL_PCD_MSPDEINIT_CB_ID :
-        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Data OUT Stage Callback
-  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_DataOutStageCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataOutStageCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Data OUT Stage Callback
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Data IN Stage Callback
-  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_DataInStageCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataInStageCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Data IN Stage Callback
-  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Iso OUT incomplete Callback
-  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOOUTIncompleteCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Iso OUT incomplete Callback
-  *         USB PCD Iso OUT incomplete Callback is redirected
-  *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Register USB PCD Iso IN incomplete Callback
-  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
-                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOINIncompleteCallback = pCallback;
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister the USB PCD Iso IN incomplete Callback
-  *         USB PCD Iso IN incomplete Callback is redirected
-  *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hpcd);
-
-  if (hpcd->State == HAL_PCD_STATE_READY)
-  {
-    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
-  }
-  else
-  {
-    /* Update the error code */
-    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hpcd);
-
-  return status;
-}
-
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the USB device
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  __HAL_PCD_ENABLE(hpcd);
-
-  HAL_PCDEx_SetConnectionState(hpcd, 1U);
-
-  (void)USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the USB device.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-  __HAL_PCD_DISABLE(hpcd);
-
-  HAL_PCDEx_SetConnectionState(hpcd, 0U);
-
-  (void)USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  This function handles PCD interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
-  {
-    /* servicing of the endpoint correct transfer interrupt */
-    /* clear of the CTR flag into the sub */
-    (void)PCD_EP_ISR_Handler(hpcd);
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->ResetCallback(hpcd);
-#else
-    HAL_PCD_ResetCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-    (void)HAL_PCD_SetAddress(hpcd, 0U);
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
-  {
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
-    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->ResumeCallback(hpcd);
-#else
-    HAL_PCD_ResumeCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
-  {
-    /* Force low-power mode in the macrocell */
-    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
-    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
-    hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SuspendCallback(hpcd);
-#else
-    HAL_PCD_SuspendCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-    hpcd->SOFCallback(hpcd);
-#else
-    HAL_PCD_SOFCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-  }
-
-  if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
-  {
-    /* clear ESOF flag in ISTR */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
-  }
-}
-
-
-/**
-  * @brief  Handles PCD Wakeup interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  /* Clear EXTI pending Bit */
-  __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG();
-}
-
-
-/**
-  * @brief  Data OUT stage callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Data IN stage callback
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Setup stage callback
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Start Of Frame callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USB Reset callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Suspend event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Resume event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Incomplete ISO IN callback.
-  * @param  hpcd PCD handle
-  * @param  epnum endpoint number
-  * @retval None
-  */
-__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(epnum);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Connection event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Disconnection event callback.
-  * @param  hpcd PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   management functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-
-  HAL_PCDEx_SetConnectionState(hpcd, 1U);
-
-  (void)USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd);
-
-  HAL_PCDEx_SetConnectionState(hpcd, 0U);
-
-  (void)USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address.
-  * @param  hpcd PCD handle
-  * @param  address new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-  __HAL_LOCK(hpcd);
-  hpcd->USB_Address = address;
-  (void)USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  ep_mps endpoint max packet size
-  * @param  ep_type endpoint type
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                  uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  PCD_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-
-  ep->num = ep_addr & EP_ADDR_MSK;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-
-  if (ep->is_in != 0U)
-  {
-    /* Assign a Tx FIFO */
-    ep->tx_fifo_num = ep->num;
-  }
-  /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK)
-  {
-    ep->data_pid_start = 0U;
-  }
-
-  __HAL_LOCK(hpcd);
-  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-
-  return ret;
-}
-
-/**
-  * @brief  Deactivate an endpoint.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if ((ep_addr & 0x80U) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-  ep->num   = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data.
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  pBuf pointer to the reception buffer
-  * @param  len amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  PCD_EPTypeDef *ep;
-
-  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 0U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval Data Size
-  */
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
-}
-/**
-  * @brief  Send an amount of data
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @param  pBuf pointer to the transmission buffer
-  * @param  len amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  PCD_EPTypeDef *ep;
-
-  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;
-  ep->xfer_len = len;
-  ep->xfer_fill_db = 1U;
-  ep->xfer_len_db = len;
-  ep->xfer_count = 0U;
-  ep->is_in = 1U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
-  {
-    return HAL_ERROR;
-  }
-
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-    ep->is_in = 0U;
-  }
-
-  ep->is_stall = 1U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-
-  (void)USB_EPSetStall(hpcd->Instance, ep);
-
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-
-  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
-  {
-    return HAL_ERROR;
-  }
-
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 1U;
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
-    ep->is_in = 0U;
-  }
-
-  ep->is_stall = 0U;
-  ep->num = ep_addr & EP_ADDR_MSK;
-
-  __HAL_LOCK(hpcd);
-  (void)USB_EPClearStall(hpcd->Instance, ep);
-  __HAL_UNLOCK(hpcd);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint
-  * @param  hpcd PCD handle
-  * @param  ep_addr endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(ep_addr);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Activate remote wakeup signalling
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  return (USB_ActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
-  * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the PCD handle state.
-  * @param  hpcd PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  This function handles PCD Endpoint interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
-  PCD_EPTypeDef *ep;
-  uint16_t count, wIstr, wEPVal, TxByteNbre;
-  uint8_t epindex;
-
-  /* stay in loop while pending interrupts */
-  while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
-  {
-    wIstr = hpcd->Instance->ISTR;
-
-    /* extract highest priority endpoint number */
-    epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
-    if (epindex == 0U)
-    {
-      /* Decode and service control endpoint interrupt */
-
-      /* DIR bit = origin of the interrupt */
-      if ((wIstr & USB_ISTR_DIR) == 0U)
-      {
-        /* DIR = 0 */
-
-        /* DIR = 0 => IN  int */
-        /* DIR = 0 implies that (EP_CTR_TX = 1) always */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-        ep = &hpcd->IN_ep[0];
-
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-        ep->xfer_buff += ep->xfer_count;
-
-        /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-        hpcd->DataInStageCallback(hpcd, 0U);
-#else
-        HAL_PCD_DataInStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-        if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
-        {
-          hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
-          hpcd->USB_Address = 0U;
-        }
-      }
-      else
-      {
-        /* DIR = 1 */
-
-        /* DIR = 1 & CTR_RX => SETUP or OUT int */
-        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
-        ep = &hpcd->OUT_ep[0];
-        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
-        if ((wEPVal & USB_EP_SETUP) != 0U)
-        {
-          /* Get SETUP Packet */
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
-                      ep->pmaadress, (uint16_t)ep->xfer_count);
-
-          /* SETUP bit kept frozen while CTR_RX = 1 */
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
-          /* Process SETUP Packet*/
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-          hpcd->SetupStageCallback(hpcd);
-#else
-          HAL_PCD_SetupStageCallback(hpcd);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-        }
-        else if ((wEPVal & USB_EP_CTR_RX) != 0U)
-        {
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
-          /* Get Control Data OUT Packet */
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
-          {
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
-                        ep->pmaadress, (uint16_t)ep->xfer_count);
-
-            ep->xfer_buff += ep->xfer_count;
-
-            /* Process Control Data OUT Packet */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-            hpcd->DataOutStageCallback(hpcd, 0U);
-#else
-            HAL_PCD_DataOutStageCallback(hpcd, 0U);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-          }
-
-          if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
-          {
-            PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
-            PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Decode and service non control endpoints interrupt */
-      /* process related endpoint register */
-      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
-
-      if ((wEPVal & USB_EP_CTR_RX) != 0U)
-      {
-        /* clear int flag */
-        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
-        ep = &hpcd->OUT_ep[epindex];
-
-        /* OUT Single Buffering */
-        if (ep->doublebuffer == 0U)
-        {
-          count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
-          if (count != 0U)
-          {
-            USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
-          }
-        }
-        else
-        {
-          /* manage double buffer bulk out */
-          if (ep->type == EP_TYPE_BULK)
-          {
-            count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
-          }
-          else /* manage double buffer iso out */
-          {
-            /* free EP OUT Buffer */
-            PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-
-            if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
-            {
-              /* read from endpoint BUF0Addr buffer */
-              count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-              if (count != 0U)
-              {
-                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
-              }
-            }
-            else
-            {
-              /* read from endpoint BUF1Addr buffer */
-              count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-              if (count != 0U)
-              {
-                USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
-              }
-            }
-          }
-        }
-        /* multi-packet on the NON control OUT endpoint */
-        ep->xfer_count += count;
-        ep->xfer_buff += count;
-
-        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
-        {
-          /* RX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-          hpcd->DataOutStageCallback(hpcd, ep->num);
-#else
-          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-        }
-        else
-        {
-          (void) USB_EPStartXfer(hpcd->Instance, ep);
-        }
-
-      }
-
-      if ((wEPVal & USB_EP_CTR_TX) != 0U)
-      {
-        ep = &hpcd->IN_ep[epindex];
-
-        /* clear int flag */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
-
-        /* Manage all non bulk/isoc transaction Bulk Single Buffer Transaction */
-        if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_CTRL) ||
-           ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
-        {
-          /* multi-packet on the NON control IN endpoint */
-          TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-
-          if (ep->xfer_len > TxByteNbre)
-          {
-            ep->xfer_len -= TxByteNbre;
-          }
-          else
-          {
-            ep->xfer_len = 0U;
-          }
-
-          /* Zero Length Packet? */
-          if (ep->xfer_len == 0U)
-          {
-            /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-            hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-            HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-          }
-          else
-          {
-            /* Transfer is not yet Done */
-            ep->xfer_buff += TxByteNbre;
-            ep->xfer_count += TxByteNbre;
-            (void)USB_EPStartXfer(hpcd->Instance, ep);
-          }
-        }
-        /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
-        else
-        {
-          (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
-        }
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Manage double buffer bulk out transaction from ISR
-  * @param  hpcd PCD handle
-  * @param  ep current endpoint handle
-  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
-  * @retval HAL status
-  */
-static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
-                                      PCD_EPTypeDef *ep, uint16_t wEPVal)
-{
-  uint16_t count;
-
-  /* Manage Buffer0 OUT */
-  if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-  {
-    /* Get count of received Data on buffer0 */
-    count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= count)
-    {
-      ep->xfer_len -= count;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    if (ep->xfer_len == 0U)
-    {
-      /* set NAK to OUT endpoint since double buffer is enabled */
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
-    }
-
-    /* Check if Buffer1 is in blocked sate which requires to toggle */
-    if ((wEPVal & USB_EP_DTOG_TX) != 0U)
-    {
-      PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-    }
-
-    if (count != 0U)
-    {
-      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
-    }
-  }
-  /* Manage Buffer 1 DTOG_RX=0 */
-  else
-  {
-    /* Get count of received data */
-    count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= count)
-    {
-      ep->xfer_len -= count;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    if (ep->xfer_len == 0U)
-    {
-      /* set NAK on the current endpoint */
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
-    }
-
-    /*Need to FreeUser Buffer*/
-    if ((wEPVal & USB_EP_DTOG_TX) == 0U)
-    {
-      PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-    }
-
-    if (count != 0U)
-    {
-      USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
-    }
-  }
-
-  return count;
-}
-
-
-/**
-  * @brief  Manage double buffer bulk IN transaction from ISR
-  * @param  hpcd PCD handle
-  * @param  ep current endpoint handle
-  * @param  wEPVal Last snapshot of EPRx register value taken in ISR
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
-                                                PCD_EPTypeDef *ep, uint16_t wEPVal)
-{
-  uint32_t len;
-  uint16_t TxByteNbre;
-
-  /* Data Buffer0 ACK received */
-  if ((wEPVal & USB_EP_DTOG_TX) != 0U)
-  {
-    /* multi-packet on the NON control IN endpoint */
-    TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len > TxByteNbre)
-    {
-      ep->xfer_len -= TxByteNbre;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-    /* Transfer is completed */
-    if (ep->xfer_len == 0U)
-    {
-      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
-      /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-      HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-    }
-    else /* Transfer is not yet Done */
-    {
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) != 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-
-      /* Still there is data to Fill in the next Buffer */
-      if (ep->xfer_fill_db == 1U)
-      {
-        ep->xfer_buff += TxByteNbre;
-        ep->xfer_count += TxByteNbre;
-
-        /* Calculate the len of the new buffer to fill */
-        if (ep->xfer_len_db >= ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len_db -= len;
-        }
-        else if (ep->xfer_len_db == 0U)
-        {
-          len = TxByteNbre;
-          ep->xfer_fill_db = 0U;
-        }
-        else
-        {
-          ep->xfer_fill_db = 0U;
-          len = ep->xfer_len_db;
-          ep->xfer_len_db = 0U;
-        }
-
-        /* Write remaining Data to Buffer */
-        /* Set the Double buffer counter for pma buffer1 */
-        PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
-        /* Copy user buffer to USB PMA */
-        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr0, (uint16_t)len);
-      }
-    }
-  }
-  else /* Data Buffer1 ACK received */
-  {
-    /* multi-packet on the NON control IN endpoint */
-    TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-
-    if (ep->xfer_len >= TxByteNbre)
-    {
-      ep->xfer_len -= TxByteNbre;
-    }
-    else
-    {
-      ep->xfer_len = 0U;
-    }
-
-    /* Transfer is completed */
-    if (ep->xfer_len == 0U)
-    {
-      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
-
-      /* TX COMPLETE */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->DataInStageCallback(hpcd, ep->num);
-#else
-      HAL_PCD_DataInStageCallback(hpcd, ep->num);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-    }
-    else /* Transfer is not yet Done */
-    {
-      /* need to Free USB Buff */
-      if ((wEPVal & USB_EP_DTOG_RX) == 0U)
-      {
-        PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
-      }
-
-      /* Still there is data to Fill in the next Buffer */
-      if (ep->xfer_fill_db == 1U)
-      {
-        ep->xfer_buff += TxByteNbre;
-        ep->xfer_count += TxByteNbre;
-
-        /* Calculate the len of the new buffer to fill */
-        if (ep->xfer_len_db >= ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len_db -= len;
-        }
-        else if (ep->xfer_len_db == 0U)
-        {
-          len = TxByteNbre;
-          ep->xfer_fill_db = 0U;
-        }
-        else
-        {
-          len = ep->xfer_len_db;
-          ep->xfer_len_db = 0U;
-          ep->xfer_fill_db = 0;
-        }
-
-        /* Set the Double buffer counter for pmabuffer1 */
-        PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
-        /* Copy the user buffer to USB PMA */
-        USB_WritePMA(hpcd->Instance, ep->xfer_buff,  ep->pmaaddr1, (uint16_t)len);
-      }
-    }
-  }
-
-  /*enable endpoint IN*/
-  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-
-  return HAL_OK;
-}
-
-
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c
deleted file mode 100644
index f3a1cda4809..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pcd_ex.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @brief   PCD Extended HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Extended features functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCD Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined (USB)
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions
-  *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Update FIFO configuration
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure PMA for EP
-  * @param  hpcd  Device instance
-  * @param  ep_addr endpoint address
-  * @param  ep_kind endpoint Kind
-  *                  USB_SNG_BUF: Single Buffer used
-  *                  USB_DBL_BUF: Double Buffer used
-  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
-  *                   this parameter is 16-bit value providing the address
-  *                   in PMA allocated to endpoint.
-  *                   In case of double buffer endpoint this parameter
-  *                   is a 32-bit value providing the endpoint buffer 0 address
-  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
-  *                   in the MSB part of 32-bit value.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
-                                       uint16_t ep_kind, uint32_t pmaadress)
-{
-  PCD_EPTypeDef *ep;
-
-  /* initialize ep structure*/
-  if ((0x80U & ep_addr) == 0x80U)
-  {
-    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-
-  /* Here we check if the endpoint is single or double Buffer*/
-  if (ep_kind == PCD_SNG_BUF)
-  {
-    /* Single Buffer */
-    ep->doublebuffer = 0U;
-    /* Configure the PMA */
-    ep->pmaadress = (uint16_t)pmaadress;
-  }
-  else /* USB_DBL_BUF */
-  {
-    /* Double Buffer Endpoint */
-    ep->doublebuffer = 1U;
-    /* Configure the PMA */
-    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
-    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Software Device Connection,
-  *         this function is not required by USB OTG FS peripheral, it is used
-  *         only by USB Device FS peripheral.
-  * @param  hpcd PCD handle
-  * @param  state connection state (0 : disconnected / 1: connected)
-  * @retval None
-  */
-__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(state);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCDEx_SetConnectionState could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Send LPM message to user layer callback.
-  * @param  hpcd PCD handle
-  * @param  msg LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_LPM_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Send BatteryCharging message to user layer callback.
-  * @param  hpcd PCD handle
-  * @param  msg LPM message
-  * @retval HAL status
-  */
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hpcd);
-  UNUSED(msg);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_PCDEx_BCD_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c
deleted file mode 100644
index a1fdcc39601..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief    PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define PVD_MODE_IT               (0x00010000U)
-#define PVD_MODE_EVT              (0x00020000U)
-#define PVD_RISING_EDGE           (0x00000001U)
-#define PVD_FALLING_EDGE          (0x00000002U)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief   Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data
-      registers) is protected against possible unwanted
-      write accesses.
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __HAL_RCC_PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
-  * @note   Before calling this function, the VOS[1:0] bits should be configured
-  *         to "10" and the system frequency has to be configured accordingly.
-  *         To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
-  *         function.
-  * @note   ULP and FWU bits are not reset by this function.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief  Enables access to the backup domain (RTC registers, RTC
-  *         backup data registers ).
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  /* Enable access to RTC and backup registers */
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables access to the backup domain (RTC registers, RTC
-  *         backup data registers).
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  /* Disable access to RTC and backup registers */
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
-  * @brief    Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
-      internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
-      when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
-
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
-          than the PVD threshold. This event is internally connected to the EXTI
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-
-    *** WakeUp pin configuration ***
-    ================================
-    [..]
-      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There are two or three WakeUp pins:
-          WakeUp Pin 1 on PA.00.
-          WakeUp Pin 2 on PC.13.
-          WakeUp Pin 3 on PE.06. : Only on product with GPIOE available
-
-    [..]
-    *** Main and Backup Regulators configuration ***
-    ================================================
-
-      (+) The main internal regulator can be configured to have a tradeoff between
-          performance and power consumption when the device does not operate at
-          the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
-          macro which configure VOS bit in PWR_CR register:
-        (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
-             the System frequency can go up to 32 MHz.
-        (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
-             the System frequency can go up to 16 MHz.
-        (++) When this bit is reset (Regulator voltage output Scale 3 mode selected)
-             the System frequency can go up to 4.2 MHz.
-
-        Refer to the datasheets for more details.
-
-    *** Low Power modes configuration ***
-    =====================================
-     [..]
-      The device features 5 low-power modes:
-      (+) Low power run mode: regulator in low power mode, limited clock frequency,
-        limited number of peripherals running.
-      (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
-      (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
-         limited number of peripherals running, regulator in low power mode.
-      (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
-      (+) Standby mode: VCORE domain powered off
-
-   *** Low power run mode ***
-   =========================
-    [..]
-       To further reduce the consumption when the system is in Run mode, the regulator can be
-        configured in low power mode. In this mode, the system frequency should not exceed
-        MSI frequency range1.
-        In Low power run mode, all I/O pins keep the same state as in Run mode.
-
-      (+) Entry:
-        (++) VCORE in range2
-        (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.
-        (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
-             function.
-      (+) Exit:
-        (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
-              function.
-        (++) Increase the system frequency if needed.
-
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
-      (+) Exit:
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
-              controller (NVIC) can wake up the device from Sleep mode.
-
-   *** Low power sleep mode ***
-   ============================
-    [..]
-      (+) Entry:
-          The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-       (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
-             This reduces power consumption but increases the wake-up time.
-
-      (+) Exit:
-        (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
-              acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
-              from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
-              the MCU exits Sleep mode as soon as an event occurs.
-
-   *** Stop mode ***
-   =================
-    [..]
-      The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
-      clock gating. The voltage regulator can be configured either in normal or low-power mode.
-      In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
-      the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
-      To get the lowest consumption in Stop mode, the internal Flash memory also enters low
-      power mode. When the Flash memory is in power-down mode, an additional startup delay is
-      incurred when waking up from Stop mode.
-      To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
-      sensor can be switched off before entering Stop mode. They can be switched on again by
-      software after exiting Stop mode using the ULP bit in the PWR_CR register.
-      In Stop mode, all I/O pins keep the same state as in Run mode.
-
-      (+) Entry:
-           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-      (+) Exit:
-        (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
-
-   *** Standby mode ***
-   ====================
-     [..]
-      The Standby mode allows to achieve the lowest power consumption. It is based on the
-      Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is
-      consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
-      also switched off. SRAM and register contents are lost except for the RTC registers, RTC
-      backup registers and Standby circuitry.
-
-      To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
-       sensor can be switched off before entering the Standby mode. They can be switched
-       on again by software after exiting the Standby mode.
-       function.
-
-      (+) Entry:
-        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (+) Exit:
-        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wakeup (AWU) from low-power mode ***
-   =============================================
-    [..]
-      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
-      Wakeup event, a tamper event, a time-stamp event, or a comparator event,
-      without depending on an external interrupt (Auto-wakeup mode).
-
-    (+) RTC auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
-             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
-                   or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()
-                   function
-             (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
-                   and HAL_RTC_SetTime() functions.
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
-             is necessary to:
-             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and
-                   Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT()
-                   or HAL_RTCEx_SetTimeStamp_IT() functions.
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
-             (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and
-                   Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-             (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer()
-                   function.
-
-    (+) RTC auto-wakeup (AWU) from the Standby mode
-        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
-             (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.
-             (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
-                   and HAL_RTC_SetTime() functions.
-        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
-             is necessary to:
-             (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to
-                   detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()
-                   or HAL_RTCEx_SetTamper_IT()functions.
-        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
-             (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event
-                   using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.
-
-    (+) Comparator auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
-             event, it is necessary to:
-             (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the
-                   selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using
-                   the COMP functions.
-             (+++) Configure the comparator to generate the event.
-
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *         information for the PVD.
-  * @note   Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE();
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-}
-
-/**
-  * @brief  Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  /* Enable the power voltage detector */
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  /* Disable the power voltage detector */
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
-  *        This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2
-  *           @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Enable the EWUPx pin */
-  *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *        This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2
-  *           @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Disable the EWUPx pin */
-  *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enters Sleep mode.
-  * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
-  *         This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
-  *           When WFI entry is used, tick interrupt have to be disabled if not desired as
-  *           the interrupt wake up source.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
-
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-}
-
-/**
-  * @brief Enters Stop mode.
-  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note  When exiting Stop mode by using an interrupt or a wakeup event,
-  *        MSI RC oscillator is selected as system clock.
-  * @note  When the voltage regulator operates in low power mode, an additional
-  *         startup delay is incurred when waking up from Stop mode.
-  *         By keeping the internal regulator ON during Stop mode, the consumption
-  *         is higher although the startup time is reduced.
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note  In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available)
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
-  *            Alarm out, or RTC clock calibration out.
-  *          - WKUP pin 1 (PA0) if enabled.
-  *          - WKUP pin 2 (PC13) if enabled.
-  *          - WKUP pin 3 (PE6) if enabled.
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  SET_BIT(PWR->CR, PWR_CR_PDDS);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-
-/**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
-  *       re-enters SLEEP mode when an interruption handling is over.
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
-  * @brief Enables CORTEX M3 SEVONPEND bit.
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
-  * @brief Disables CORTEX M3 SEVONPEND bit.
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-
-/**
-  * @brief  This function handles the PWR PVD interrupt request.
-  * @note   This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c
deleted file mode 100644
index e3580ec2899..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief    PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
-  * @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions
-  * @brief    Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return Voltage Scaling Range.
-  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
-  */
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return  (PWR->CR & PWR_CR_VOS);
-}
-
-
-/**
-  * @brief  Enables the Fast WakeUp from Ultra Low Power mode.
-  * @note   This bit works in conjunction with ULP bit.
-  *         Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when
-  *         exiting from low power mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFastWakeUp(void)
-{
-  /* Enable the fast wake up */
-  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Fast WakeUp from Ultra Low Power mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFastWakeUp(void)
-{
-  /* Disable the fast wake up */
-  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Enables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_EnableUltraLowPower(void)
-{
-  /* Enable the Ultra Low Power mode */
-  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_DisableUltraLowPower(void)
-{
-  /* Disable the Ultra Low Power mode */
-  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Enters the Low Power Run mode.
-  * @note   Low power run mode can only be entered when VCORE is in range 2.
-  *         In addition, the dynamic voltage scaling must not be used when Low
-  *         power run mode is selected. Only Stop and Sleep modes with regulator
-  *         configured in Low power mode is allowed when Low power run mode is
-  *         selected.
-  * @note   In Low power run mode, all I/O pins keep the same state as in Run mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableLowPowerRunMode(void)
-{
-  /* Enters the Low Power Run mode */
-  *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE;
-  *(__IO uint32_t *) CR_LPRUN_BB  = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Exits the Low Power Run mode.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
-{
-  /* Exits the Low Power Run mode */
-  *(__IO uint32_t *) CR_LPRUN_BB  = (uint32_t)DISABLE;
-  *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c
deleted file mode 100644
index 7be986e85b2..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c
+++ /dev/null
@@ -1,1394 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]
-      After reset the device is running from multispeed internal oscillator clock
-      (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled,
-      and all peripherals are off except internal SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
-          all peripherals mapped on these buses are running at MSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-    [..] Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings
-      (+) Configure the AHB and APB buses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals whose clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
-          (*) SDIO only for STM32L1xxxD devices
-
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */
-extern const uint8_t PLLMulTable[];          /* Defined in CMSIS (system_stm32l0xx.c)*/
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_Private_Functions RCC Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-  @verbatim
-  ===============================================================================
-           ##### Initialization and de-initialization functions #####
-  ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
-      and APB2).
-
-    [..] Internal/external clock and PLL configuration
-      (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz,
-          131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.
-
-      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-          the PLL as System clock source.
-      (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC
-          clock source.
-
-      (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or
-          through the PLL as System clock source. Can be used also as RTC clock source.
-
-      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
-      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
-        (++) The first output is used to generate the high speed system clock (up to 32 MHz)
-        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
-
-      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-          and if a HSE clock failure occurs(HSE used directly or through PLL as System
-          clock source), the System clocks automatically switched to MSI and an interrupt
-          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
-          (Non-Maskable Interrupt) exception vector.
-
-      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE,
-          HSE or PLL clock (through a configurable prescaler) on PA8 pin.
-
-    [..] System, AHB and APB buses clocks configuration
-      (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
-          HSE and PLL.
-          The AHB clock (HCLK) is derived from System clock through configurable
-          prescaler and used to clock the CPU, memory and peripherals mapped
-          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
-          from AHB clock through configurable prescalers and used to clock
-          the peripherals mapped on these buses. You can use
-          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
-      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RTC_ENABLE()
-              macros to configure this clock.
-          (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG()
-              macros to configure this clock.
-          (+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz
-              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
-
-          (+@) IWDG clock which is always the LSI clock.
-
-      (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz
-          and PCLK1 32 MHz. Depending on the device voltage range, the maximum
-          frequency should be adapted accordingly.
-  @endverbatim
-  * @{
-  */
-
-/*
-  Additional consideration on the HCLK based on Latency settings:
-  +----------------------------------------------------------------------+
-  | Latency       |                HCLK clock frequency (MHz)            |
-  |               |------------------------------------------------------|
-  |               | voltage range 1  | voltage range 2 | voltage range 3 |
-  |               |      1.8 V       |     1.5 V       |      1.2 V      |
-  |---------------|------------------|-----------------|-----------------|
-  |0WS(1CPU cycle)| 0 < HCLK <= 16   | 0 < HCLK <= 8   | 0 < HCLK <= 2   |
-  |---------------|------------------|-----------------|-----------------|
-  |1WS(2CPU cycle)| 16 < HCLK <= 32  | 8 < HCLK <= 16  | 2 < HCLK <= 4   |
-  +----------------------------------------------------------------------+
-
-  The following table gives the different clock source frequencies depending on the product
-  voltage range:
-  +------------------------------------------------------------------------------------------+
-  | Product voltage |                    Clock frequency                                     |
-  |                 |------------------|-----------------------------|-----------------------|
-  |      range      |   MSI   |   HSI  |              HSE            |          PLL          |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) |         32 MHz        |
-  |                 |         |        |      or 24 MHz (crystal)    | (PLLVCO max = 96 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 2 (1.5 V) | 4.2 MHz | 16 MHz |         16 MHz              |         16 MHz        |
-  |                 |         |        |                             | (PLLVCO max = 48 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|
-  | Range 3 (1.2 V) | 4.2 MHz |   NA   |         8 MHz               |           4 MHz       |
-  |                 |         |        |                             | (PLLVCO max = 24 MHz) |
-  +------------------------------------------------------------------------------------------+
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - MSI ON and used as system clock source
-  *            - HSI, HSE and PLL  OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS and MCO1 OFF
-  *            - All interrupts disabled
-  * @note   This function does not modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef status;
-
-  /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */
-  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \
-            ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5));
-
-  /* Set MSION bit */
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till MSI is ready */
-  while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Switch SYSCLK to MSI*/
-  CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-
-  /* Wait till MSI as SYSCLK status is ready */
-  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = MSI_VALUE;
-
-  /* Configure the source of time base considering new system clock settings  */
-  status = HAL_InitTick(uwTickPrio);
-  if(status != HAL_OK)
-  {
-    return status;
-  }
-
-  /* Reset HSION, HSEON, CSSON & PLLON bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-
-  /* Wait till PLL is not ready */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR);
-
-  /* Clear all flags */
-#if defined(RCC_LSECSS_SUPPORT)
-  WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC |  RCC_CIR_LSECSSC | RCC_CIR_CSSC);
-#else
-  WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC |  RCC_CIR_CSSC);
-#endif
-
-  /* Clear all reset flags */
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this macro. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this macro. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef status;
-  uint32_t sysclk_source, pll_config;
-
-  /* Check the parameters */
-  if(RCC_OscInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
-  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
-  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
-
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
-    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
-    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
-       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
-        {
-           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
-       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- MSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
-  {
-    /* When the MSI is used as system clock it will not be disabled */
-    if(sysclk_source == RCC_CFGR_SWS_MSI)
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration and MSI range change are allowed */
-      else
-      {
-       /* Check MSICalibrationValue and MSIClockRange input parameters */
-        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
-        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-           must be correctly programmed according to the frequency of the CPU clock
-           (HCLK) and the supply voltage of the device. */
-        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
-        {
-          /* First increase number of wait states update if necessary */
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-        }
-        else
-        {
-          /* Else, keep current flash latency while decreasing applies */
-          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
-          /* Decrease number of wait states update if necessary */
-          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
-          {
-            return HAL_ERROR;
-          }
-        }
-
-        /* Update the SystemCoreClock global variable */
-        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
-                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-
-        /* Configure the source of time base considering new system clocks settings*/
-        status = HAL_InitTick(uwTickPrio);
-        if(status != HAL_OK)
-        {
-          return status;
-        }
-      }
-    }
-    else
-    {
-      /* Check MSI State */
-      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
-
-      /* Check the MSI State */
-      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
-      {
-        /* Enable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-        /* Check MSICalibrationValue and MSIClockRange input parameters */
-        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
-
-        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
-        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-
-      }
-      else
-      {
-        /* Disable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till MSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is disabled */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is disabled */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Require to disable power clock if necessary */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLMUL,
-                             RCC_OscInitStruct->PLL.PLLDIV);
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Check if there is a request to disable the PLL used as System clock source */
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Do not return HAL_ERROR if request repeats the current configuration */
-        pll_config = RCC->CFGR;
-        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
-           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
-        {
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency FLASH Latency
-  *          The value of this parameter depend on device used within the same series
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The MSI is used (enabled by hardware) as system clock source after
-  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after start-up delay or PLL locked).
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready.
-  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
-  *         currently used as system clock source.
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef status;
-
-  /* Check the parameters */
-  if(RCC_ClkInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  assert_param(IS_FLASH_LATENCY(FLatency));
-
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-  must be correctly programmed according to the frequency of the CPU clock
-  (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > __HAL_FLASH_GET_LATENCY())
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-    {
-      /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* MSI is selected as System Clock Source */
-    else
-    {
-      /* Check the MSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
-      {
-        return HAL_ERROR;
-      }
-    }
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-    {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < __HAL_FLASH_GET_LATENCY())
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
-
-  /* Configure the source of time base considering new system clocks settings*/
-  status = HAL_InitTick(uwTickPrio);
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
-  *  @brief   RCC clocks control functions
-  *
-  @verbatim
-  ===============================================================================
-                  ##### Peripheral Control functions #####
-  ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO pin.
-  * @note   MCO pin should be configured in alternate function mode.
-  * @param  RCC_MCOx specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
-  * @param  RCC_MCOSource specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_MSI         MSI oscillator clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLL clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSI         LSI clock selected as MCO clock
-  *            @arg @ref RCC_MCO1SOURCE_LSE         LSE clock selected as MCO clock
-  * @param  RCC_MCODiv specifies the MCO DIV.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
-  *            @arg @ref RCC_MCODIV_2  division by 2 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_4  division by 4 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_8  division by 8 applied to MCO clock
-  *            @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef gpio;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
-  /* Configure the MCO1 pin in alternate function mode */
-  gpio.Mode      = GPIO_MODE_AF_PP;
-  gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
-  gpio.Pull      = GPIO_NOPULL;
-  gpio.Pin       = MCO1_PIN;
-  gpio.Alternate = GPIO_AF0_MCO;
-
-  /* MCO1 Clock Enable */
-  MCO1_CLK_ENABLE();
-
-  HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-
-  /* Configure the MCO clock source */
-  __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
-}
-
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to
-  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Clock Security System.
-  * @retval None
-  */
-void HAL_RCC_DisableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Returns the SYSCLK frequency
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is MSI, function returns a value based on MSI
-  *             Value as defined by the MSI range.
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**)
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value
-  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baud-rate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
-
-  tmpreg = RCC->CFGR;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (tmpreg & RCC_CFGR_SWS)
-  {
-    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
-    {
-      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
-      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
-      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
-      }
-      sysclockfreq = pllvco;
-      break;
-    }
-    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
-    default: /* MSI used as system clock */
-    {
-      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
-      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
-}
-
-/**
-  * @brief  Returns the PCLK2 frequency
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Check the parameters */
-  assert_param(RCC_OscInitStruct != (void *)NULL);
-
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
-                  | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;
-
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
-
-  /* Get the MSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
-  }
-
-  RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
-  RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
-  RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV);
-}
-
-/**
-  * @brief  Get the RCC_ClkInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
-  * contains the current clock configuration.
-  * @param  pFLatency Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Check the parameters */
-  assert_param(RCC_ClkInitStruct != (void *)NULL);
-  assert_param(pFLatency != (void *)NULL);
-
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  /* Get the SYSCLK configuration --------------------------------------------*/
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
-  /* Get the HCLK configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
-  /* Get the APB1 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
-  /* Get the APB2 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/
-  *pFLatency = __HAL_FLASH_GET_LATENCY();
-}
-
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval none
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-    the HAL_RCC_CSSCallback could be implemented in the user file
-    */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Update number of Flash wait states in line with MSI range and current
-            voltage range
-  * @param  MSIrange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
-{
-  uint32_t vos;
-  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
-
-  /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
-  if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
-  {
-    if(__HAL_RCC_PWR_IS_CLK_ENABLED())
-    {
-      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
-    }
-    else
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-
-    /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
-    if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
-    {
-      latency = FLASH_LATENCY_1; /* 1WS */
-    }
-  }
-
-  __HAL_FLASH_SET_LATENCY(latency);
-
-  /* Check that the new number of wait states is taken into account to access the Flash
-     memory by reading the FLASH_ACR register */
-  if(__HAL_FLASH_GET_LATENCY() != latency)
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c
deleted file mode 100644
index 5b900414706..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCC Extension HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- *  @brief  Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-    [..]
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in
-        order to modify the RTC Clock source, as consequence RTC registers (including
-        the backup registers) are set to their reset values.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
-  * @retval HAL status
-  * @note   If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
-  *         to possibly update HSE divider.
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart;
-  uint32_t temp_reg;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*------------------------------- RTC/LCD Configuration ------------------------*/
-  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-#if defined(LCD)
-   || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-#endif /* LCD */
-     )
-  {
-    /* check for RTC Parameters used to output RTCCLK */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-    {
-      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-    }
-
-#if defined(LCD)
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-    {
-      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
-    }
-#endif /* LCD */
-
-    FlagStatus       pwrclkchanged = RESET;
-
-    /* As soon as function is called to change RTC clock source, activation of the
-       power domain is done. */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
-    temp_reg = (RCC->CR & RCC_CR_RTCPRE);
-    if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
-#if defined (LCD)
-     || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
-#endif /* LCD */
-       )
-    { /* Check HSE State */
-      if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-        {
-          /* To update HSE divider, first switch-OFF HSE clock oscillator*/
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
-
-    if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
-      && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-#if defined(LCD)
-      || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
-       && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
-#endif /* LCD */
-     ))
-    {
-      /* Store the content of CSR register before the reset of Backup Domain */
-      temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
-
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-
-      /* Restore the Content of CSR register */
-      RCC->CSR = temp_reg;
-
-       /* Wait for LSERDY if LSE was enabled */
-      if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-#if defined(LCD)
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-    {
-      __HAL_RCC_LCD_CONFIG(PeriphClkInit->LCDClockSelection);
-    } 
-#endif /* LCD */
-
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-    {
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-    }
-
-    /* Require to disable power clock if necessary */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the PeriphClkInit according to the internal RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t srcclk;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
-#if defined(LCD)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
-#endif /* LCD */
-
-  /* Get the RTC/LCD configuration -----------------------------------------------*/
-  srcclk = __HAL_RCC_GET_RTC_SOURCE();
-  if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
-  {
-    /* Source clock is LSE or LSI*/
-    PeriphClkInit->RTCClockSelection = srcclk;
-  }
-  else
-  {
-    /* Source clock is HSE. Need to get the prescaler value*/
-    PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
-  }
-#if defined(LCD)
-  PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
-#endif /* LCD */
-}
-
-/**
-  * @brief  Return the peripheral clock frequency
-  * @note   Return 0 if peripheral clock is unknown
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PERIPHCLK_RTC      RTC peripheral clock
-  *            @arg @ref RCC_PERIPHCLK_LCD      LCD peripheral clock (*)
-  * @note   (*) means that this peripheral is not present on all the devices
-  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t frequency = 0;
-  uint32_t srcclk;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_RTC:
-#if defined(LCD)
-  case RCC_PERIPHCLK_LCD:
-#endif /* LCD */
-    {
-      /* Get the current RTC source */
-      srcclk = __HAL_RCC_GET_RTC_SOURCE();
-
-      /* Check if LSE is ready if RTC clock selection is LSE */
-      if (srcclk == RCC_RTCCLKSOURCE_LSE)
-      {
-        if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
-        {
-          frequency = LSE_VALUE;
-        }
-      }
-      /* Check if LSI is ready if RTC clock selection is LSI */
-      else if (srcclk == RCC_RTCCLKSOURCE_LSI)
-      {
-        if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
-        {
-          frequency = LSI_VALUE;
-        }
-      }
-      /* Check if HSE is ready and if RTC clock selection is HSE */
-      else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)
-      {
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-        {
-          /* Get the current HSE clock divider */
-          switch (__HAL_RCC_GET_RTC_HSE_PRESCALER())
-          {
-            case RCC_RTC_HSE_DIV_16:  /* HSE DIV16 has been selected */
-            {
-              frequency = HSE_VALUE / 16U;
-              break;
-            }
-            case RCC_RTC_HSE_DIV_8:   /* HSE DIV8 has been selected  */
-            {
-              frequency = HSE_VALUE / 8U;
-              break;
-            }
-            case RCC_RTC_HSE_DIV_4:   /* HSE DIV4 has been selected  */
-            {
-              frequency = HSE_VALUE / 4U;
-              break;
-            }
-            default:                  /* HSE DIV2 has been selected  */
-            {
-              frequency = HSE_VALUE / 2U;
-              break;
-            }
-          }
-        }
-      }
-      else
-      {
-        /* No clock source, frequency default init at 0 */
-      }
-      break;
-    }
-
-  default:
-    break;
-  }
-
-  return(frequency);
-}
-
-#if defined(RCC_LSECSS_SUPPORT)
-/**
-  * @brief  Enables the LSE Clock Security System.
-  * @note   If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
-  *         to the RTC but no hardware action is made to the registers.
-  *         In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
-  *         the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
-  *         The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
-  *         (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
-  *         RTCSEL), or take any required action to secure the application.
-  * @note   LSE CSS available only for high density and medium+ devices
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS(void)
-{
-  *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the LSE Clock Security System.
-  * @note   Once enabled this bit cannot be disabled, except after an LSE failure detection
-  *         (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
-  *         Reset by power on reset and RTC software reset (RTCRST bit).
-  * @note   LSE CSS available only for high density and medium+ devices
-  * @retval None
-  */
-void HAL_RCCEx_DisableLSECSS(void)
-{
-  /* Disable LSE CSS */
-  *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
-
-  /* Disable LSE CSS IT */
-  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
-}
-
-/**
-  * @brief  Enable the LSE Clock Security System IT & corresponding EXTI line.
-  * @note   LSE Clock Security System IT is mapped on RTC EXTI line 19
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS_IT(void)
-{
-  /* Enable LSE CSS */
-  *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
-
-  /* Enable LSE CSS IT */
-  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
-
-  /* Enable IT on EXTI Line 19 */
-  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
-  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
-}
-
-/**
-  * @brief Handle the RCC LSE Clock Security System interrupt request.
-  * @retval None
-  */
-void HAL_RCCEx_LSECSS_IRQHandler(void)
-{
-  /* Check RCC LSE CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
-  {
-    /* RCC LSE Clock Security System interrupt user callback */
-    HAL_RCCEx_LSECSS_Callback();
-
-    /* Clear RCC LSE CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
-  }
-}
-
-/**
-  * @brief  RCCEx LSE Clock Security System interrupt callback.
-  * @retval none
-  */
-__weak void HAL_RCCEx_LSECSS_Callback(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
-   */
-}
-#endif /* RCC_LSECSS_SUPPORT */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c
deleted file mode 100644
index 1cdb4ef32dd..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c
+++ /dev/null
@@ -1,1944 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real Time Clock (RTC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + RTC Time and Date functions
-  *           + RTC Alarm functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
- ===============================================================================
-                          ##### RTC Operating Condition #####
- ===============================================================================
-  [..] The real-time clock (RTC) and the RTC backup registers can be powered
-       from the VBAT voltage when the main VDD supply is powered off.
-       To retain the content of the RTC backup registers and supply the RTC
-       when VDD is turned off, VBAT pin can be connected to an optional
-       standby voltage supplied by a battery or by another source.
-
-  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
-       off, the VBAT pin powers the following blocks:
-    (#) The RTC
-    (#) The LSE oscillator
-    (#) PC13 to PC15 I/Os (when available)
-
-  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
-       the following pins are available:
-    (#) PC14 and PC15 can be used as either GPIO or LSE pins
-    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-
-  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
-       because VDD is not present), the following pins are available:
-    (#) PC14 and PC15 can be used as LSE pins only
-    (#) PC13 can be used as the RTC_AF1 pin
-
-                   ##### Backup Domain Reset #####
- ===============================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
-       to their reset values.
-  [..] A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the
-        RCC Backup domain control register (RCC_BDCR).
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
-                   ##### Backup Domain Access #####
- ===================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data
-       registers and backup SRAM) is protected against possible unwanted write
-       accesses.
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (+) Enable the Power Controller (PWR) APB1 interface clock using the
-        __HAL_RCC_PWR_CLK_ENABLE() function.
-    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
-    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-
-
-                  ##### How to use RTC Driver #####
- ===================================================================
-  [..]
-    (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** Time and Date configuration ***
-  ===================================
-  [..]
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
-        and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
-            You can also configure the RTC Alarm with interrupt mode using the
-            HAL_RTC_SetAlarm_IT() function.
-    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
-       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending
-       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
-       or the RTC wakeup events.
-  [..] The RTC provides a programmable time base for waking up from the
-       Stop or Standby mode at regular intervals.
-       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
-       is LSE or LSI.
-
-  *** Callback registration ***
-  =============================================
-
-  [..]
-  The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-  Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
-
-  [..]
-  Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
-    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
-    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
-    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
-    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
-    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
-    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
-    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
-    (+) MspInitCallback              : RTC MspInit callback.
-    (+) MspDeInitCallback            : RTC MspDeInit callback.
-  [..]
-  This function takes as parameters the HAL peripheral handle, the Callback ID
-  and a pointer to the user callback function.
-
-  [..]
-  Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-  This function allows to reset following callbacks:
-    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
-    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
-    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
-    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
-    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
-    (+) Tamper2EventCallback         : RTC Tamper 2 Event callback.
-    (+) Tamper3EventCallback         : RTC Tamper 3 Event callback.
-    (+) MspInitCallback              : RTC MspInit callback.
-    (+) MspDeInitCallback            : RTC MspDeInit callback.
-
-  [..]
-  By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
-  all callbacks are set to the corresponding weak functions :
-  examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
-  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
-  in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
-  (not registered beforehand).
-  If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
-  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-  [..]
-  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
-  Exception done MspInit/MspDeInit that can be registered/unregistered
-  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
-  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
-  or @ref HAL_RTC_Init() function.
-
-  [..]
-  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
-  not defined, the callback registration feature is not available and all callbacks
-  are set to the corresponding weak functions.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-
-/** @addtogroup RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
-         RTC registers Write protection, enter and exit the RTC initialization mode,
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter
-             initialization mode. In this mode, the calendar counter is stopped
-             and its value can be updated. When the initialization sequence is
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar
-             initialization, calendar update or after wakeup from low power modes
-             the software must first clear the RSF flag. The software must then
-             wait until it is set again before reading the calendar, which means
-             that the calendar registers have been correctly copied into the
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
-             implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the RTC peripheral
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if (hrtc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  if (hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-
-    hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
-    hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
-    hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
-    hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
-    hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;     /* Legacy weak Tamper2EventCallback     */
-    hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;     /* Legacy weak Tamper3EventCallback     */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-    if (hrtc->MspInitCallback == NULL)
-    {
-      hrtc->MspInitCallback = HAL_RTC_MspInit;
-    }
-    /* Init the low level hardware */
-    hrtc->MspInitCallback(hrtc);
-
-    if (hrtc->MspDeInitCallback == NULL)
-    {
-      hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-    }
-  }
-#else
-  if (hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hrtc->Lock = HAL_UNLOCKED;
-
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-#if defined (RTC_CR_BYPSHAD)
-    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-#endif /* RTC_CR_BYPSHAD */
-    {
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
-    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitialize the RTC peripheral.
-  * @param  hrtc RTC handle
-  * @note   This function does not reset the RTC Backup Data registers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = 0x00000000U;
-    hrtc->Instance->DR = 0x00002101U;
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= 0x00000007U;
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= 0x00000000U;
-    hrtc->Instance->WUTR = 0x0000FFFFU;
-    hrtc->Instance->PRER = 0x007F00FFU;
-    hrtc->Instance->CALIBR = 0x00000000U;
-    hrtc->Instance->ALRMAR = 0x00000000U;
-    hrtc->Instance->ALRMBR = 0x00000000U;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    hrtc->Instance->SHIFTR = 0x00000000U;
-    hrtc->Instance->CALR = 0x00000000U;
-    hrtc->Instance->ALRMASSR = 0x00000000U;
-    hrtc->Instance->ALRMBSSR = 0x00000000U;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = 0x00000000U;
-
-    /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAFCR = 0x00000000U;
-
-    /* Wait for synchro */
-    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  if (hrtc->MspDeInitCallback == NULL)
-  {
-    hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-  }
-
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  hrtc->MspDeInitCallback(hrtc);
-
-#else
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-  hrtc->State = HAL_RTC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User RTC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hrtc RTC handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
-  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
-  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
-  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
-  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
-  *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
-  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hrtc);
-
-  if (HAL_RTC_STATE_READY == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_ALARM_A_EVENT_CB_ID :
-        hrtc->AlarmAEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_ALARM_B_EVENT_CB_ID :
-        hrtc->AlarmBEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
-        hrtc->TimeStampEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
-        hrtc->WakeUpTimerEventCallback = pCallback;
-        break;
-
-      case HAL_RTC_TAMPER1_EVENT_CB_ID :
-        hrtc->Tamper1EventCallback = pCallback;
-        break;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-      case HAL_RTC_TAMPER2_EVENT_CB_ID :
-        hrtc->Tamper2EventCallback = pCallback;
-        break;
-
-      case HAL_RTC_TAMPER3_EVENT_CB_ID :
-        hrtc->Tamper3EventCallback = pCallback;
-        break;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RTC_STATE_RESET == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an RTC Callback
-  *         RTC callabck is redirected to the weak predefined callback
-  * @param  hrtc RTC handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
-  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
-  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
-  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      WakeUp Timer Event Callback ID
-  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID          Tamper 2 Callback ID
-  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID          Tamper 3 Callback ID
-  *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
-  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hrtc);
-
-  if (HAL_RTC_STATE_READY == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_ALARM_A_EVENT_CB_ID :
-        hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
-        break;
-
-      case HAL_RTC_ALARM_B_EVENT_CB_ID :
-        hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
-        break;
-
-      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
-        hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
-        break;
-
-      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
-        hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
-        break;
-
-      case HAL_RTC_TAMPER1_EVENT_CB_ID :
-        hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
-        break;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-      case HAL_RTC_TAMPER2_EVENT_CB_ID :
-        hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;         /* Legacy weak Tamper2EventCallback         */
-        break;
-
-      case HAL_RTC_TAMPER3_EVENT_CB_ID :
-        hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
-        break;
-#endif
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = HAL_RTC_MspInit;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_RTC_STATE_RESET == hrtc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_RTC_MSPINIT_CB_ID :
-        hrtc->MspInitCallback = HAL_RTC_MspInit;
-        break;
-
-      case HAL_RTC_MSPDEINIT_CB_ID :
-        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return status;
-}
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Initialize the RTC MSP.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitialize the RTC MSP.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
- *  @brief   RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set RTC current time.
-  * @param  hrtc RTC handle
-  * @param  sTime Pointer to Time structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16U));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    }
-    else
-    {
-      sTime->TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
-              ((uint32_t)(sTime->Minutes) << 8U) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16U));
-  }
-  UNUSED(tmpreg);
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
-    /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
-    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
-
-    /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* Wait for synchro */
-    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY;
-
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current time.
-  * @param  hrtc RTC handle
-  * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
-  *                with input format (BIN or BCD), also SubSeconds field (if availabale) returning the
-  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
-  *                factor to be used for second fraction ratio computation.
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note  If available, you can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
-  *        value in second fraction ratio with time unit following generic formula:
-  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
-  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
-  *        to ensure consistency between the time and date values.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Get subseconds structure field from the corresponding register*/
-  sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS);
-
-  /* Get SecondFraction structure field from the corresponding register field*/
-  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set RTC current date.
-  * @param  hrtc RTC handle
-  * @param  sDate Pointer to date structure
-  * @param  Format specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format
-  *            @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
-  }
-
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date));
-
-    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
-                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
-                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                  ((uint32_t)sDate->WeekDay << 13U));
-  }
-  else
-  {
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
-    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
-
-    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
-                  (((uint32_t)sDate->Month) << 8U) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13U));
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-    /* Wait for synchro */
-    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    hrtc->State = HAL_RTC_STATE_READY ;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  Get RTC current date.
-  * @param  hrtc RTC handle
-  * @param  sDate Pointer to Date structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format
-  *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Daylight Saving Time, adda one hour to the calendar in one
-  *         single operation without going through the initialization procedure.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, subtracts one hour from the calendar in one
-  *         single operation without going through the initialization procedure.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, sets the store operation bit.
-  * @note   It can be used by the software in order to memorize the DST status.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, clears the store operation bit.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-}
-
-/**
-  * @brief  Daylight Saving Time, reads the store operation bit.
-  * @param  hrtc RTC handle
-  * @retval operation see RTC_StoreOperation_Definitions
-  */
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
-{
-  return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
- *  @brief   RTC Alarm functions
- *
-@verbatim
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Set the specified RTC Alarm.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Alarm structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart;
-  uint32_t tmpreg;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t subsecondtmpreg = 0;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if (sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified RTC Alarm with Interrupt.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Alarm structure
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).
-  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t subsecondtmpreg = 0;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-  else
-  {
-    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
-    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));
-  }
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if (sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
-  __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the specified RTC Alarm.
-  * @param  hrtc RTC handle
-  * @param  Alarm Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  if (Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* In case of interrupt mode is used, the interrupt source must disabled */
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RTC Alarm value and masks.
-  * @param  hrtc RTC handle
-  * @param  sAlarm Pointer to Date structure
-  * @param  Alarm Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB
-  * @param  Format Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  uint32_t subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_ALARM(Alarm));
-
-  if (Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  }
-
-  /* Fill the structure with the read parameters */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
-  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
-  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
-  if (Format == RTC_FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle Alarm interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the AlarmA interrupt source enable status */
-  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
-  {
-    /* Get the pending status of the AlarmA Interrupt */
-    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
-    {
-      /* AlarmA callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->AlarmAEventCallback(hrtc);
-#else
-      HAL_RTC_AlarmAEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the AlarmA interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-    }
-  }
-
-  /* Get the AlarmB interrupt source enable status */
-  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
-  {
-    /* Get the pending status of the AlarmB Interrupt */
-    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
-    {
-      /* AlarmB callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->AlarmBEventCallback(hrtc);
-#else
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the AlarmB interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-    }
-  }
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle AlarmA Polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group4
- *  @brief   Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-#if defined (RTC_CR_BYPSHAD)
-  /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-  if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-#endif /* RTC_CR_BYPSHAD */
-  {
-    /* Clear RSF flag */
-    hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
-    tickstart = HAL_GetTick();
-
-    /* Wait the registers to be synchronised */
-    while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group5
- *  @brief   Peripheral State functions
- *
-@verbatim
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Return the RTC handle state.
-  * @param  hrtc RTC handle
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
-{
-  /* Return RTC handle state */
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Private_Functions
-  * @{
-  */
-/**
-  * @brief  Enter the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Check if the Initialization mode is set */
-  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Convert a 2 digit decimal to BCD format.
-  * @param  Value Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0U;
-  uint8_t Param = Value;
-
-  while (Param >= 10U)
-  {
-    bcdhigh++;
-    Param -= 10U;
-  }
-
-  return ((uint8_t)(bcdhigh << 4U) | Param);
-}
-
-/**
-  * @brief  Convert from 2 digit BCD to Binary.
-  * @param  Value BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp;
-  tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
-  return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c
deleted file mode 100644
index 6d06b39883d..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c
+++ /dev/null
@@ -1,1806 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended RTC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Real Time Clock (RTC) Extended peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions
-  *           + RTC Wake-up functions
-  *           + Extended Control functions
-  *           + Extended RTC features functions
-  *
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
-        format using the HAL_RTC_Init() function.
-
-  *** RTC Wakeup configuration ***
-  ================================
-  [..]
-    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
-        function. You can also configure the RTC Wakeup timer with interrupt mode
-        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
-        function.
-
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
-        HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
-        interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
-        function.
-    (+) The TIMESTAMP alternate function can be mapped to RTC_AF1 (PC13).
-
-  *** Tamper configuration ***
-  ============================
-  [..]
-    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
-        or Level according to the Tamper filter (if equal to 0 Edge else Level)
-        value, sampling frequency, precharge or discharge and Pull-UP using the
-        HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
-        mode using HAL_RTCEx_SetTamper_IT() function.
-    (+) The TAMPER1 alternate function can be mapped to RTC_AF1 (PC13).
-
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
-        function.
-    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
-        function.
-
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @brief RTC Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup RTCEx_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
-  * @brief    RTC TimeStamp and Tamper functions
-  *
-@verbatim
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  hrtc RTC handle
-  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set TimeStamp with Interrupt.
-  * @param  hrtc RTC handle
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
-  *                                         falling edge of the related pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable IT timestamp */
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
-
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate TimeStamp.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RTC TimeStamp value.
-  * @param  hrtc RTC handle
-  * @param  sTimeStamp Pointer to Time structure
-  * @param  sTimeStampDate Pointer to Date structure
-  * @param  Format specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format
-  *             @arg RTC_FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime, tmpdate;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0U;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
-
-  /* Check the input parameters format */
-  if (Format == RTC_FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-
-  /* Clear the TIMESTAMP Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers.
-  * @param  hrtc RTC handle
-  * @param  sTamper Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE))
-  {
-    /* Configure the RTC_TAFCR register */
-    sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
-  }
-  else
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
-            (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS | \
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
-#else
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Trigger));
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG);
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  hrtc->Instance->TAFCR |= tmpreg;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc RTC handle
-  * @param  sTamper Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
-{
-  uint32_t tmpreg;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
-  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Configure the tamper trigger */
-  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE))
-  {
-    sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
-  }
-  else
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
-            (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS | \
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS);
-#else
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-  hrtc->Instance->TAFCR |= tmpreg;
-
-  /* Configure the Tamper Interrupt in the RTC_TAFCR */
-  hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate Tamper.
-  * @param  hrtc RTC handle
-  * @param  Tamper Selected tamper pin.
-  *          This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_RTC_TAMPER(Tamper));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the selected Tamper pin */
-  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle TimeStamp interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the TimeStamp interrupt source enable status */
-  if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
-  {
-    /* Get the pending status of the TIMESTAMP Interrupt */
-    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
-    {
-      /* TIMESTAMP callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->TimeStampEventCallback(hrtc);
-#else
-      HAL_RTCEx_TimeStampEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-    }
-  }
-
-  /* Get the Tamper1 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
-  {
-    /* Get the pending status of the Tamper1 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
-    {
-      /* Tamper1 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper1EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper1 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-    }
-  }
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Get the Tamper2 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U)
-  {
-    /* Get the pending status of the Tamper2 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
-    {
-      /* Tamper2 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper2EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper2 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-
-  /* Get the Tamper3 interrupts source enable status */
-  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U)
-  {
-    /* Get the pending status of the Tamper3 Interrupt */
-    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
-    {
-      /* Tamper3 callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-      hrtc->Tamper3EventCallback(hrtc);
-#else
-      HAL_RTCEx_Tamper3EventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-      /* Clear the Tamper3 interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-    }
-  }
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  TimeStamp callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Tamper 1 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
-   */
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Tamper 2 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tamper 3 callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
-   */
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @brief  Handle TimeStamp polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
-  {
-    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
-    {
-      /* Clear the TIMESTAMP OverRun Flag */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-      /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle Tamper 1 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Handle Tamper 2 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle Tamper 3 Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
-  * @brief    RTC Wake-up functions
-  *
-@verbatim
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set wake up timer.
-  * @param  hrtc RTC handle
-  * @param  WakeUpCounter Wake up counter
-  * @param  WakeUpClock Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set wake up timer with interrupt.
-  * @param  hrtc RTC handle
-  * @param  WakeUpCounter Wake up counter
-  * @param  WakeUpClock Wake up clock
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U)
-    {
-      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Disable the Wake-Up timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Clear flag Wake-Up */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
-  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate wake up timer counter.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Disable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
-
-  tickstart = HAL_GetTick();
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get wake up timer counter.
-  * @param  hrtc RTC handle
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
-  * @brief  Handle Wake Up Timer interrupt request.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the pending status of the WAKEUPTIMER Interrupt */
-  if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
-  {
-    /* WAKEUPTIMER callback */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    hrtc->WakeUpTimerEventCallback(hrtc);
-#else
-    HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-    /* Clear the WAKEUPTIMER interrupt pending bit */
-    __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  }
-
-
-  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
-  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle Wake Up Timer Polling.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim
- ===============================================================================
-              ##### Extended Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Write a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Set the Coarse calibration parameters.
-      (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
-      (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enable the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Write a data in a specified RTC Backup data register.
-  * @param  hrtc RTC handle
-  * @param  BackupRegister RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @param  Data Data to be written in the specified RTC Backup data register.
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc RTC handle
-  * @param  BackupRegister RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
-  *                                 specify the register.
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4U);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @brief  Sets the Coarse calibration parameters.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  CalibSign Specifies the sign of the coarse calibration value.
-  *          This parameter can be  one of the following values :
-  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
-  *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
-  * @param  Value value of coarse calibration expressed in ppm (coded on 5 bits).
-  *
-  * @note   This Calibration value should be between 0 and 63 when using negative
-  *         sign with a 2-ppm step.
-  *
-  * @note   This Calibration value should be between 0 and 126 when using positive
-  *         sign with a 4-ppm step.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_SIGN(CalibSign));
-  assert_param(IS_RTC_CALIB_VALUE(Value));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
-
-    /* Set the coarse calibration value */
-    hrtc->Instance->CALIBR = (uint32_t)(CalibSign | Value);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Coarse calibration parameters.
-  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Set the Smooth calibration parameters.
-  * @param  hrtc RTC handle
-  * @param  SmoothCalibPeriod Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
-  * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
-  *         SmoothCalibMinusPulsesValue mut be equal to 0.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* check if a calibration is pending*/
-  if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
-  {
-    tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
-    {
-      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register.
-  * @param  hrtc RTC handle
-  * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait until the shift is completed*/
-  while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Check if the reference clock detection is disabled */
-  if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
-  {
-    /* Configure the Shift settings */
-    hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
-    /* Wait for synchro */
-    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Change RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc RTC handle
-  * @param  CalibOutput : Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
-#else
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB).
-  * @param  hrtc  RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-{
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enable the RTC reference clock detection.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc RTC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-/**
-  * @brief  Enable the Bypass Shadow feature.
-  * @param  hrtc RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the Bypass Shadow feature.
-  * @param  hrtc RTC handle
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @brief    Extended features functions
-  *
-@verbatim
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) RTC Alram B callback
-      (+) RTC Poll for Alarm B request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hrtc);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Handle Alarm B Polling request.
-  * @param  hrtc RTC handle
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c
deleted file mode 100644
index 9368895ecd2..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sd.c
+++ /dev/null
@@ -1,3231 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sd.c
-  * @author  MCD Application Team
-  * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Secure Digital (SD) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver implements a high level communication layer for read and write from/to
-    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
-    the user in HAL_SD_MspInit() function (MSP layer).
-    Basically, the MSP layer configuration should be the same as we provide in the
-    examples.
-    You can easily tailor this configuration according to hardware resources.
-
-  [..]
-    This driver is a generic layered driver for SDIO memories which uses the HAL
-    SDIO driver functions to interface with SD and uSD cards devices.
-    It is used as follows:
-
-    (#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:
-        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
-        (##) SDIO pins configuration for SD card
-            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
-                  and according to your pin assignment;
-        (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
-             and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
-        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
-            (+++) Configure the SDIO and DMA interrupt priorities using functions
-                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
-            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
-                  and __HAL_SD_DISABLE_IT() inside the communication process.
-            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
-                  and __HAL_SD_CLEAR_IT()
-        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
-             and HAL_SD_WriteBlocks_IT() APIs).
-            (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();
-            (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
-                  and __HAL_SD_DISABLE_IT() inside the communication process.
-            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
-                  and __HAL_SD_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
-
-  *** SD Card Initialization and configuration ***
-  ================================================
-  [..]
-    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
-    SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
-    This function provide the following operations:
-
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
-        type (Standard Capacity or High Capacity). You can change or adapt this
-        frequency by adjusting the "ClockDiv" field.
-        The SD Card frequency (SDIO_CK) is computed as follows:
-
-           SDIO_CK = SDIOCLK / (ClockDiv + 2)
-
-        In initialization mode and according to the SD Card standard,
-        make sure that the SDIO_CK frequency doesn't exceed 400KHz.
-
-        This phase of initialization is done through SDIO_Init() and
-        SDIO_PowerState_ON() SDIO low level APIs.
-
-    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
-        This phase allows the card initialization and identification
-        and check the SD Card type (Standard Capacity or High Capacity)
-        The initialization flow is compatible with SD standard.
-
-        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
-        of plug-off plug-in.
-
-    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
-        frequency by adjusting the "ClockDiv" field.
-        In transfer mode and according to the SD Card standard, make sure that the
-        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDIO
-        peripheral in bypass mode. Refer to the corresponding reference manual
-        for more details.
-
-    (#) Select the corresponding SD Card according to the address read with the step 2.
-
-    (#) Configure the SD Card in wide bus mode: 4-bits data.
-
-  *** SD Card Read operation ***
-  ==============================
-  [..]
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-
-    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-        You could also check the DMA transfer process through the SD Rx interrupt event.
-
-    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-        You could also check the IT transfer process through the SD Rx interrupt event.
-
-  *** SD Card Write operation ***
-  ===============================
-  [..]
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-
-    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-        You could also check the DMA transfer process through the SD Tx interrupt event.
-
-    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
-        This function support only 512-bytes block length (the block size should be
-        chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to ensure that the transfer is done correctly. The check is done
-        through HAL_SD_GetCardState() function for SD card state.
-        You could also check the IT transfer process through the SD Tx interrupt event.
-
-  *** SD card status ***
-  ======================
-  [..]
-    (+) The SD Status contains status bits that are related to the SD Memory
-        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
-
-  *** SD card information ***
-  ===========================
-  [..]
-    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
-        It returns useful information about the SD card such as block size, card type,
-        block number ...
-
-  *** SD card CSD register ***
-  ============================
-    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
-        Some of the CSD parameters are useful for card initialization and identification.
-
-  *** SD card CID register ***
-  ============================
-    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
-        Some of the CSD parameters are useful for card initialization and identification.
-
-  *** SD HAL driver macros list ***
-  ==================================
-  [..]
-    Below the list of most used macros in SD HAL driver.
-
-    (+) __HAL_SD_ENABLE : Enable the SD device
-    (+) __HAL_SD_DISABLE : Disable the SD device
-    (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
-    (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
-    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
-
-    (@) You can refer to the SD HAL driver header file for more useful macros
-
-  *** Callback registration ***
-  =============================================
-  [..]
-    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
-    it allows to register following callbacks:
-      (+) TxCpltCallback : callback when a transmission transfer is completed.
-      (+) RxCpltCallback : callback when a reception transfer is completed.
-      (+) ErrorCallback : callback when error occurs.
-      (+) AbortCpltCallback : callback when abort is completed.
-      (+) MspInitCallback    : SD MspInit.
-      (+) MspDeInitCallback  : SD MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function. It allows to reset following callbacks:
-      (+) TxCpltCallback : callback when a transmission transfer is completed.
-      (+) RxCpltCallback : callback when a reception transfer is completed.
-      (+) ErrorCallback : callback when error occurs.
-      (+) AbortCpltCallback : callback when abort is completed.
-      (+) MspInitCallback    : SD MspInit.
-      (+) MspDeInitCallback  : SD MspDeInit.
-    This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-    By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
-    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-    Exception done for MspInit and MspDeInit callbacks that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
-    and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-    Callbacks can be registered/unregistered in READY state only.
-    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-    during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
-    or @ref HAL_SD_Init function.
-
-    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registering feature is not available
-    and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#if defined(SDIO)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD
-  * @{
-  */
-
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_PowerOFF(SD_HandleTypeDef *hsd);
-static void SD_Write_IT(SD_HandleTypeDef *hsd);
-static void SD_Read_IT(SD_HandleTypeDef *hsd);
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMAError(DMA_HandleTypeDef *hdma);
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
- *
-@verbatim
-  ==============================================================================
-          ##### Initialization and de-initialization functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to initialize/de-initialize the SD
-    card device to be ready for use.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SD according to the specified parameters in the
-            SD_HandleTypeDef and create the associated handle.
-  * @param  hsd: Pointer to the SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
-{
-  /* Check the SD handle allocation */
-  if(hsd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
-  assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
-  assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
-  assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
-  assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
-  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
-  assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
-
-  if(hsd->State == HAL_SD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hsd->Lock = HAL_UNLOCKED;
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
-    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
-    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
-    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
-    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
-
-    if(hsd->MspInitCallback == NULL)
-    {
-      hsd->MspInitCallback = HAL_SD_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hsd->MspInitCallback(hsd);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_SD_MspInit(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-  }
-
-  hsd->State = HAL_SD_STATE_BUSY;
-
-  /* Initialize the Card parameters */
-  if (HAL_SD_InitCard(hsd) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Initialize the error code */
-  hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-  /* Initialize the SD operation */
-  hsd->Context = SD_CONTEXT_NONE;
-
-  /* Initialize the SD state */
-  hsd->State = HAL_SD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the SD Card.
-  * @param  hsd: Pointer to SD handle
-  * @note   This function initializes the SD card. It could be used when a card
-            re-initialization is needed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
-{
-  uint32_t errorstate;
-  HAL_StatusTypeDef status;
-  SD_InitTypeDef Init;
-  
-  /* Default SDIO peripheral configuration for SD card initialization */
-  Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
-  Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
-  Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  Init.BusWide             = SDIO_BUS_WIDE_1B;
-  Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
-  Init.ClockDiv            = SDIO_INIT_CLK_DIV;
-
-  /* Initialize SDIO peripheral interface with default configuration */
-  status = SDIO_Init(hsd->Instance, Init);
-  if(status != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Disable SDIO Clock */
-  __HAL_SD_DISABLE(hsd);
-
-  /* Set Power State to ON */
-  (void)SDIO_PowerState_ON(hsd->Instance);
-
-  /* Enable SDIO Clock */
-  __HAL_SD_ENABLE(hsd);
-
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->State = HAL_SD_STATE_READY;
-    hsd->ErrorCode |= errorstate;
-    return HAL_ERROR;
-  }
-
-  /* Card initialization */
-  errorstate = SD_InitCard(hsd);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->State = HAL_SD_STATE_READY;
-    hsd->ErrorCode |= errorstate;
-    return HAL_ERROR;
-  }
-
-  /* Set Block Size for Card */
-  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->ErrorCode |= errorstate;
-    hsd->State = HAL_SD_STATE_READY;
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-Initializes the SD card.
-  * @param  hsd: Pointer to SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
-  /* Check the SD handle allocation */
-  if(hsd == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
-
-  hsd->State = HAL_SD_STATE_BUSY;
-
-  /* Set SD power state to off */
-  SD_PowerOFF(hsd);
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-  if(hsd->MspDeInitCallback == NULL)
-  {
-    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
-  }
-
-  /* DeInit the low level hardware */
-  hsd->MspDeInitCallback(hsd);
-#else
-  /* De-Initialize the MSP layer */
-  HAL_SD_MspDeInit(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-
-  hsd->ErrorCode = HAL_SD_ERROR_NONE;
-  hsd->State = HAL_SD_STATE_RESET;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the SD MSP.
-  * @param  hsd: Pointer to SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize SD MSP.
-  * @param  hsd: Pointer to SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group2
- *  @brief   Data transfer functions
- *
-@verbatim
-  ==============================================================================
-                        ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the data
-    transfer from/to SD card.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer
-  *         is managed by polling mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @param  hsd: Pointer to SD handle
-  * @param  pData: pointer to the buffer that will contain the received data
-  * @param  BlockAdd: Block Address from where data is to be read
-  * @param  NumberOfBlocks: Number of SD blocks to read
-  * @param  Timeout: Specify timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t count, data, dataremaining;
-  uint32_t add = BlockAdd;
-  uint8_t *tempbuff = pData;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      add *= 512U;
-    }
-
-    /* Configure the SD DPSM (Data Path State Machine) */
-    config.DataTimeOut   = SDMMC_DATATIMEOUT;
-    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
-    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    config.DPSM          = SDIO_DPSM_ENABLE;
-    (void)SDIO_ConfigData(hsd->Instance, &config);
-
-    /* Read block(s) in polling mode */
-    if(NumberOfBlocks > 1U)
-    {
-      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
-      /* Read Multi Block command */
-      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
-    }
-    else
-    {
-      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
-      /* Read Single Block command */
-      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
-    }
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-
-    /* Poll on SDIO flags */
-    dataremaining = config.DataLength;
-    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-    {
-      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
-      {
-        /* Read data from SDIO Rx FIFO */
-        for(count = 0U; count < 8U; count++)
-        {
-          data = SDIO_ReadFIFO(hsd->Instance);
-          *tempbuff = (uint8_t)(data & 0xFFU);
-          tempbuff++;
-          dataremaining--;
-          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
-          tempbuff++;
-          dataremaining--;
-          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
-          tempbuff++;
-          dataremaining--;
-          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
-          tempbuff++;
-          dataremaining--;
-        }
-      }
-
-      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
-        hsd->State= HAL_SD_STATE_READY;
-        hsd->Context = SD_CONTEXT_NONE;
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Send stop transmission command in case of multiblock read */
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
-    {
-      if(hsd->SdCard.CardType != CARD_SECURED)
-      {
-        /* Send stop transmission command */
-        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          /* Clear all the static flags */
-          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-          hsd->ErrorCode |= errorstate;
-          hsd->State = HAL_SD_STATE_READY;
-          hsd->Context = SD_CONTEXT_NONE;
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Get error state */
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    /* Empty FIFO if there is still any data */
-    while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
-    {
-      data = SDIO_ReadFIFO(hsd->Instance);
-      *tempbuff = (uint8_t)(data & 0xFFU);
-      tempbuff++;
-      dataremaining--;
-      *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
-      tempbuff++;
-      dataremaining--;
-      *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
-      tempbuff++;
-      dataremaining--;
-      *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
-      tempbuff++;
-      dataremaining--;
-
-      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
-        hsd->State= HAL_SD_STATE_READY;
-        hsd->Context = SD_CONTEXT_NONE;
-        return HAL_ERROR;
-      }
-    }
-
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-    hsd->State = HAL_SD_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @param  hsd: Pointer to SD handle
-  * @param  pData: pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd: Block Address where data will be written
-  * @param  NumberOfBlocks: Number of SD blocks to write
-  * @param  Timeout: Specify timeout value
-  * @note   Due to limitation "SDIO hardware flow control" indicated in Errata Sheet :
-  *         In 4-bits bus wide mode, do not use this API otherwise underrun will occur and
-  *         there is not possibility to activate the flow control.
-  *         Use DMA mode when using 4-bits bus wide mode or decrease the frequency.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t count, data, dataremaining;
-  uint32_t add = BlockAdd;
-  uint8_t *tempbuff = pData;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      add *= 512U;
-    }
-
-    /* Configure the SD DPSM (Data Path State Machine) */
-    config.DataTimeOut   = SDMMC_DATATIMEOUT;
-    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
-    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    config.DPSM          = SDIO_DPSM_ENABLE;
-    (void)SDIO_ConfigData(hsd->Instance, &config);
-
-    /* Write Blocks in Polling mode */
-    if(NumberOfBlocks > 1U)
-    {
-      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
-      /* Write Multi Block command */
-      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
-    }
-    else
-    {
-      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
-      /* Write Single Block command */
-      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
-    }
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-
-    /* Write block(s) in polling mode */
-    dataremaining = config.DataLength;
-    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-    {
-      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
-      {
-        /* Write data to SDIO Tx FIFO */
-        for(count = 0U; count < 8U; count++)
-        {
-          data = (uint32_t)(*tempbuff);
-          tempbuff++;
-          dataremaining--;
-          data |= ((uint32_t)(*tempbuff) << 8U);
-          tempbuff++;
-          dataremaining--;
-          data |= ((uint32_t)(*tempbuff) << 16U);
-          tempbuff++;
-          dataremaining--;
-          data |= ((uint32_t)(*tempbuff) << 24U);
-          tempbuff++;
-          dataremaining--;
-          (void)SDIO_WriteFIFO(hsd->Instance, &data);
-        }
-      }
-
-      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        hsd->Context = SD_CONTEXT_NONE;
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send stop transmission command in case of multiblock write */
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
-    {
-      if(hsd->SdCard.CardType != CARD_SECURED)
-      {
-        /* Send stop transmission command */
-        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          /* Clear all the static flags */
-          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-          hsd->ErrorCode |= errorstate;
-          hsd->State = HAL_SD_STATE_READY;
-          hsd->Context = SD_CONTEXT_NONE;
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Get error state */
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-    hsd->State = HAL_SD_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer
-  *         is managed in interrupt mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @note   You could also check the IT transfer process through the SD Rx
-  *         interrupt event.
-  * @param  hsd: Pointer to SD handle
-  * @param  pData: Pointer to the buffer that will contain the received data
-  * @param  BlockAdd: Block Address from where data is to be read
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t add = BlockAdd;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    hsd->pRxBuffPtr = pData;
-    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
-    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
-
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      add *= 512U;
-    }
-
-    /* Configure the SD DPSM (Data Path State Machine) */
-    config.DataTimeOut   = SDMMC_DATATIMEOUT;
-    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
-    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    config.DPSM          = SDIO_DPSM_ENABLE;
-    (void)SDIO_ConfigData(hsd->Instance, &config);
-
-    /* Read Blocks in IT mode */
-    if(NumberOfBlocks > 1U)
-    {
-      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
-      /* Read Multi Block command */
-      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
-    }
-    else
-    {
-      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
-      /* Read Single Block command */
-      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
-    }
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer
-  *         is managed in interrupt mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @note   You could also check the IT transfer process through the SD Tx
-  *         interrupt event.
-  * @param  hsd: Pointer to SD handle
-  * @param  pData: Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd: Block Address where data will be written
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @note   Due to limitation "SDIO hardware flow control" indicated in Errata Sheet :
-  *         In 4-bits bus wide mode, do not use this API otherwise underrun will occur and
-  *         there is not possibility to activate the flow control.
-  *         Use DMA mode when using 4-bits bus wide mode or decrease the frequency.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t add = BlockAdd;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    hsd->pTxBuffPtr = pData;
-    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
-    /* Enable transfer interrupts */
-    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
-
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      add *= 512U;
-    }
-
-    /* Write Blocks in Polling mode */
-    if(NumberOfBlocks > 1U)
-    {
-      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
-      /* Write Multi Block command */
-      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
-    }
-    else
-    {
-      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
-      /* Write Single Block command */
-      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
-    }
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-
-    /* Configure the SD DPSM (Data Path State Machine) */
-    config.DataTimeOut   = SDMMC_DATATIMEOUT;
-    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
-    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    config.DPSM          = SDIO_DPSM_ENABLE;
-    (void)SDIO_ConfigData(hsd->Instance, &config);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer
-  *         is managed by DMA mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @note   You could also check the DMA transfer process through the SD Rx
-  *         interrupt event.
-  * @param  hsd: Pointer SD handle
-  * @param  pData: Pointer to the buffer that will contain the received data
-  * @param  BlockAdd: Block Address from where data is to be read
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t add = BlockAdd;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
-
-    /* Set the DMA transfer complete callback */
-    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
-
-    /* Set the DMA error callback */
-    hsd->hdmarx->XferErrorCallback = SD_DMAError;
-
-    /* Set the DMA Abort callback */
-    hsd->hdmarx->XferAbortCallback = NULL;
-
-    /* Force DMA Direction */
-    hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
-    MODIFY_REG(hsd->hdmarx->Instance->CCR, DMA_CCR_DIR, hsd->hdmarx->Init.Direction);
-
-    /* Enable the DMA Channel */
-    if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
-    {
-      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
-      hsd->State = HAL_SD_STATE_READY;
-      return HAL_ERROR;
-    }
-    else
-    {
-      /* Enable SD DMA transfer */
-      __HAL_SD_DMA_ENABLE(hsd);
-
-      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-      {
-        add *= 512U;
-      }
-
-      /* Configure the SD DPSM (Data Path State Machine) */
-      config.DataTimeOut   = SDMMC_DATATIMEOUT;
-      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
-      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-      config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-      config.DPSM          = SDIO_DPSM_ENABLE;
-      (void)SDIO_ConfigData(hsd->Instance, &config);
-
-      /* Read Blocks in DMA mode */
-      if(NumberOfBlocks > 1U)
-      {
-        hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
-        /* Read Multi Block command */
-        errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
-      }
-      else
-      {
-        hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
-        /* Read Single Block command */
-        errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
-      }
-      if(errorstate != HAL_SD_ERROR_NONE)
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        hsd->Context = SD_CONTEXT_NONE;
-        return HAL_ERROR;
-      }
-
-      return HAL_OK;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer
-  *         is managed by DMA mode.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @note   You could also check the DMA transfer process through the SD Tx
-  *         interrupt event.
-  * @param  hsd: Pointer to SD handle
-  * @param  pData: Pointer to the buffer that will contain the data to transmit
-  * @param  BlockAdd: Block Address where data will be written
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t add = BlockAdd;
-
-  if(NULL == pData)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Initialize data control register */
-    hsd->Instance->DCTRL = 0U;
-
-    /* Enable SD Error interrupts */
-    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
-
-    /* Set the DMA transfer complete callback */
-    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
-
-    /* Set the DMA error callback */
-    hsd->hdmatx->XferErrorCallback = SD_DMAError;
-
-    /* Set the DMA Abort callback */
-    hsd->hdmatx->XferAbortCallback = NULL;
-
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      add *= 512U;
-    }
-
-    /* Write Blocks in Polling mode */
-    if(NumberOfBlocks > 1U)
-    {
-      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
-      /* Write Multi Block command */
-      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
-    }
-    else
-    {
-      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
-      /* Write Single Block command */
-      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
-    }
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-
-    /* Enable SDIO DMA transfer */
-    __HAL_SD_DMA_ENABLE(hsd);
-
-    /* Force DMA Direction */
-    hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
-    MODIFY_REG(hsd->hdmatx->Instance->CCR, DMA_CCR_DIR, hsd->hdmatx->Init.Direction);
-
-    /* Enable the DMA Channel */
-    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
-    {
-      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      return HAL_ERROR;
-    }
-    else
-    {
-      /* Configure the SD DPSM (Data Path State Machine) */
-      config.DataTimeOut   = SDMMC_DATATIMEOUT;
-      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
-      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-      config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-      config.DPSM          = SDIO_DPSM_ENABLE;
-      (void)SDIO_ConfigData(hsd->Instance, &config);
-
-      return HAL_OK;
-    }
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @note   This API should be followed by a check on the card state through
-  *         HAL_SD_GetCardState().
-  * @param  hsd: Pointer to SD handle
-  * @param  BlockStartAdd: Start Block address
-  * @param  BlockEndAdd: End Block address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
-{
-  uint32_t errorstate;
-  uint32_t start_add = BlockStartAdd;
-  uint32_t end_add = BlockEndAdd;
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    hsd->ErrorCode = HAL_SD_ERROR_NONE;
-
-    if(end_add < start_add)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-      return HAL_ERROR;
-    }
-
-    if(end_add > (hsd->SdCard.LogBlockNbr))
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_BUSY;
-
-    /* Check if the card command class supports erase command */
-    if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
-      hsd->State = HAL_SD_STATE_READY;
-      return HAL_ERROR;
-    }
-
-    if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
-      hsd->State = HAL_SD_STATE_READY;
-      return HAL_ERROR;
-    }
-
-    /* Get start and end block for high capacity cards */
-    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
-    {
-      start_add *= 512U;
-      end_add   *= 512U;
-    }
-
-    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-    if(hsd->SdCard.CardType != CARD_SECURED)
-    {
-      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
-      if(errorstate != HAL_SD_ERROR_NONE)
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        return HAL_ERROR;
-      }
-
-      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
-      if(errorstate != HAL_SD_ERROR_NONE)
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        return HAL_ERROR;
-      }
-    }
-
-    /* Send CMD38 ERASE */
-    errorstate = SDMMC_CmdErase(hsd->Instance);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-      hsd->ErrorCode |= errorstate;
-      hsd->State = HAL_SD_STATE_READY;
-      return HAL_ERROR;
-    }
-
-    hsd->State = HAL_SD_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: Pointer to SD handle
-  * @retval None
-  */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
-  uint32_t errorstate;
-  uint32_t context = hsd->Context;
-
-  /* Check for SDIO interrupt flags */
-  if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
-  {
-    SD_Read_IT(hsd);
-  }
-
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)
-  {
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
-
-    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
-                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\
-                             SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR);
-
-    hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
-    
-    if((context & SD_CONTEXT_IT) != 0U)
-    {
-      if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
-      {
-        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          hsd->ErrorCode |= errorstate;
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-          hsd->ErrorCallback(hsd);
-#else
-          HAL_SD_ErrorCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-        }
-      }
-
-      /* Clear all the static flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
-      {
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-        hsd->RxCpltCallback(hsd);
-#else
-        HAL_SD_RxCpltCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-      }
-      else
-      {
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-        hsd->TxCpltCallback(hsd);
-#else
-        HAL_SD_TxCpltCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-      }
-    }
-    else if((context & SD_CONTEXT_DMA) != 0U)
-    {
-      if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
-      {
-        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          hsd->ErrorCode |= errorstate;
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-          hsd->ErrorCallback(hsd);
-#else
-          HAL_SD_ErrorCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-        }
-      }
-      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
-      {
-        /* Disable the DMA transfer for transmit request by setting the DMAEN bit
-        in the SD DCTRL register */
-        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
-        hsd->State = HAL_SD_STATE_READY;
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-        hsd->TxCpltCallback(hsd);
-#else
-        HAL_SD_TxCpltCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-
-  else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
-  {
-    SD_Write_IT(hsd);
-  }
-
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET)
-  {
-    /* Set Error code */
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
-    }
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
-    }
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
-    }
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
-    }
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
-    }
-
-    /* Clear All flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
-
-    /* Disable all interrupts */
-    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
-                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
-
-    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
-    if((context & SD_CONTEXT_IT) != 0U)
-    {
-      /* Set the SD state to ready to be able to start again the process */
-      hsd->State = HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-      hsd->ErrorCallback(hsd);
-#else
-      HAL_SD_ErrorCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-    }
-    else if((context & SD_CONTEXT_DMA) != 0U)
-    {
-      /* Abort the SD DMA channel */
-      if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
-      {
-        /* Set the DMA Tx abort callback */
-        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
-        /* Abort DMA in IT mode */
-        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
-        {
-          SD_DMATxAbort(hsd->hdmatx);
-        }
-      }
-      else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
-      {
-        /* Set the DMA Rx abort callback */
-        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
-        /* Abort DMA in IT mode */
-        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
-        {
-          SD_DMARxAbort(hsd->hdmarx);
-        }
-      }
-      else
-      {
-        hsd->ErrorCode = HAL_SD_ERROR_NONE;
-        hsd->State = HAL_SD_STATE_READY;
-        hsd->Context = SD_CONTEXT_NONE;
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-        hsd->AbortCpltCallback(hsd);
-#else
-        HAL_SD_AbortCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-}
-
-/**
-  * @brief return the SD state
-  * @param hsd: Pointer to sd handle
-  * @retval HAL state
-  */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
-{
-  return hsd->State;
-}
-
-/**
-* @brief  Return the SD error code
-* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
-  *              the configuration information.
-* @retval SD Error Code
-*/
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
-{
-  return hsd->ErrorCode;
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param hsd: Pointer to SD handle
-  * @retval None
-  */
-__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_TxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param hsd: Pointer SD handle
-  * @retval None
-  */
-__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_RxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief SD error callbacks
-  * @param hsd: Pointer SD handle
-  * @retval None
-  */
-__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_ErrorCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief SD Abort callbacks
-  * @param hsd: Pointer SD handle
-  * @retval None
-  */
-__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsd);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SD_AbortCallback can be implemented in the user file
-   */
-}
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User SD Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hsd : SD handle
-  * @param CallbackID : ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
-  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
-  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
-  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
-  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
-  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
-  * @param pCallback : pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(pCallback == NULL)
-  {
-    /* Update the error code */
-    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hsd);
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-    case HAL_SD_TX_CPLT_CB_ID :
-      hsd->TxCpltCallback = pCallback;
-      break;
-    case HAL_SD_RX_CPLT_CB_ID :
-      hsd->RxCpltCallback = pCallback;
-      break;
-    case HAL_SD_ERROR_CB_ID :
-      hsd->ErrorCallback = pCallback;
-      break;
-    case HAL_SD_ABORT_CB_ID :
-      hsd->AbortCpltCallback = pCallback;
-      break;
-    case HAL_SD_MSP_INIT_CB_ID :
-      hsd->MspInitCallback = pCallback;
-      break;
-    case HAL_SD_MSP_DEINIT_CB_ID :
-      hsd->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hsd->State == HAL_SD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-    case HAL_SD_MSP_INIT_CB_ID :
-      hsd->MspInitCallback = pCallback;
-      break;
-    case HAL_SD_MSP_DEINIT_CB_ID :
-      hsd->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsd);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User SD Callback
-  *         SD Callback is redirected to the weak (surcharged) predefined callback
-  * @param hsd : SD handle
-  * @param CallbackID : ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
-  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
-  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
-  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
-  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
-  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hsd);
-
-  if(hsd->State == HAL_SD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-    case HAL_SD_TX_CPLT_CB_ID :
-      hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
-      break;
-    case HAL_SD_RX_CPLT_CB_ID :
-      hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
-      break;
-    case HAL_SD_ERROR_CB_ID :
-      hsd->ErrorCallback = HAL_SD_ErrorCallback;
-      break;
-    case HAL_SD_ABORT_CB_ID :
-      hsd->AbortCpltCallback = HAL_SD_AbortCallback;
-      break;
-    case HAL_SD_MSP_INIT_CB_ID :
-      hsd->MspInitCallback = HAL_SD_MspInit;
-      break;
-    case HAL_SD_MSP_DEINIT_CB_ID :
-      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if (hsd->State == HAL_SD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-    case HAL_SD_MSP_INIT_CB_ID :
-      hsd->MspInitCallback = HAL_SD_MspInit;
-      break;
-    case HAL_SD_MSP_DEINIT_CB_ID :
-      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsd);
-  return status;
-}
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SD_Exported_Functions_Group3
- *  @brief   management functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the SD card
-    operations and get the related information
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns information the information of the card which are stored on
-  *         the CID register.
-  * @param  hsd: Pointer to SD handle
-  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that  
-  *         contains all CID register parameters
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
-{
-  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
-
-  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
-
-  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
-
-  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
-
-  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
-
-  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
-
-  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
-
-  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
-
-  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
-
-  pCID->Reserved2 = 1U;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Returns information the information of the card which are stored on
-  *         the CSD register.
-  * @param  hsd: Pointer to SD handle
-  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that  
-  *         contains all CSD register parameters
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
-{
-  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
-
-  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
-
-  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
-
-  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
-
-  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
-
-  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
-
-  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
-
-  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
-
-  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
-
-  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
-
-  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
-
-  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
-
-  pCSD->Reserved2 = 0U; /*!< Reserved */
-
-  if(hsd->SdCard.CardType == CARD_SDSC)
-  {
-    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
-
-    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
-
-    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
-
-    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
-
-    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
-
-    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
-
-    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
-    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
-    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
-
-    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
-    hsd->SdCard.LogBlockSize = 512U;
-  }
-  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
-  {
-    /* Byte 7 */
-    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
-
-    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
-    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
-    hsd->SdCard.BlockSize = 512U;
-    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
-  }
-  else
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-    hsd->State = HAL_SD_STATE_READY;
-    return HAL_ERROR;
-  }
-
-  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
-
-  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
-
-  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
-
-  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
-
-  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
-
-  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
-
-  pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
-
-  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
-
-  pCSD->Reserved3 = 0;
-
-  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
-
-  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
-
-  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
-
-  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
-
-  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
-
-  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
-
-  pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
-
-  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
-
-  pCSD->Reserved4 = 1;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the SD status info.
-  * @param  hsd: Pointer to SD handle
-  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that 
-  *         will contain the SD card status information
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
-{
-  uint32_t sd_status[16];
-  uint32_t errorstate;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  errorstate = SD_SendSDStatus(hsd, sd_status);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->ErrorCode |= errorstate;
-    hsd->State = HAL_SD_STATE_READY;
-    status = HAL_ERROR;
-  }
-  else
-  {
-    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
-
-    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
-
-    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
-
-    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
-                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
-
-    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
-
-    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
-
-    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
-
-    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
-
-    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
-
-    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
-  }
-
-  /* Set Block Size for Card */
-  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->ErrorCode = errorstate;
-    hsd->State = HAL_SD_STATE_READY;
-    status = HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Gets the SD card info.
-  * @param  hsd: Pointer to SD handle
-  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
-  *         will contain the SD card status information
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
-{
-  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
-  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
-  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
-  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
-  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
-  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
-  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
-  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables wide bus operation for the requested card if supported by
-  *         card.
-  * @param  hsd: Pointer to SD handle
-  * @param  WideMode: Specifies the SD card wide bus mode
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
-  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
-  SDIO_InitTypeDef Init;
-  uint32_t errorstate;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_BUS_WIDE(WideMode));
-
-  /* Change State */
-  hsd->State = HAL_SD_STATE_BUSY;
-
-  if(hsd->SdCard.CardType != CARD_SECURED)
-  {
-    if(WideMode == SDIO_BUS_WIDE_8B)
-    {
-      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-    }
-    else if(WideMode == SDIO_BUS_WIDE_4B)
-    {
-      errorstate = SD_WideBus_Enable(hsd);
-
-      hsd->ErrorCode |= errorstate;
-    }
-    else if(WideMode == SDIO_BUS_WIDE_1B)
-    {
-      errorstate = SD_WideBus_Disable(hsd);
-
-      hsd->ErrorCode |= errorstate;
-    }
-    else
-    {
-      /* WideMode is not a valid argument*/
-      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
-    }
-  }
-  else
-  {
-    /* MMC Card does not support this feature */
-    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-  }
-
-  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->State = HAL_SD_STATE_READY;
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Configure the SDIO peripheral */
-    Init.ClockEdge           = hsd->Init.ClockEdge;
-    Init.ClockBypass         = hsd->Init.ClockBypass;
-    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
-    Init.BusWide             = WideMode;
-    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-    Init.ClockDiv            = hsd->Init.ClockDiv;
-    (void)SDIO_Init(hsd->Instance, Init);
-  }
-
-  /* Set Block Size for Card */
-  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    hsd->ErrorCode |= errorstate;
-    status = HAL_ERROR;
-  }
-
-  /* Change State */
-  hsd->State = HAL_SD_STATE_READY;
-
-  return status;
-}
-
-/**
-  * @brief  Gets the current sd card data state.
-  * @param  hsd: pointer to SD handle
-  * @retval Card state
-  */
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
-{
-  uint32_t cardstate;
-  uint32_t errorstate;
-  uint32_t resp1 = 0;
-
-  errorstate = SD_SendStatus(hsd, &resp1);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->ErrorCode |= errorstate;
-  }
-
-  cardstate = ((resp1 >> 9U) & 0x0FU);
-
-  return (HAL_SD_CardStateTypeDef)cardstate;
-}
-
-/**
-  * @brief  Abort the current transfer and disable the SD.
-  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
-  *                the configuration information for SD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypeDef CardState;
-  uint32_t context = hsd->Context;
-
-  /* DIsable All interrupts */
-  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
-                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
-  /* Clear All flags */
-  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
-
-  if ((context & SD_CONTEXT_DMA) != 0U)
-  {
-    /* Disable the SD DMA request */
-    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
-    /* Abort the SD DMA Tx channel */
-    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
-    {
-      if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
-      {
-        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
-      }
-    }
-    /* Abort the SD DMA Rx channel */
-    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
-    {
-      if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
-      {
-        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-
-  hsd->State = HAL_SD_STATE_READY;
-
-  /* Initialize the SD operation */
-  hsd->Context = SD_CONTEXT_NONE;
-
-  CardState = HAL_SD_GetCardState(hsd);
-  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
-  {
-    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
-  }
-  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
-  {
-    return HAL_ERROR;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort the current transfer and disable the SD (IT mode).
-  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
-  *                the configuration information for SD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypeDef CardState;
-  uint32_t context = hsd->Context;
-
-  /* Disable All interrupts */
-  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
-                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
-  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
-
-  if ((context & SD_CONTEXT_DMA) != 0U)
-  {
-    /* Disable the SD DMA request */
-    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
-    /* Abort the SD DMA Tx channel */
-    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
-    {
-      hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
-      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
-      {
-        hsd->hdmatx = NULL;
-      }
-    }
-    /* Abort the SD DMA Rx channel */
-    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
-    {
-      hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
-      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
-      {
-        hsd->hdmarx = NULL;
-      }
-    }
-    else
-    {
-      /* Nothing to do */
-    }
-  }
-  /* No transfer ongoing on both DMA channels*/
-  else
-  {
-    /* Clear All flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-    CardState = HAL_SD_GetCardState(hsd);
-    hsd->State = HAL_SD_STATE_READY;
-    hsd->Context = SD_CONTEXT_NONE;
-    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
-    {
-      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
-    }
-    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-      hsd->AbortCpltCallback(hsd);
-#else
-      HAL_SD_AbortCallback(hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  DMA SD transmit process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-
-  /* Enable DATAEND Interrupt */
-  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
-}
-
-/**
-  * @brief  DMA SD receive process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-  uint32_t errorstate;
-
-  /* Send stop command in multiblock write */
-  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
-  {
-    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      hsd->ErrorCode |= errorstate;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-      hsd->ErrorCallback(hsd);
-#else
-      HAL_SD_ErrorCallback(hsd);
-#endif
-    }
-  }
-
-  /* Disable the DMA transfer for transmit request by setting the DMAEN bit
-  in the SD DCTRL register */
-  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
-  /* Clear all the static flags */
-  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-  hsd->State = HAL_SD_STATE_READY;
-  hsd->Context = SD_CONTEXT_NONE;
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-  hsd->RxCpltCallback(hsd);
-#else
-  HAL_SD_RxCpltCallback(hsd);
-#endif
-}
-
-/**
-  * @brief  DMA SD communication error callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void SD_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-  HAL_SD_CardStateTypeDef CardState;
-  uint32_t RxErrorCode, TxErrorCode;
-
-    RxErrorCode = hsd->hdmarx->ErrorCode;
-    TxErrorCode = hsd->hdmatx->ErrorCode;  
-    if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
-    {
-      /* Clear All flags */
-      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
-      /* Disable All interrupts */
-      __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
-        SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
-      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
-      CardState = HAL_SD_GetCardState(hsd);
-      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
-      {
-        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-      }
-
-      hsd->State= HAL_SD_STATE_READY;
-      hsd->Context = SD_CONTEXT_NONE;
-    }
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-    hsd->ErrorCallback(hsd);
-#else
-    HAL_SD_ErrorCallback(hsd);
-#endif
-}
-
-/**
-  * @brief  DMA SD Tx Abort callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-  HAL_SD_CardStateTypeDef CardState;
-
-  /* Clear All flags */
-  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-  CardState = HAL_SD_GetCardState(hsd);
-  hsd->State = HAL_SD_STATE_READY;
-  hsd->Context = SD_CONTEXT_NONE;
-  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
-  {
-    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-  }
-
-  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
-  {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-    hsd->AbortCpltCallback(hsd);
-#else
-    HAL_SD_AbortCallback(hsd);
-#endif
-  }
-  else
-  {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-    hsd->ErrorCallback(hsd);
-#else
-    HAL_SD_ErrorCallback(hsd);
-#endif
-  }
-}
-
-/**
-  * @brief  DMA SD Rx Abort callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-  HAL_SD_CardStateTypeDef CardState;
-
-  /* Clear All flags */
-  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-  CardState = HAL_SD_GetCardState(hsd);
-  hsd->State = HAL_SD_STATE_READY;
-  hsd->Context = SD_CONTEXT_NONE;
-  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
-  {
-    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-  }
-
-  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
-  {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-    hsd->AbortCpltCallback(hsd);
-#else
-    HAL_SD_AbortCallback(hsd);
-#endif
-  }
-  else
-  {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
-    hsd->ErrorCallback(hsd);
-#else
-    HAL_SD_ErrorCallback(hsd);
-#endif
-  }
-}
-
-/**
-  * @brief  Initializes the sd card.
-  * @param  hsd: Pointer to SD handle
-  * @retval SD Card error state
-  */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardCSDTypeDef CSD;
-  uint32_t errorstate;
-  uint16_t sd_rca = 1U;
-
-  /* Check the power State */
-  if(SDIO_GetPowerState(hsd->Instance) == 0U)
-  {
-    /* Power off */
-    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
-  }
-
-  if(hsd->SdCard.CardType != CARD_SECURED)
-  {
-    /* Send CMD2 ALL_SEND_CID */
-    errorstate = SDMMC_CmdSendCID(hsd->Instance);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-    else
-    {
-      /* Get Card identification number data */
-      hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-      hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
-      hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
-      hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
-    }
-  }
-
-  if(hsd->SdCard.CardType != CARD_SECURED)
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-  }
-  if(hsd->SdCard.CardType != CARD_SECURED)
-  {
-    /* Get the SD card RCA */
-    hsd->SdCard.RelCardAdd = sd_rca;
-
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-    else
-    {
-      /* Get Card Specific Data */
-      hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-      hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
-      hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
-      hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
-    }
-  }
-
-  /* Get the Card Class */
-  hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
-
-  /* Get CSD parameters */
-  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
-  {
-    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-  }
-
-  /* Select the Card */
-  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* Configure SDIO peripheral interface */
-  (void)SDIO_Init(hsd->Instance, hsd->Init);
-
-  /* All cards are initialized */
-  return HAL_SD_ERROR_NONE;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: Pointer to SD handle
-  * @retval error state
-  */
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
-{
-  __IO uint32_t count = 0U;
-  uint32_t response = 0U, validvoltage = 0U;
-  uint32_t errorstate;
-
-  /* CMD0: GO_IDLE_STATE */
-  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
-  errorstate = SDMMC_CmdOperCond(hsd->Instance);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->SdCard.CardVersion = CARD_V1_X;
-    /* CMD0: GO_IDLE_STATE */
-    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-  }
-  else
-  {
-    hsd->SdCard.CardVersion = CARD_V2_X;
-  }
-
-  if( hsd->SdCard.CardVersion == CARD_V2_X)
-  {
-    /* SEND CMD55 APP_CMD with RCA as 0 */
-    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-    }
-  }
-  /* SD CARD */
-  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-  while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
-  {
-    /* SEND CMD55 APP_CMD with RCA as 0 */
-    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-    /* Send CMD41 */
-    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
-    }
-
-    /* Get command response */
-    response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
-    /* Get operating voltage*/
-    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
-
-    count++;
-  }
-
-  if(count >= SDMMC_MAX_VOLT_TRIAL)
-  {
-    return HAL_SD_ERROR_INVALID_VOLTRANGE;
-  }
-
-  if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
-  {
-    hsd->SdCard.CardType = CARD_SDHC_SDXC;
-  }
-  else
-  {
-    hsd->SdCard.CardType = CARD_SDSC;
-  }
-
-
-  return HAL_SD_ERROR_NONE;
-}
-
-/**
-  * @brief  Turns the SDIO output signals off.
-  * @param  hsd: Pointer to SD handle
-  * @retval None
-  */
-static void SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
-  /* Set Power State to OFF */
-  (void)SDIO_PowerState_OFF(hsd->Instance);
-}
-
-/**
-  * @brief  Send Status info command.
-  * @param  hsd: pointer to SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
-  *         SD Status register)
-  * @retval error state
-  */
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t count;
-  uint32_t *pData = pSDstatus;
-
-  /* Check SD response */
-  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
-  {
-    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
-  }
-
-  /* Set block size for card if it is not equal to current block size for card */
-  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
-    return errorstate;
-  }
-
-  /* Send CMD55 */
-  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
-    return errorstate;
-  }
-
-  /* Configure the SD DPSM (Data Path State Machine) */
-  config.DataTimeOut   = SDMMC_DATATIMEOUT;
-  config.DataLength    = 64U;
-  config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
-  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  config.DPSM          = SDIO_DPSM_ENABLE;
-  (void)SDIO_ConfigData(hsd->Instance, &config);
-
-  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
-  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
-    return errorstate;
-  }
-
-  /* Get status data */
-  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
-  {
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-    {
-      for(count = 0U; count < 8U; count++)
-      {
-        *pData = SDIO_ReadFIFO(hsd->Instance);
-        pData++;
-      }
-    }
-
-    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
-    {
-      return HAL_SD_ERROR_TIMEOUT;
-    }
-  }
-
-  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    return HAL_SD_ERROR_DATA_TIMEOUT;
-  }
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    return HAL_SD_ERROR_DATA_CRC_FAIL;
-  }
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    return HAL_SD_ERROR_RX_OVERRUN;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-
-  while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
-  {
-    *pData = SDIO_ReadFIFO(hsd->Instance);
-    pData++;
-
-    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
-    {
-      return HAL_SD_ERROR_TIMEOUT;
-    }
-  }
-
-  /* Clear all the static status flags*/
-  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-  return HAL_SD_ERROR_NONE;
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  hsd: Pointer to SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card
-  *         status (Card Status register)
-  * @retval error state
-  */
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
-  uint32_t errorstate;
-
-  if(pCardStatus == NULL)
-  {
-    return HAL_SD_ERROR_PARAM;
-  }
-
-  /* Send Status command */
-  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* Get SD card status */
-  *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
-  return HAL_SD_ERROR_NONE;
-}
-
-/**
-  * @brief  Enables the SDIO wide bus mode.
-  * @param  hsd: pointer to SD handle
-  * @retval error state
-  */
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
-  uint32_t scr[2U] = {0U, 0U};
-  uint32_t errorstate;
-
-  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
-  {
-    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
-  }
-
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* If requested card supports wide bus operation */
-  if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-    return HAL_SD_ERROR_NONE;
-  }
-  else
-  {
-    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
-  }
-}
-
-/**
-  * @brief  Disables the SDIO wide bus mode.
-  * @param  hsd: Pointer to SD handle
-  * @retval error state
-  */
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
-  uint32_t scr[2U] = {0U, 0U};
-  uint32_t errorstate;
-
-  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
-  {
-    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
-  }
-
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* If requested card supports 1 bit mode operation */
-  if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA */
-    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
-    if(errorstate != HAL_SD_ERROR_NONE)
-    {
-      return errorstate;
-    }
-
-    return HAL_SD_ERROR_NONE;
-  }
-  else
-  {
-    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
-  }
-}
-
-
-/**
-  * @brief  Finds the SD card SCR register value.
-  * @param  hsd: Pointer to SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value
-  * @retval error state
-  */
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
-  SDIO_DataInitTypeDef config;
-  uint32_t errorstate;
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t index = 0U;
-  uint32_t tempscr[2U] = {0U, 0U};
-  uint32_t *scr = pSCR;
-
-  /* Set Block Size To 8 Bytes */
-  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  config.DataTimeOut   = SDMMC_DATATIMEOUT;
-  config.DataLength    = 8U;
-  config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
-  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  config.DPSM          = SDIO_DPSM_ENABLE;
-  (void)SDIO_ConfigData(hsd->Instance, &config);
-
-  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
-  if(errorstate != HAL_SD_ERROR_NONE)
-  {
-    return errorstate;
-  }
-
-  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
-  {
-    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
-    {
-      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
-      index++;
-    }
-    else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT))
-    {
-      break;
-    }
-
-    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
-    {
-      return HAL_SD_ERROR_TIMEOUT;
-    }
-  }
-
-  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
-    return HAL_SD_ERROR_DATA_TIMEOUT;
-  }
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-
-    return HAL_SD_ERROR_DATA_CRC_FAIL;
-  }
-  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
-    return HAL_SD_ERROR_RX_OVERRUN;
-  }
-  else
-  {
-    /* No error flag set */
-    /* Clear all the static flags */
-    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
-
-    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
-            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
-    scr++;
-    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
-            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
-
-  }
-
-  return HAL_SD_ERROR_NONE;
-}
-
-/**
-  * @brief  Wrap up reading in non-blocking mode.
-  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
-  *              the configuration information.
-  * @retval None
-  */
-static void SD_Read_IT(SD_HandleTypeDef *hsd)
-{
-  uint32_t count, data, dataremaining;
-  uint8_t* tmp;
-
-  tmp = hsd->pRxBuffPtr;
-  dataremaining = hsd->RxXferSize;
-
-  if (dataremaining > 0U)
-  {
-    /* Read data from SDIO Rx FIFO */
-    for(count = 0U; count < 8U; count++)
-    {
-      data = SDIO_ReadFIFO(hsd->Instance);
-      *tmp = (uint8_t)(data & 0xFFU);
-      tmp++;
-      dataremaining--;
-      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
-      tmp++;
-      dataremaining--;
-      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
-      tmp++;
-      dataremaining--;
-      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
-      tmp++;
-      dataremaining--;
-    }
-
-    hsd->pRxBuffPtr = tmp;
-    hsd->RxXferSize = dataremaining;
-  }
-}
-
-/**
-  * @brief  Wrap up writing in non-blocking mode.
-  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
-  *              the configuration information.
-  * @retval None
-  */
-static void SD_Write_IT(SD_HandleTypeDef *hsd)
-{
-  uint32_t count, data, dataremaining;
-  uint8_t* tmp;
-
-  tmp = hsd->pTxBuffPtr;
-  dataremaining = hsd->TxXferSize;
-
-  if (dataremaining > 0U)
-  {
-    /* Write data to SDIO Tx FIFO */
-    for(count = 0U; count < 8U; count++)
-    {
-      data = (uint32_t)(*tmp);
-      tmp++;
-      dataremaining--;
-      data |= ((uint32_t)(*tmp) << 8U);
-      tmp++;
-      dataremaining--;
-      data |= ((uint32_t)(*tmp) << 16U);
-      tmp++;
-      dataremaining--;
-      data |= ((uint32_t)(*tmp) << 24U);
-      tmp++;
-      dataremaining--;
-      (void)SDIO_WriteFIFO(hsd->Instance, &data);
-    }
-
-    hsd->pTxBuffPtr = tmp;
-    hsd->TxXferSize = dataremaining;
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* SDIO */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c
deleted file mode 100644
index d70cb167d9e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_smartcard.c
+++ /dev/null
@@ -1,2351 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_smartcard.c
-  * @author  MCD Application Team
-  * @brief   SMARTCARD HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the SMARTCARD peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Error functions
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SMARTCARD HAL driver can be used as follows:
-
-    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
-    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
-        (##) Enable the interface clock of the USARTx associated to the SMARTCARD.
-        (##) SMARTCARD pins configuration:
-            (+++) Enable the clock for the SMARTCARD GPIOs.
-            (+++) Configure SMARTCARD pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
-             and HAL_SMARTCARD_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
-             and HAL_SMARTCARD_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
-                  (used for last byte sending completion detection in DMA non circular mode)
-
-    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
-
-    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
-        (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_SMARTCARD_MspInit() API.
-    [..]
-    (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
-        RXNE interrupt and Error Interrupts) will be managed using the macros
-        __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
-    [..]
-    Three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
-      (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
-      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
-      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
-      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
-      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
-      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
-      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
-          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
-    *** SMARTCARD HAL driver macros list ***
-    ========================================
-    [..]
-      Below the list of most used macros in SMARTCARD HAL driver.
-
-      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
-      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
-      (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
-      (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
-      (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
-      (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-
-    [..]
-      (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
-    Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : SMARTCARD MspInit.
-    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : SMARTCARD MspInit.
-    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
-
-    [..]
-    By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
-    and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
-    or @ref HAL_SMARTCARD_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMARTCARD SMARTCARD
-  * @brief HAL SMARTCARD module driver
-  * @{
-  */
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions
-  * @{
-  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USART
-  in Smartcard mode.
-  [..]
-  The Smartcard interface is designed to support asynchronous protocol Smartcards as
-  defined in the ISO 7816-3 standard.
-  [..]
-  The USART can provide a clock to the smartcard through the SCLK output.
-  In smartcard mode, SCLK is not associated to the communication but is simply derived
-  from the internal peripheral input clock through a 5-bit prescaler.
-  [..]
-  (+) For the Smartcard mode only these parameters can be configured:
-      (++) Baud Rate
-      (++) Word Length => Should be 9 bits (8 bits + parity)
-      (++) Stop Bit
-      (++) Parity: => Should be enabled
-      (++) USART polarity
-      (++) USART phase
-      (++) USART LastBit
-      (++) Receiver/transmitter modes
-      (++) Prescaler
-      (++) GuardTime
-      (++) NACKState: The Smartcard NACK state
-
-     (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
-        (++) Word Length = 9 Bits
-        (++) 1.5 Stop Bit
-        (++) Even parity
-        (++) BaudRate = 12096 baud
-        (++) Tx and Rx enabled
-  [..]
-  Please refer to the ISO 7816-3 specification for more details.
-
-  [..]
-   (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
-       to use 1.5 stop bits for both transmitting and receiving to avoid switching
-       between the two configurations.
-  [..]
-    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
-    procedures (details for the procedures are available in reference manual (RM0038)).
-
-@endverbatim
-
-  The SMARTCARD frame format is given in the following table:
-       +-------------------------------------------------------------+
-       |   M bit |  PCE bit  |        SMARTCARD frame                |
-       |---------------------|---------------------------------------|
-       |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-       +-------------------------------------------------------------+
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SmartCard mode according to the specified
-  *         parameters in the SMARTCARD_InitTypeDef and create the associated handle.
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Check the SMARTCARD handle allocation */
-  if(hsc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
-
-  if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hsc->Lock = HAL_UNLOCKED;
-
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-    SMARTCARD_InitCallbacksToDefault(hsc);
-
-    if (hsc->MspInitCallback == NULL)
-    {
-      hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hsc->MspInitCallback(hsc);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_SMARTCARD_MspInit(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-  }
-
-  hsc->gState = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Set the Prescaler */
-  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
-
-  /* Set the Guard Time */
-  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
-
-  /* Set the Smartcard Communication parameters */
-  SMARTCARD_SetConfig(hsc);
-
-  /* In SmartCard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register
-  - HDSEL and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
-  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-
-  /* Enable the SMARTCARD Parity Error Interrupt */
-  SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
-  /* Enable the SMARTCARD Framing Error Interrupt */
-  SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Enable the Peripheral */
-  __HAL_SMARTCARD_ENABLE(hsc);
-
-  /* Configure the Smartcard NACK state */
-  MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
-
-  /* Enable the SC mode by setting the SCEN bit in the CR3 register */
-  hsc->Instance->CR3 |= (USART_CR3_SCEN);
-
-  /* Initialize the SMARTCARD state*/
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->gState= HAL_SMARTCARD_STATE_READY;
-  hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DeInitializes the USART SmartCard peripheral
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Check the SMARTCARD handle allocation */
-  if(hsc == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-
-  hsc->gState = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_SMARTCARD_DISABLE(hsc);
-
-  /* DeInit the low level hardware */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-  if (hsc->MspDeInitCallback == NULL)
-  {
-    hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  hsc->MspDeInitCallback(hsc);
-#else
-  HAL_SMARTCARD_MspDeInit(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->gState = HAL_SMARTCARD_STATE_RESET;
-  hsc->RxState = HAL_SMARTCARD_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  SMARTCARD MSP Init
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspInit can be implemented in the user file
-   */
-}
-
-/**
-  * @brief SMARTCARD MSP DeInit
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
-   */
-}
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User SMARTCARD Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hsc smartcard handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hsc);
-
-  if (hsc->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-
-      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
-        hsc->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
-        hsc->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ERROR_CB_ID :
-        hsc->ErrorCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
-        hsc->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hsc->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hsc->AbortReceiveCpltCallback = pCallback;
-        break;
-
-
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hsc->gState == HAL_SMARTCARD_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsc);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an SMARTCARD callback
-  *         SMARTCARD callback is redirected to the weak predefined callback
-  * @param  hsc smartcard handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hsc);
-
-  if (HAL_SMARTCARD_STATE_READY == hsc->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
-        hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
-        break;
-
-      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
-        hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
-        break;
-
-      case HAL_SMARTCARD_ERROR_CB_ID :
-        hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                         /* Legacy weak ErrorCallback             */
-        break;
-
-      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
-        hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
-        break;
-
-      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-        break;
-
-      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
-        hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
-        break;
-
-
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsc->MspInitCallback = HAL_SMARTCARD_MspInit;                             /* Legacy weak MspInitCallback           */
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
-        break;
-
-      default :
-        /* Update the error code */
-        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SMARTCARD_STATE_RESET == hsc->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SMARTCARD_MSPINIT_CB_ID :
-        hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
-        break;
-
-      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
-        hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsc);
-
-  return status;
-}
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
-  * @brief    SMARTCARD Transmit and Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-   This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
- [..]
-    (#) Smartcard is a single wire half duplex communication protocol.
-    The Smartcard interface is designed to support asynchronous protocol Smartcards as
-    defined in the ISO 7816-3 standard.
-    (#) The USART should be configured as:
-       (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
-       (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) Non Blocking mode: The communication is performed using Interrupts
-           or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the Transmit or Receive process
-           The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_SMARTCARD_Transmit()
-        (++) HAL_SMARTCARD_Receive()
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_SMARTCARD_Transmit_IT()
-        (++) HAL_SMARTCARD_Receive_IT()
-        (++) HAL_SMARTCARD_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_SMARTCARD_Transmit_DMA()
-        (++) HAL_SMARTCARD_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_SMARTCARD_TxCpltCallback()
-        (++) HAL_SMARTCARD_RxCpltCallback()
-        (++) HAL_SMARTCARD_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_SMARTCARD_Abort()
-        (+) HAL_SMARTCARD_AbortTransmit()
-        (+) HAL_SMARTCARD_AbortReceive()
-        (+) HAL_SMARTCARD_Abort_IT()
-        (+) HAL_SMARTCARD_AbortTransmit_IT()
-        (+) HAL_SMARTCARD_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_SMARTCARD_AbortCpltCallback()
-        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
-        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
-           If user wants to abort it, Abort services should be called by user.
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Send an amount of data in blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t *tmp = pData;
-  uint32_t tickstart = 0U;
-
-  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-    while(hsc->TxXferCount > 0U)
-    {
-      hsc->TxXferCount--;
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      hsc->Instance->DR = (uint8_t)(*tmp & 0xFFU);
-      tmp++;
-    }
-
-    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-	/* At end of Tx process, restore hsc->gState to Ready */
-    hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be received
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *tmp = pData;
-  uint32_t tickstart = 0U;
-
-  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    hsc->RxXferSize = Size;
-    hsc->RxXferCount = Size;
-
-    /* Check the remain data to be received */
-    while(hsc->RxXferCount > 0U)
-    {
-      hsc->RxXferCount--;
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
-      tmp++;
-    }
-
-    /* At end of Rx process, restore hsc->RxState to Ready */
-    hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pTxBuffPtr = pData;
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    /* Enable the SMARTCARD Parity Error Interrupt */
-    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
-    /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the SMARTCARD Transmit data register empty Interrupt */
-    SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pRxBuffPtr = pData;
-    hsc->RxXferSize = Size;
-    hsc->RxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
-    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Send an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Tx process is not already ongoing */
-  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pTxBuffPtr = pData;
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
-    /* Set the DMA error callback */
-    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Set the DMA abort callback */
-    hsc->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the SMARTCARD transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
-
-     /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the SMARTCARD CR3 register */
-    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  pData  Pointer to data buffer
-  * @param  Size   Amount of data to be received
-  * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Rx process is not already ongoing */
-  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pRxBuffPtr = pData;
-    hsc->RxXferSize = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
-    /* Set the DMA error callback */
-    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Set the DMA abort callback */
-    hsc->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
-    __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    /* Enable the SMARTCARD Parity Error Interrupt */
-    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-    in the SMARTCARD CR3 register */
-    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsc->hdmatx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hsc->hdmatx);
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsc->hdmarx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hsc->hdmarx);
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  hsc->TxXferCount = 0x00U;
-  hsc->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Restore hsc->RxState and hsc->gState to Ready */
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-  hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsc->hdmatx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hsc->hdmatx);
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  hsc->TxXferCount = 0x00U;
-
-  /* Restore hsc->gState to Ready */
-  hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      hsc->hdmarx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(hsc->hdmarx);
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  hsc->RxXferCount = 0x00U;
-
-  /* Restore hsc->RxState to Ready */
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint32_t AbortCplt = 0x01U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if(hsc->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
-    {
-      hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
-    }
-    else
-    {
-      hsc->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if(hsc->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-    {
-      hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
-    }
-    else
-    {
-      hsc->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at SMARTCARD level */
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if(hsc->hdmatx != NULL)
-    {
-      /* SMARTCARD Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
-      {
-        hsc->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if(hsc->hdmarx != NULL)
-    {
-      /* SMARTCARD Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
-      {
-        hsc->hdmarx->XferAbortCallback = NULL;
-        AbortCplt = 0x01U;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if(AbortCplt == 0x01U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hsc->TxXferCount = 0x00U;
-    hsc->RxXferCount = 0x00U;
-
-    /* Reset ErrorCode */
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-    /* Restore hsc->gState and hsc->RxState to Ready */
-    hsc->gState  = HAL_SMARTCARD_STATE_READY;
-    hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    hsc->AbortCpltCallback(hsc);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_SMARTCARD_AbortCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the SMARTCARD DMA Tx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmatx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-      hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
-      {
-        /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
-        hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      hsc->TxXferCount = 0x00U;
-
-      /* Restore hsc->gState to Ready */
-      hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      hsc->AbortTransmitCpltCallback(hsc);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    hsc->TxXferCount = 0x00U;
-
-    /* Restore hsc->gState to Ready */
-    hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    hsc->AbortTransmitCpltCallback(hsc);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  hsc SMARTCARD handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SMARTCARD Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the SMARTCARD DMA Rx request if enabled */
-  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if(hsc->hdmarx != NULL)
-    {
-      /* Set the SMARTCARD DMA Abort callback :
-         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-      hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
-      {
-        /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
-        hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      hsc->RxXferCount = 0x00U;
-
-      /* Restore hsc->RxState to Ready */
-      hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      hsc->AbortReceiveCpltCallback(hsc);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    hsc->RxXferCount = 0x00U;
-
-    /* Restore hsc->RxState to Ready */
-    hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    hsc->AbortReceiveCpltCallback(hsc);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief This function handles SMARTCARD interrupt request.
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint32_t isrflags   = READ_REG(hsc->Instance->SR);
-  uint32_t cr1its     = READ_REG(hsc->Instance->CR1);
-  uint32_t cr3its     = READ_REG(hsc->Instance->CR3);
-  uint32_t dmarequest = 0x00U;
-  uint32_t errorflags = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if(errorflags == RESET)
-  {
-    /* SMARTCARD in mode Receiver -------------------------------------------------*/
-    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      SMARTCARD_Receive_IT(hsc);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* SMARTCARD parity error interrupt occurred ---------------------------*/
-    if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
-    }
-
-    /* SMARTCARD frame error interrupt occurred ----------------------------*/
-    if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
-    }
-
-    /* SMARTCARD noise error interrupt occurred ----------------------------*/
-    if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
-    }
-
-    /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
-    if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
-    }
-    /* Call the Error call Back in case of Errors --------------------------*/
-    if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
-    {
-      /* SMARTCARD in mode Receiver ----------------------------------------*/
-      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        SMARTCARD_Receive_IT(hsc);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
-      if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Blocking error : transfer is aborted
-          Set the SMARTCARD state ready to be able to start again the process,
-          Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        SMARTCARD_EndRxTransfer(hsc);
-        /* Disable the SMARTCARD DMA Rx request if enabled */
-        if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the SMARTCARD DMA Rx channel */
-          if(hsc->hdmarx != NULL)
-          {
-            /* Set the SMARTCARD DMA Abort callback :
-              will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
-            hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
-
-           if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
-            }
-          }
-          else
-          {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-            /* Call registered user error callback */
-            hsc->ErrorCallback(hsc);
-#else
-            /* Call legacy weak user error callback */
-            HAL_SMARTCARD_ErrorCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-          }
-        }
-        else
-        {
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-          /* Call registered user error callback */
-          hsc->ErrorCallback(hsc);
-#else
-          /* Call legacy weak user error callback */
-          HAL_SMARTCARD_ErrorCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-        /* Call registered user error callback */
-        hsc->ErrorCallback(hsc);
-#else
-        /* Call legacy weak user error callback */
-        HAL_SMARTCARD_ErrorCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-        hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-      }
-    }
-    return;
-  } /* End if some error occurs */
-
-  /* SMARTCARD in mode Transmitter ------------------------------------------*/
-  if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    SMARTCARD_Transmit_IT(hsc);
-    return;
-  }
-
-  /* SMARTCARD in mode Transmitter (transmission end) -----------------------*/
-  if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    SMARTCARD_EndTransmit_IT(hsc);
-    return;
-  }
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callback
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief SMARTCARD error callback
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Complete callback.
-  * @param  hsc SMARTCARD handle.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Transmit Complete callback.
-  * @param  hsc SMARTCARD handle.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
-    /* Prevent unused argument(s) compilation warning */
-    UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  SMARTCARD Abort Receive Complete callback.
-  * @param  hsc SMARTCARD handle.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
-    /* Prevent unused argument(s) compilation warning */
-    UNUSED(hsc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   SMARTCARD State and Errors functions
-  *
-@verbatim
- ===============================================================================
-                ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SmartCard.
-     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
-     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Return the SMARTCARD handle state
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval HAL state
-  */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint32_t temp1= 0x00U, temp2 = 0x00U;
-  temp1 = hsc->gState;
-  temp2 = hsc->RxState;
-
-  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the SMARTCARD error code
-  * @param  hsc  Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *              the configuration information for the specified SMARTCARD.
-  * @retval SMARTCARD Error Code
-  */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
-{
-  return hsc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
-  * @{
-  */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  hsc SMARTCARD handle.
-  * @retval none
-  */
-void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Init the SMARTCARD Callback settings */
-  hsc->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  hsc->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  hsc->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  hsc->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  hsc->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-
-}
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @brief DMA SMARTCARD transmit process complete callback
-  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->TxXferCount = 0U;
-
-  /* Disable the DMA transfer for transmit request by setting the DMAT bit
-     in the USART CR3 register */
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-  /* Enable the SMARTCARD Transmit Complete Interrupt */
-  SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief DMA SMARTCARD receive process complete callback
-  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->RxXferCount = 0U;
-
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the DMA transfer for the receiver request by setting the DMAR bit
-     in the USART CR3 register */
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-  /* At end of Rx process, restore hsc->RxState to Ready */
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx complete callback */
-  hsc->RxCpltCallback(hsc);
-#else
-  /* Call legacy weak Rx complete callback */
-  HAL_SMARTCARD_RxCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief DMA SMARTCARD communication error callback
-  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hsc->RxXferCount = 0U;
-  hsc->TxXferCount = 0U;
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
-  /* Stop SMARTCARD DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
-  if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
-  {
-    SMARTCARD_EndTxTransfer(hsc);
-  }
-
-  /* Stop SMARTCARD DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
-  if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
-  {
-    SMARTCARD_EndRxTransfer(hsc);
-  }
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hsc->ErrorCallback(hsc);
-#else
-  /* Call legacy weak user error callback */
-  HAL_SMARTCARD_ErrorCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  This function handles SMARTCARD Communication Timeout.
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @param  Flag   Specifies the SMARTCARD flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
-      {
-        /* Disable TXE and RXNE interrupts for the interrupt process */
-        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
-
-        hsc->gState= HAL_SMARTCARD_STATE_READY;
-        hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hsc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* At end of Tx process, restore hsc->gState to Ready */
-  hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-}
-
-
-/**
-  * @brief  End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* At end of Rx process, restore hsc->RxState to Ready */
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief Send an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-
-  /* Check that a Tx process is ongoing */
-  if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
-  {
-    hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr & 0xFFU);
-    hsc->pTxBuffPtr++;
-
-    if(--hsc->TxXferCount == 0U)
-    {
-      /* Disable the SMARTCARD Transmit data register empty Interrupt */
-      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the SMARTCARD Transmit Complete Interrupt */
-      SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Disable the SMARTCARD Transmit Complete Interrupt */
-  CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
-
-  /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-  /* Tx process is ended, restore hsc->gState to Ready */
-  hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx complete callback */
-  hsc->TxCpltCallback(hsc);
-#else
-  /* Call legacy weak Tx complete callback */
-  HAL_SMARTCARD_TxCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Receive an amount of data in non blocking mode
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-
-  /* Check that a Rx process is ongoing */
-  if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
-  {
-    *hsc->pRxBuffPtr = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
-    hsc->pRxBuffPtr++;
-
-    if(--hsc->RxXferCount == 0U)
-    {
-      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
-
-      /* Disable the SMARTCARD Parity Error Interrupt */
-      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
-      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
-      /* Rx process is completed, restore hsc->RxState to Ready */
-      hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx complete callback */
-      hsc->RxCpltCallback(hsc);
-#else
-      /* Call legacy weak Rx complete callback */
-      HAL_SMARTCARD_RxCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hsc->RxXferCount = 0x00U;
-  hsc->TxXferCount = 0x00U;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered user error callback */
-  hsc->ErrorCallback(hsc);
-#else
-  /* Call legacy weak user error callback */
-  HAL_SMARTCARD_ErrorCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if(hsc->hdmarx != NULL)
-  {
-    if(hsc->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hsc->TxXferCount = 0x00U;
-  hsc->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Restore hsc->gState and hsc->RxState to Ready */
-  hsc->gState  = HAL_SMARTCARD_STATE_READY;
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hsc->AbortCpltCallback(hsc);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_SMARTCARD_AbortCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if(hsc->hdmatx != NULL)
-  {
-    if(hsc->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  hsc->TxXferCount = 0x00U;
-  hsc->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-  /* Restore hsc->gState and hsc->RxState to Ready */
-  hsc->gState  = HAL_SMARTCARD_STATE_READY;
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  hsc->AbortCpltCallback(hsc);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_SMARTCARD_AbortCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
-  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->TxXferCount = 0x00U;
-
-  /* Restore hsc->gState to Ready */
-  hsc->gState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  hsc->AbortTransmitCpltCallback(hsc);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
-  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->RxXferCount = 0x00U;
-
-  /* Restore hsc->RxState to Ready */
-  hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  hsc->AbortReceiveCpltCallback(hsc);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
-}
-
-/**
-  * @brief Configure the SMARTCARD peripheral
-  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint32_t tmpreg = 0x00U;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-  assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
-  assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
-  assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
-  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
-  assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
-  assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
-  assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
-  assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
-  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
-
-  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
-     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
-  /*---------------------------- USART CR2 Configuration ---------------------*/
-  tmpreg = hsc->Instance->CR2;
-  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
-  /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
-  /* Set CPOL bit according to hsc->Init.CLKPolarity value */
-  /* Set CPHA bit according to hsc->Init.CLKPhase value */
-  /* Set LBCL bit according to hsc->Init.CLKLastBit value */
-  /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
-  tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
-                      hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
-  /* Write to USART CR2 */
-  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
-
-  tmpreg = hsc->Instance->CR2;
-
-  /* Clear STOP[13:12] bits */
-  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
-  /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
-  tmpreg |= (uint32_t)(hsc->Init.StopBits);
-
-  /* Write to USART CR2 */
-  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = hsc->Instance->CR1;
-
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-                                   USART_CR1_RE));
-
-  /* Configure the SMARTCARD Word Length, Parity and mode:
-     Set the M bits according to hsc->Init.WordLength value
-     Set PCE and PS bits according to hsc->Init.Parity value
-     Set TE and RE bits according to hsc->Init.Mode value */
-  tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
-
-  /* Write to USART CR1 */
-  WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if(hsc->Instance == USART1)
-  {
-    pclk = HAL_RCC_GetPCLK2Freq();
-    hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
-  }
-  else
-  {
-    pclk = HAL_RCC_GetPCLK1Freq();
-    hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c
deleted file mode 100644
index 51400658d6a..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c
+++ /dev/null
@@ -1,3940 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi.c
-  * @author  MCD Application Team
-  * @brief   SPI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi;
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
-          (##) Enable the SPIx interface clock
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters
-              (+++) Configure the DMA Tx or Rx Stream/Channel
-              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
-
-      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customized HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-     [..]
-       Master Receive mode restriction:
-      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
-          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
-          does not initiate a new transfer the following procedure has to be respected:
-          (##) HAL_SPI_DeInit()
-          (##) HAL_SPI_Init()
-     [..]
-       Callback registration:
-
-      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
-          allows the user to configure dynamically the driver callbacks.
-          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
-
-          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
-            (++) TxCpltCallback        : SPI Tx Completed callback
-            (++) RxCpltCallback        : SPI Rx Completed callback
-            (++) TxRxCpltCallback      : SPI TxRx Completed callback
-            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
-            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
-            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
-            (++) ErrorCallback         : SPI Error callback
-            (++) AbortCpltCallback     : SPI Abort callback
-            (++) MspInitCallback       : SPI Msp Init callback
-            (++) MspDeInitCallback     : SPI Msp DeInit callback
-          This function takes as parameters the HAL peripheral handle, the Callback ID
-          and a pointer to the user callback function.
-
-
-      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
-          weak function.
-          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
-          and the Callback ID.
-          This function allows to reset following callbacks:
-            (++) TxCpltCallback        : SPI Tx Completed callback
-            (++) RxCpltCallback        : SPI Rx Completed callback
-            (++) TxRxCpltCallback      : SPI TxRx Completed callback
-            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
-            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
-            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
-            (++) ErrorCallback         : SPI Error callback
-            (++) AbortCpltCallback     : SPI Abort callback
-            (++) MspInitCallback       : SPI Msp Init callback
-            (++) MspDeInitCallback     : SPI Msp DeInit callback
-
-       [..]
-       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
-       all callbacks are set to the corresponding weak functions:
-       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
-       Exception done for MspInit and MspDeInit functions that are
-       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
-       these callbacks are null (not registered beforehand).
-       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
-       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
-       [..]
-       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
-       Exception done MspInit/MspDeInit functions that can be registered/unregistered
-       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
-       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-       Then, the user first registers the MspInit/MspDeInit user callbacks
-       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
-       or HAL_SPI_Init() function.
-
-       [..]
-       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
-       not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
-
-     [..]
-       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
-       the following table resume the max SPI frequency reached with data size 8bits/16bits,
-         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
-
-  @endverbatim
-
-  Additional table :
-
-       DataSize = SPI_DATASIZE_8BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Transfer mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-
-       DataSize = SPI_DATASIZE_16BIT:
-       +----------------------------------------------------------------------------------------------+
-       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
-       | Process | Transfer mode  |---------------------|----------------------|----------------------|
-       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
-       |==============================================================================================|
-       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
-       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
-       |=========|================|==========|==========|===========|==========|===========|==========|
-       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
-       |         |----------------|----------|----------|-----------|----------|-----------|----------|
-       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
-       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
-       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
-       +----------------------------------------------------------------------------------------------+
-       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
-             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
-       @note
-            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
-            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
-            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_DEFAULT_TIMEOUT 100U
-#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs             */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with
-          the selected configuration:
-        (++) Mode
-        (++) Direction
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
-          of the selected SPIx peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the SPI according to the specified parameters
-  *         in the SPI_InitTypeDef and initialize the associated handle.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  /* TI mode is not supported on all devices in stm32l1xx serie.
-     TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
-  {
-    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-
-    if (hspi->Init.Mode == SPI_MODE_MASTER)
-    {
-      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-    }
-    else
-    {
-      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
-      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
-    }
-  }
-  else
-  {
-    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-
-    /* Force polarity and phase to TI protocaol requirements */
-    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
-    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
-  }
-#if (USE_SPI_CRC != 0U)
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-  }
-#else
-  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
-  if (hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hspi->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    /* Init the SPI Callback settings */
-    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
-    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
-    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
-    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
-    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
-    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
-    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
-    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
-
-    if (hspi->MspInitCallback == NULL)
-    {
-      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    hspi->MspInitCallback(hspi);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
-  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
-  Communication speed, First bit and CRC calculation state */
-  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
-                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
-                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
-                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
-                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
-                                  (hspi->Init.NSS & SPI_CR1_SSM) |
-                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
-                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
-                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
-
-#if defined(SPI_CR2_FRF)
-  /* Configure : NSS management, TI Mode */
-  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
-#else
-  /* Configure : NSS management */
-  WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
-#endif
-
-#if (USE_SPI_CRC != 0U)
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
-  /* Configure : CRC Polynomial */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
-  }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State     = HAL_SPI_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  De-Initialize the SPI peripheral.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if (hspi == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check SPI Instance parameter */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  if (hspi->MspDeInitCallback == NULL)
-  {
-    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  hspi->MspDeInitCallback(hspi);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the SPI MSP.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize the SPI MSP.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit should be implemented in the user file
-   */
-}
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  Register a User SPI Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI.
-  * @param  CallbackID ID of the callback to be registered
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
-                                           pSPI_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if (HAL_SPI_STATE_READY == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_TX_COMPLETE_CB_ID :
-        hspi->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_RX_COMPLETE_CB_ID :
-        hspi->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
-        hspi->TxRxCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
-        hspi->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
-        hspi->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
-        hspi->TxRxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_ERROR_CB_ID :
-        hspi->ErrorCallback = pCallback;
-        break;
-
-      case HAL_SPI_ABORT_CB_ID :
-        hspi->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SPI_STATE_RESET == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = pCallback;
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-  return status;
-}
-
-/**
-  * @brief  Unregister an SPI Callback
-  *         SPI callback is redirected to the weak predefined callback
-  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI.
-  * @param  CallbackID ID of the callback to be unregistered
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  if (HAL_SPI_STATE_READY == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_TX_COMPLETE_CB_ID :
-        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
-        break;
-
-      case HAL_SPI_RX_COMPLETE_CB_ID :
-        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
-        break;
-
-      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
-        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
-        break;
-
-      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
-        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
-        break;
-
-      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
-        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
-        break;
-
-      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
-        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
-        break;
-
-      case HAL_SPI_ERROR_CB_ID :
-        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
-        break;
-
-      case HAL_SPI_ABORT_CB_ID :
-        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
-        break;
-
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_SPI_STATE_RESET == hspi->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_SPI_MSPINIT_CB_ID :
-        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_SPI_MSPDEINIT_CB_ID :
-        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-  return status;
-}
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
-  *  @brief   Data transfers functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
- [..]
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-            or DMA, These APIs return the HAL status.
-            The end of the data processing will be indicated through the
-            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
-            will be executed respectively at the end of the transmit or Receive process
-            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
-        exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  uint16_t initial_TxXferCount;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-  initial_TxXferCount = Size;
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit data in 16 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    /* Transmit data in 16 Bit mode */
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint16_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  /* Transmit data in 8 Bit mode */
-  else
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while (hspi->TxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send data */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
-      {
-        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint8_t);
-        hspi->TxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error:
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be received
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-  uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-    /* this is done to handle the CRCNEXT before the latest data */
-    hspi->RxXferCount--;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Configure communication direction: 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Receive data in 8 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        /* read the received data */
-        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint8_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Transfer loop */
-    while (hspi->RxXferCount > 0U)
-    {
-      /* Check the RXNE flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
-      {
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        /* Timeout management */
-        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-        {
-          errorcode = HAL_TIMEOUT;
-          goto error;
-        }
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Handle the CRC Transmission */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* freeze the CRC before the latest data */
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
-    /* Read the latest data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* the latest data has not been received */
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Receive last data in 16 Bit mode */
-    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-    }
-    /* Receive last data in 8 Bit mode */
-    else
-    {
-      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
-    }
-
-    /* Wait the CRC data */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-
-    /* Read CRC to Flush DR and RXNE flag */
-    tmpreg = READ_REG(hspi->Instance->DR);
-    /* To avoid GCC warning */
-    UNUSED(tmpreg);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    errorcode = HAL_ERROR;
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @param  Size amount of data to be sent and received
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout)
-{
-  uint16_t             initial_TxXferCount;
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  uint32_t             tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Variable used to alternate Rx and Tx during transfer */
-  uint32_t             txallowed = 1U;
-  HAL_StatusTypeDef    errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-  initial_TxXferCount = Size;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferCount = Size;
-  hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferCount = Size;
-  hspi->TxXferSize  = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Transmit and Receive data in 16 Bit mode */
-  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint16_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
-      {
-        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint16_t);
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Check RXNE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
-      {
-        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
-        hspi->pRxBuffPtr += sizeof(uint16_t);
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-  /* Transmit and Receive data in 8 Bit mode */
-  else
-  {
-    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
-    {
-      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
-      hspi->pTxBuffPtr += sizeof(uint8_t);
-      hspi->TxXferCount--;
-    }
-    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
-    {
-      /* Check TXE flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
-      {
-        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr++;
-        hspi->TxXferCount--;
-        /* Next Data is a reception (Rx). Tx not allowed */
-        txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
-        /* Enable CRC Transmission */
-        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-#endif /* USE_SPI_CRC */
-      }
-
-      /* Wait until RXNE flag is reset */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
-      {
-        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr++;
-        hspi->RxXferCount--;
-        /* Next Data is a Transmission (Tx). Tx is allowed */
-        txallowed = 1U;
-      }
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
-      {
-        errorcode = HAL_TIMEOUT;
-        goto error;
-      }
-    }
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Read CRC from DR to close CRC calculation process */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until TXE flag */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
-    {
-      /* Error on the CRC reception */
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      errorcode = HAL_TIMEOUT;
-      goto error;
-    }
-    /* Read CRC */
-    tmpreg = READ_REG(hspi->Instance->DR);
-    /* To avoid GCC warning */
-    UNUSED(tmpreg);
-  }
-
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    /* Clear CRC Flag */
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
-    errorcode = HAL_ERROR;
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
-  {
-    errorcode = HAL_ERROR;
-    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    goto error;
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-error :
-  hspi->State = HAL_SPI_STATE_READY;
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-  hspi->RxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->TxISR = SPI_TxISR_16BIT;
-  }
-  else
-  {
-    hspi->TxISR = SPI_TxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pTxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-  hspi->TxISR       = NULL;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->RxISR = SPI_RxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR = SPI_RxISR_8BIT;
-  }
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Note : The SPI must be enabled after unlocking current process
-            to avoid the risk of SPI interrupt handle execution before current
-            process unlock */
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @param  Size amount of data to be sent and received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef    errorcode = HAL_OK;
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Set the function for IT treatment */
-  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-  {
-    hspi->RxISR     = SPI_2linesRxISR_16BIT;
-    hspi->TxISR     = SPI_2linesTxISR_16BIT;
-  }
-  else
-  {
-    hspi->RxISR     = SPI_2linesRxISR_8BIT;
-    hspi->TxISR     = SPI_2linesTxISR_8BIT;
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Enable TXE, RXNE and ERR interrupt */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit an amount of data in non-blocking mode with DMA.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check tx dma handle */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_TX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->pRxBuffPtr  = (uint8_t *)NULL;
-  hspi->TxISR       = NULL;
-  hspi->RxISR       = NULL;
-  hspi->RxXferSize  = 0U;
-  hspi->RxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_TX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI TxDMA Half transfer complete callback */
-  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
-  /* Set the SPI TxDMA transfer complete callback */
-  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmatx->XferAbortCallback = NULL;
-
-  /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
-                                 hspi->TxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pData pointer to data buffer
-  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check rx dma handle */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-
-    /* Check tx dma handle */
-    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  if (hspi->State != HAL_SPI_STATE_READY)
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Set the transaction information */
-  hspi->State       = HAL_SPI_STATE_BUSY_RX;
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pRxBuffPtr  = (uint8_t *)pData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /*Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-  hspi->TxXferSize  = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Configure communication direction : 1Line */
-  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
-  {
-    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
-    __HAL_SPI_DISABLE(hspi);
-    SPI_1LINE_RX(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Set the SPI RxDMA Half transfer complete callback */
-  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
-  /* Set the SPI Rx DMA transfer complete callback */
-  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
-                                 hspi->RxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  pTxData pointer to transmission data buffer
-  * @param  pRxData pointer to reception data buffer
-  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
-  * @param  Size amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size)
-{
-  uint32_t             tmp_mode;
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  /* Check rx & tx dma handles */
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
-  /* Check Direction parameter */
-  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) ||
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
-  {
-    errorcode = HAL_BUSY;
-    goto error;
-  }
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
-  {
-    errorcode = HAL_ERROR;
-    goto error;
-  }
-
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
-
-  /* Set the transaction information */
-  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
-  hspi->TxXferSize  = Size;
-  hspi->TxXferCount = Size;
-  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
-  hspi->RxXferSize  = Size;
-  hspi->RxXferCount = Size;
-
-  /* Init field not used in handle to zero */
-  hspi->RxISR       = NULL;
-  hspi->TxISR       = NULL;
-
-#if (USE_SPI_CRC != 0U)
-  /* Reset CRC Calculation */
-  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    SPI_RESET_CRC(hspi);
-  }
-#endif /* USE_SPI_CRC */
-
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
-  }
-
-  /* Set the DMA error callback */
-  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-  /* Set the DMA AbortCpltCallback */
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
-                                 hspi->RxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Enable Rx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-  is performed in DMA reception complete callback  */
-  hspi->hdmatx->XferHalfCpltCallback = NULL;
-  hspi->hdmatx->XferCpltCallback     = NULL;
-  hspi->hdmatx->XferErrorCallback    = NULL;
-  hspi->hdmatx->XferAbortCallback    = NULL;
-
-  /* Enable the Tx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
-                                 hspi->TxXferCount))
-  {
-    /* Update SPI error code */
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
-
-    hspi->State = HAL_SPI_STATE_READY;
-    goto error;
-  }
-
-  /* Check if the SPI is already enabled */
-  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
-  {
-    /* Enable SPI peripheral */
-    __HAL_SPI_ENABLE(hspi);
-  }
-  /* Enable the SPI Error Interrupt Bit */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
-
-  /* Enable Tx DMA Request */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (blocking mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-  __IO uint32_t count;
-  __IO uint32_t resetcount;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-  count = resetcount;
-
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  /* Disable the SPI DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmatx->XferAbortCallback = NULL;
-
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable Tx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
-      /* Wait until TXE flag is set */
-      do
-      {
-        if (count == 0U)
-        {
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          break;
-        }
-        count--;
-      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-    }
-  }
-
-  /* Disable the SPI DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Set the SPI DMA Abort callback :
-      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
-      hspi->hdmarx->XferAbortCallback = NULL;
-
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
-      {
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-
-      /* Disable peripheral */
-      __HAL_SPI_DISABLE(hspi);
-
-      /* Disable Rx DMA Request */
-      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
-    }
-  }
-  /* Reset Tx and Rx transfer counters */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check error during Abort procedure */
-  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-  {
-    /* return HAL_Error in case of error during Abort procedure */
-    errorcode = HAL_ERROR;
-  }
-  else
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-#if defined(SPI_CR2_FRF)
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-#endif
-
-  /* Restore hspi->state to ready */
-  hspi->State = HAL_SPI_STATE_READY;
-
-  return errorcode;
-}
-
-/**
-  * @brief  Abort ongoing transfer (Interrupt mode).
-  * @param  hspi SPI handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
-  *         started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable SPI Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode;
-  uint32_t abortcplt ;
-  __IO uint32_t count;
-  __IO uint32_t resetcount;
-
-  /* Initialized local variable  */
-  errorcode = HAL_OK;
-  abortcplt = 1U;
-  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-  count = resetcount;
-
-  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
-  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
-  {
-    hspi->TxISR = SPI_AbortTx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
-  {
-    hspi->RxISR = SPI_AbortRx_ISR;
-    /* Wait HAL_SPI_STATE_ABORT state */
-    do
-    {
-      if (count == 0U)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-        break;
-      }
-      count--;
-    } while (hspi->State != HAL_SPI_STATE_ABORT);
-    /* Reset Timeout Counter */
-    count = resetcount;
-  }
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (hspi->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-    {
-      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (hspi->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-    {
-      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
-    }
-    else
-    {
-      hspi->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the SPI DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
-  {
-    /* Abort the SPI DMA Tx Stream/Channel */
-    if (hspi->hdmatx != NULL)
-    {
-      /* Abort DMA Tx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
-      {
-        hspi->hdmatx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-  /* Disable the SPI DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
-  {
-    /* Abort the SPI DMA Rx Stream/Channel */
-    if (hspi->hdmarx != NULL)
-    {
-      /* Abort DMA Rx Handle linked to SPI Peripheral */
-      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
-      {
-        hspi->hdmarx->XferAbortCallback = NULL;
-        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
-      }
-      else
-      {
-        abortcplt = 0U;
-      }
-    }
-  }
-
-  if (abortcplt == 1U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    hspi->RxXferCount = 0U;
-    hspi->TxXferCount = 0U;
-
-    /* Check error during Abort procedure */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
-    {
-      /* return HAL_Error in case of error during Abort procedure */
-      errorcode = HAL_ERROR;
-    }
-    else
-    {
-      /* Reset errorCode */
-      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-    }
-
-    /* Clear the Error flags in the SR register */
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-#if defined(SPI_CR2_FRF)
-    __HAL_SPI_CLEAR_FREFLAG(hspi);
-#endif
-
-    /* Restore hspi->State to Ready */
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->AbortCpltCallback(hspi);
-#else
-    HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-
-  return errorcode;
-}
-
-/**
-  * @brief  Pause the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resume the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA Transfer.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-
-  /* Abort the SPI DMA tx Stream/Channel  */
-  if (hspi->hdmatx != NULL)
-  {
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-      errorcode = HAL_ERROR;
-    }
-  }
-  /* Abort the SPI DMA rx Stream/Channel  */
-  if (hspi->hdmarx != NULL)
-  {
-    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-      errorcode = HAL_ERROR;
-    }
-  }
-
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-  hspi->State = HAL_SPI_STATE_READY;
-  return errorcode;
-}
-
-/**
-  * @brief  Handle SPI interrupt request.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for the specified SPI module.
-  * @retval None
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  uint32_t itsource = hspi->Instance->CR2;
-  uint32_t itflag   = hspi->Instance->SR;
-
-  /* SPI in mode Receiver ----------------------------------------------------*/
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
-      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Transmitter -------------------------------------------------*/
-  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  /* SPI in Error Treatment --------------------------------------------------*/
-#if defined(SPI_CR2_FRF)
-  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
-       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
-#else
-  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
-      && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
-#endif
-  {
-    /* SPI Overrun error interrupt occurred ----------------------------------*/
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
-    {
-      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-      }
-      else
-      {
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);
-        return;
-      }
-    }
-
-    /* SPI Mode Fault error interrupt occurred -------------------------------*/
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-
-    /* SPI Frame error interrupt occurred ------------------------------------*/
-#if defined(SPI_CR2_FRF)
-    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-#endif
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Disable all interrupts */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Disable the SPI DMA requests if enabled */
-      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
-      {
-        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
-        /* Abort the SPI DMA Rx channel */
-        if (hspi->hdmarx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
-          {
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          }
-        }
-        /* Abort the SPI DMA Tx channel */
-        if (hspi->hdmatx != NULL)
-        {
-          /* Set the SPI DMA Abort callback :
-          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
-          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
-          {
-            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-          }
-        }
-      }
-      else
-      {
-        /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->ErrorCallback(hspi);
-#else
-        HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-    }
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx and Rx Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx and Rx Half Transfer callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SPI error callback.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback should be implemented in the user file
-   */
-  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred
-   */
-}
-
-/**
-  * @brief  SPI Abort Complete callback.
-  * @param  hspi SPI handle.
-  * @retval None
-  */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hspi);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
-  * @brief   SPI control functions
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI handle state.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI handle state */
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval SPI error code in bitmap format
-  */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  /* Return SPI ErrorCode */
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Private_Functions
-  * @brief   Private functions
-  * @{
-  */
-
-/**
-  * @brief  DMA SPI transmit process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->TxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user Tx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxCpltCallback(hspi);
-#else
-  HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until RXNE flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        /* Error on the CRC reception */
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC */
-      tmpreg = READ_REG(hspi->Instance->DR);
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Check if we are in Master RX 2 line mode */
-    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-    }
-    else
-    {
-      /* Normal case */
-      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-    }
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
-    }
-
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->RxCpltCallback(hspi);
-#else
-  HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI transmit receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  uint32_t tickstart;
-#if (USE_SPI_CRC != 0U)
-  __IO uint32_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* DMA Normal Mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-#if (USE_SPI_CRC != 0U)
-    /* CRC handling */
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait the CRC data */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      }
-      /* Read CRC to Flush DR and RXNE flag */
-      tmpreg = READ_REG(hspi->Instance->DR);
-      /* To avoid GCC warning */
-      UNUSED(tmpreg);
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Check the end of the transaction */
-    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Rx/Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0U;
-    hspi->RxXferCount = 0U;
-    hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-    /* Check if CRC error occurred */
-    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-#endif /* USE_SPI_CRC */
-
-    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      return;
-    }
-  }
-  /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxRxCpltCallback(hspi);
-#else
-  HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half transmit process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Tx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_TxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half receive process complete callback
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user Rx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->RxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_RxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI half transmit receive process complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Call user TxRx half complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->TxRxHalfCpltCallback(hspi);
-#else
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI communication error callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Stop the disable DMA transfer on SPI side */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-  hspi->State = HAL_SPI_STATE_READY;
-  /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->ErrorCallback(hspi);
-#else
-  HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->ErrorCallback(hspi);
-#else
-  HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-  __IO uint32_t count;
-
-  hspi->hdmatx->XferAbortCallback = NULL;
-  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Disable Tx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmarx != NULL)
-  {
-    if (hspi->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-#if defined(SPI_CR2_FRF)
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-#endif
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->AbortCpltCallback(hspi);
-#else
-  HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SPI Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  hspi->hdmarx->XferAbortCallback = NULL;
-
-  /* Disable Rx DMA Request */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-  /* Check Busy flag */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-  }
-
-  /* Check if an Abort process is still ongoing */
-  if (hspi->hdmatx != NULL)
-  {
-    if (hspi->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
-  hspi->RxXferCount = 0U;
-  hspi->TxXferCount = 0U;
-
-  /* Check no error during Abort procedure */
-  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
-  {
-    /* Reset errorCode */
-    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  }
-
-  /* Clear the Error flags in the SR register */
-  __HAL_SPI_CLEAR_OVRFLAG(hspi);
-#if defined(SPI_CR2_FRF)
-  __HAL_SPI_CLEAR_FREFLAG(hspi);
-#endif
-
-  /* Restore hspi->State to Ready */
-  hspi->State  = HAL_SPI_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  hspi->AbortCpltCallback(hspi);
-#else
-  HAL_SPI_AbortCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 8bit mode */
-  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
-  hspi->pRxBuffPtr++;
-  hspi->RxXferCount--;
-
-  /* Check end of the reception */
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE  and ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t  * ptmpreg8;
-  __IO uint8_t  tmpreg8 = 0;
-
-  /* Initialize the 8bit temporary pointer */
-  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
-  /* Read 8bit CRC to flush Data Register */
-  tmpreg8 = *ptmpreg8;
-  /* To avoid GCC warning */
-  UNUSED(tmpreg8);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  if (hspi->TxXferCount == 0U)
-  {
-    SPI_CloseRxTx_ISR(hspi);
-  }
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr++;
-  hspi->TxXferCount--;
-
-  /* Check the end of the transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 16 Bit mode */
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable RXNE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-    if (hspi->TxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-
-  /* Read 16bit CRC to flush Data Register */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);  
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
-  SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  /* Enable CRC Transmission */
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Set CRC Next Bit to send CRC */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      /* Disable TXE interrupt */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-      return;
-    }
-#endif /* USE_SPI_CRC */
-
-    /* Disable TXE interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
-    if (hspi->RxXferCount == 0U)
-    {
-      SPI_CloseRxTx_ISR(hspi);
-    }
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 8-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint8_t  * ptmpreg8;
-  __IO uint8_t  tmpreg8 = 0;
-
-  /* Initialize the 8bit temporary pointer */
-  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
-  /* Read 8bit CRC to flush Data Register */
-  tmpreg8 = *ptmpreg8;
-  /* To avoid GCC warning */
-  UNUSED(tmpreg8);
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the receive 8-bit in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
-  hspi->pRxBuffPtr++;
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR =  SPI_RxISR_8BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
-  * @brief  Manage the CRC 16-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-
-  /* Read 16bit CRC to flush Data Register */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
-  * @brief  Manage the 16-bit receive in Interrupt context.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
-  hspi->pRxBuffPtr += sizeof(uint16_t);
-  hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
-  /* Enable CRC Transmission */
-  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-  {
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-#endif /* USE_SPI_CRC */
-
-  if (hspi->RxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      hspi->RxISR = SPI_RxISR_16BITCRC;
-      return;
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseRx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 8-bit transmit in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr++;
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle the data 16-bit transmit in Interrupt mode.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 16 Bit mode */
-  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
-  hspi->pTxBuffPtr += sizeof(uint16_t);
-  hspi->TxXferCount--;
-
-  if (hspi->TxXferCount == 0U)
-  {
-#if (USE_SPI_CRC != 0U)
-    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Enable CRC Transmission */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-#endif /* USE_SPI_CRC */
-    SPI_CloseTx_ISR(hspi);
-  }
-}
-
-/**
-  * @brief  Handle SPI Communication Timeout.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *              the configuration information for SPI module.
-  * @param  Flag SPI flag to check
-  * @param  State flag state to check
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
-                                                       uint32_t Timeout, uint32_t Tickstart)
-{
-  __IO uint32_t count;
-  uint32_t tmp_timeout;
-  uint32_t tmp_tickstart;
-
-  /* Adjust Timeout value  in case of end of transfer */
-  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
-  tmp_tickstart = HAL_GetTick();
-
-  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
-  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
-
-  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
-  {
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
-      {
-        /* Disable the SPI and reset the CRC: the CRC value should be cleared
-           on both master and slave sides in order to resynchronize the master
-           and slave for their respective CRC calculation */
-
-        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-        {
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-        }
-
-        /* Reset CRC Calculation */
-        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          SPI_RESET_CRC(hspi);
-        }
-
-        hspi->State = HAL_SPI_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
-
-        return HAL_TIMEOUT;
-      }
-      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
-      if(count == 0U)
-      {
-        tmp_timeout = 0U;
-      }
-      count--;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the check of the RX transaction complete.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
-{
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
-                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-  {
-    /* Disable SPI peripheral */
-    __HAL_SPI_DISABLE(hspi);
-  }
-
-  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
-  if (hspi->Init.Mode == SPI_MODE_MASTER)
-  {
-    if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
-    {
-      /* Control the BSY flag */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-        return HAL_TIMEOUT;
-      }
-    }
-    else
-    {
-      /* Wait the RXNE reset */
-      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  else
-  {
-    /* Wait the RXNE reset */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the check of the RXTX or TX transaction complete.
-  * @param  hspi SPI handle
-  * @param  Timeout Timeout duration
-  * @param  Tickstart tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
-  /* Timeout in µs */
-  __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
-  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
-  if (hspi->Init.Mode == SPI_MODE_MASTER)
-  {
-    /* Control the BSY flag */
-    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-  }
-  else
-  {
-    /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
-    * If Timeout is reached, the transfer is considered as finish.
-    * User have to calculate the timeout value to fit with the time of 1 byte transfer.
-    * This time is directly link with the SPI clock from Master device.
-    */
-    do
-    {
-      if (count == 0U)
-      {
-        break;
-      }
-      count--;
-    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle the end of the RXTX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
-
-  /* Disable ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    hspi->State = HAL_SPI_STATE_READY;
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->RxCpltCallback(hspi);
-#else
-        HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        hspi->State = HAL_SPI_STATE_READY;
-        /* Call user TxRx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-        hspi->TxRxCpltCallback(hspi);
-#else
-        HAL_SPI_TxRxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-      }
-    }
-    else
-    {
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the RX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-  hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
-  /* Check if CRC error occurred */
-  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-#endif /* USE_SPI_CRC */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
-    {
-      /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->RxCpltCallback(hspi);
-#else
-      HAL_SPI_RxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-    else
-    {
-      /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-      hspi->ErrorCallback(hspi);
-#else
-      HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-    }
-#if (USE_SPI_CRC != 0U)
-  }
-#endif /* USE_SPI_CRC */
-}
-
-/**
-  * @brief  Handle the end of the TX transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  uint32_t tickstart;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Init tickstart for timeout management*/
-  tickstart = HAL_GetTick();
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Disable TXE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-  /* Check the end of the transaction */
-  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Clear overrun flag in 2 Lines communication mode because received is not read */
-  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  hspi->State = HAL_SPI_STATE_READY;
-  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    /* Call user error callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->ErrorCallback(hspi);
-#else
-    HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* Call user Rx complete callback */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-    hspi->TxCpltCallback(hspi);
-#else
-    HAL_SPI_TxCpltCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Handle abort a Rx transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
-  __IO uint32_t tmpreg = 0U;
-  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
-  /* Wait until TXE flag is set */
-  do
-  {
-    if (count == 0U)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
-      break;
-    }
-    count--;
-  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
-  /* Flush Data Register by a blank read */
-  tmpreg = READ_REG(hspi->Instance->DR);
-  /* To avoid GCC warning */
-  UNUSED(tmpreg);
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @brief  Handle abort a Tx or Rx/Tx transaction.
-  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
-  *               the configuration information for SPI module.
-  * @retval None
-  */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
-  /* Disable TXEIE interrupt */
-  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
-
-  /* Disable SPI Peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  hspi->State = HAL_SPI_STATE_ABORT;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c
deleted file mode 100644
index 6c9e208ff94..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_sram.c
+++ /dev/null
@@ -1,1112 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sram.c
-  * @author  MCD Application Team
-  * @brief   SRAM HAL module driver.
-  *          This file provides a generic firmware to drive SRAM memories
-  *          mounted as external device.
-  *
-  @verbatim
-  ==============================================================================
-                          ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver is a generic layered driver which contains a set of APIs used to
-    control SRAM memories. It uses the FSMC layer functions to interface
-    with SRAM devices.
-    The following sequence should be followed to configure the FSMC to interface
-    with SRAM/PSRAM memories:
-
-   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
-          SRAM_HandleTypeDef  hsram; and:
-
-       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
-            values of the structure member.
-
-       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
-            base register instance for NOR or SRAM device
-
-       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
-            base register instance for NOR or SRAM extended mode
-
-   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
-       mode timings; for example:
-          FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
-      and fill its fields with the allowed values of the structure member.
-
-   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
-       performs the following sequence:
-
-       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
-       (##) Control register configuration using the FSMC NORSRAM interface function
-            FSMC_NORSRAM_Init()
-       (##) Timing register configuration using the FSMC NORSRAM interface function
-            FSMC_NORSRAM_Timing_Init()
-       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
-            FSMC_NORSRAM_Extended_Timing_Init()
-       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
-
-   (#) At this stage you can perform read/write accesses from/to the memory connected
-       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
-       following APIs:
-       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
-       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-
-   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
-       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
-
-   (#) You can continuously monitor the SRAM device HAL state by calling the function
-       HAL_SRAM_GetState()
-
-       *** Callback registration ***
-    =============================================
-    [..]
-      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
-      allows the user to configure dynamically the driver callbacks.
-
-      Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
-      it allows to register following callbacks:
-        (+) MspInitCallback    : SRAM MspInit.
-        (+) MspDeInitCallback  : SRAM MspDeInit.
-      This function takes as parameters the HAL peripheral handle, the Callback ID
-      and a pointer to the user callback function.
-
-      Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
-        (+) MspInitCallback    : SRAM MspInit.
-        (+) MspDeInitCallback  : SRAM MspDeInit.
-      This function) takes as parameters the HAL peripheral handle and the Callback ID.
-
-      By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
-      Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
-      and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
-      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-      Callbacks can be registered/unregistered in READY state only.
-      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-      during the Init/DeInit.
-      In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
-      or @ref HAL_SRAM_Init function.
-
-      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#if defined(FSMC_BANK1)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-
-/** @defgroup SRAM SRAM
-  * @brief SRAM driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
-static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
-static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
-  * @{
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions.
-  *
-  @verbatim
-  ==============================================================================
-           ##### SRAM Initialization and de_initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to initialize/de-initialize
-          the SRAM memory
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Performs the SRAM device initialization sequence
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  Timing Pointer to SRAM control timing structure
-  * @param  ExtTiming Pointer to SRAM extended mode timing structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
-                                FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
-  /* Check the SRAM handle parameter */
-  if (hsram == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if (hsram->State == HAL_SRAM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hsram->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-    if (hsram->MspInitCallback == NULL)
-    {
-      hsram->MspInitCallback = HAL_SRAM_MspInit;
-    }
-    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
-    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
-    /* Init the low level hardware */
-    hsram->MspInitCallback(hsram);
-#else
-    /* Initialize the low level hardware (MSP) */
-    HAL_SRAM_MspInit(hsram);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-  }
-
-  /* Initialize SRAM control Interface */
-  (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
-
-  /* Initialize SRAM timing Interface */
-  (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
-
-  /* Initialize SRAM extended mode timing Interface */
-  (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
-                                         hsram->Init.ExtendedMode);
-
-  /* Enable the NORSRAM device */
-  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
-
-  /* Initialize the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Performs the SRAM device De-initialization sequence.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  if (hsram->MspDeInitCallback == NULL)
-  {
-    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
-  }
-
-  /* DeInit the low level hardware */
-  hsram->MspDeInitCallback(hsram);
-#else
-  /* De-Initialize the low level hardware (MSP) */
-  HAL_SRAM_MspDeInit(hsram);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-
-  /* Configure the SRAM registers with their reset values */
-  (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
-
-  /* Reset the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  SRAM MSP Init.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsram);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SRAM MSP DeInit.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hsram);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA transfer complete callback.
-  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA transfer complete error callback.
-  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdma);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
-  * @brief    Input Output and memory control functions
-  *
-  @verbatim
-  ==============================================================================
-                  ##### SRAM Input and Output functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to use and control the SRAM memory
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads 8-bit buffer from SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to read start address
-  * @param  pDstBuffer Pointer to destination buffer
-  * @param  BufferSize Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
-                                   uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
-  uint8_t *pdestbuff = pDstBuffer;
-  HAL_SRAM_StateTypeDef state = hsram->State;
-
-  /* Check the SRAM controller state */
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Read data from memory */
-    for (size = BufferSize; size != 0U; size--)
-    {
-      *pdestbuff = *psramaddress;
-      pdestbuff++;
-      psramaddress++;
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Writes 8-bit buffer to SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to write start address
-  * @param  pSrcBuffer Pointer to source buffer to write
-  * @param  BufferSize Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
-                                    uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
-  uint8_t *psrcbuff = pSrcBuffer;
-
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Write data to memory */
-    for (size = BufferSize; size != 0U; size--)
-    {
-      *psramaddress = *psrcbuff;
-      psrcbuff++;
-      psramaddress++;
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Reads 16-bit buffer from SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to read start address
-  * @param  pDstBuffer Pointer to destination buffer
-  * @param  BufferSize Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
-                                    uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint32_t *psramaddress = pAddress;
-  uint16_t *pdestbuff = pDstBuffer;
-  uint8_t limit;
-  HAL_SRAM_StateTypeDef state = hsram->State;
-
-  /* Check the SRAM controller state */
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Check if the size is a 32-bits multiple */
-    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
-
-    /* Read data from memory */
-    for (size = BufferSize; size != limit; size -= 2U)
-    {
-      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
-      pdestbuff++;
-      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
-      pdestbuff++;
-      psramaddress++;
-    }
-
-    /* Read last 16-bits if size is not 32-bits multiple */
-    if (limit != 0U)
-    {
-      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Writes 16-bit buffer to SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to write start address
-  * @param  pSrcBuffer Pointer to source buffer to write
-  * @param  BufferSize Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
-                                     uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint32_t *psramaddress = pAddress;
-  uint16_t *psrcbuff = pSrcBuffer;
-  uint8_t limit;
-
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Check if the size is a 32-bits multiple */
-    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
-
-    /* Write data to memory */
-    for (size = BufferSize; size != limit; size -= 2U)
-    {
-      *psramaddress = (uint32_t)(*psrcbuff);
-      psrcbuff++;
-      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
-      psrcbuff++;
-      psramaddress++;
-    }
-
-    /* Write last 16-bits if size is not 32-bits multiple */
-    if (limit != 0U)
-    {
-      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Reads 32-bit buffer from SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to read start address
-  * @param  pDstBuffer Pointer to destination buffer
-  * @param  BufferSize Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
-                                    uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint32_t *psramaddress = pAddress;
-  uint32_t *pdestbuff = pDstBuffer;
-  HAL_SRAM_StateTypeDef state = hsram->State;
-
-  /* Check the SRAM controller state */
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Read data from memory */
-    for (size = BufferSize; size != 0U; size--)
-    {
-      *pdestbuff = *psramaddress;
-      pdestbuff++;
-      psramaddress++;
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = state;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Writes 32-bit buffer to SRAM memory.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to write start address
-  * @param  pSrcBuffer Pointer to source buffer to write
-  * @param  BufferSize Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
-                                     uint32_t BufferSize)
-{
-  uint32_t size;
-  __IO uint32_t *psramaddress = pAddress;
-  uint32_t *psrcbuff = pSrcBuffer;
-
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Write data to memory */
-    for (size = BufferSize; size != 0U; size--)
-    {
-      *psramaddress = *psrcbuff;
-      psrcbuff++;
-      psramaddress++;
-    }
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to read start address
-  * @param  pDstBuffer Pointer to destination buffer
-  * @param  BufferSize Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
-                                    uint32_t BufferSize)
-{
-  HAL_StatusTypeDef status;
-  HAL_SRAM_StateTypeDef state = hsram->State;
-
-  /* Check the SRAM controller state */
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Configure DMA user callbacks */
-    if (state == HAL_SRAM_STATE_READY)
-    {
-      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
-    }
-    else
-    {
-      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
-    }
-    hsram->hdma->XferErrorCallback = SRAM_DMAError;
-
-    /* Enable the DMA Stream */
-    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress Pointer to write start address
-  * @param  pSrcBuffer Pointer to source buffer to write
-  * @param  BufferSize Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
-                                     uint32_t BufferSize)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Configure DMA user callbacks */
-    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
-    hsram->hdma->XferErrorCallback = SRAM_DMAError;
-
-    /* Enable the DMA Stream */
-    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-
-  return status;
-}
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User SRAM Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hsram : SRAM handle
-  * @param CallbackId : ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
-  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
-  * @param pCallback : pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
-                                            pSRAM_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_SRAM_StateTypeDef state;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hsram);
-
-  state = hsram->State;
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    switch (CallbackId)
-    {
-      case HAL_SRAM_MSP_INIT_CB_ID :
-        hsram->MspInitCallback = pCallback;
-        break;
-      case HAL_SRAM_MSP_DEINIT_CB_ID :
-        hsram->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
-  return status;
-}
-
-/**
-  * @brief  Unregister a User SRAM Callback
-  *         SRAM Callback is redirected to the weak (surcharged) predefined callback
-  * @param hsram : SRAM handle
-  * @param CallbackId : ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
-  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
-  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
-  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_SRAM_StateTypeDef state;
-
-  /* Process locked */
-  __HAL_LOCK(hsram);
-
-  state = hsram->State;
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    switch (CallbackId)
-    {
-      case HAL_SRAM_MSP_INIT_CB_ID :
-        hsram->MspInitCallback = HAL_SRAM_MspInit;
-        break;
-      case HAL_SRAM_MSP_DEINIT_CB_ID :
-        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
-        break;
-      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
-        hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
-        break;
-      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
-        hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (state == HAL_SRAM_STATE_RESET)
-  {
-    switch (CallbackId)
-    {
-      case HAL_SRAM_MSP_INIT_CB_ID :
-        hsram->MspInitCallback = HAL_SRAM_MspInit;
-        break;
-      case HAL_SRAM_MSP_DEINIT_CB_ID :
-        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
-  return status;
-}
-
-/**
-  * @brief  Register a User SRAM Callback for DMA transfers
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hsram : SRAM handle
-  * @param CallbackId : ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
-  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
-  * @param pCallback : pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
-                                               pSRAM_DmaCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_SRAM_StateTypeDef state;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(hsram);
-
-  state = hsram->State;
-  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
-  {
-    switch (CallbackId)
-    {
-      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
-        hsram->DmaXferCpltCallback = pCallback;
-        break;
-      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
-        hsram->DmaXferErrorCallback = pCallback;
-        break;
-      default :
-        /* update return status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* update return status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
-  return status;
-}
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions
-  *  @brief   Control functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### SRAM Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the SRAM interface.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables dynamically SRAM write operation.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
-{
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_PROTECTED)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Enable write operation */
-    (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_READY;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables dynamically SRAM write operation.
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
-{
-  /* Check the SRAM controller state */
-  if (hsram->State == HAL_SRAM_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hsram);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_BUSY;
-
-    /* Disable write operation */
-    (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
-
-    /* Update the SRAM controller state */
-    hsram->State = HAL_SRAM_STATE_PROTECTED;
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hsram);
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
-  *  @brief   Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### SRAM State functions #####
-  ==============================================================================
-  [..]
-    This subsection permits to get in run-time the status of the SRAM controller
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the SRAM controller state
-  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL state
-  */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
-{
-  return hsram->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  DMA SRAM process complete callback.
-  * @param  hdma : DMA handle
-  * @retval None
-  */
-static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
-{
-  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
-
-  /* Disable the DMA channel */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  hsram->DmaXferCpltCallback(hdma);
-#else
-  HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SRAM process complete callback.
-  * @param  hdma : DMA handle
-  * @retval None
-  */
-static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
-{
-  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
-
-  /* Disable the DMA channel */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_PROTECTED;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  hsram->DmaXferCpltCallback(hdma);
-#else
-  HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA SRAM error callback.
-  * @param  hdma : DMA handle
-  * @retval None
-  */
-static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
-
-  /* Disable the DMA channel */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_ERROR;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  hsram->DmaXferErrorCallback(hdma);
-#else
-  HAL_SRAM_DMA_XferErrorCallback(hdma);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-#endif /* FSMC_BANK1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c
deleted file mode 100644
index 9d00316b1e3..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c
+++ /dev/null
@@ -1,7044 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim.c
-  * @author  MCD Application Team
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + TIM Time Base Initialization
-  *           + TIM Time Base Start
-  *           + TIM Time Base Start Interruption
-  *           + TIM Time Base Start DMA
-  *           + TIM Output Compare/PWM Initialization
-  *           + TIM Output Compare/PWM Channel Configuration
-  *           + TIM Output Compare/PWM  Start
-  *           + TIM Output Compare/PWM  Start Interruption
-  *           + TIM Output Compare/PWM Start DMA
-  *           + TIM Input Capture Initialization
-  *           + TIM Input Capture Channel Configuration
-  *           + TIM Input Capture Start
-  *           + TIM Input Capture Start Interruption
-  *           + TIM Input Capture Start DMA
-  *           + TIM One Pulse Initialization
-  *           + TIM One Pulse Channel Configuration
-  *           + TIM One Pulse Start
-  *           + TIM Encoder Interface Initialization
-  *           + TIM Encoder Interface Start
-  *           + TIM Encoder Interface Start Interruption
-  *           + TIM Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + TIM OCRef clear configuration
-  *           + TIM External Clock configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include:
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output
-       (#) Synchronization circuit to control the timer with external signals and to interconnect
-            several timers together.
-       (#) Supports incremental encoder for positioning purposes
-
-            ##### How to use this driver #####
-  ==============================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending on the selected feature:
-           (++) Time Base : HAL_TIM_Base_MspInit()
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-             __HAL_RCC_GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-       Initialization function of this driver:
-       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
-            Output Compare signal.
-       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
-            PWM signal.
-       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
-            external signal.
-       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
-            in One Pulse Mode.
-       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-
-    *** Callback registration ***
-  =============================================
-
-  [..]
-  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-
-  [..]
-  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
-  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
-  the Callback ID and a pointer to the user callback function.
-
-  [..]
-  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-
-  [..]
-  These functions allow to register/unregister following callbacks:
-    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
-    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
-    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
-    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
-    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
-    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
-    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
-    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
-    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
-    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
-    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
-    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
-    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
-    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
-    (+) TriggerCallback                   : TIM Trigger Callback.
-    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
-    (+) IC_CaptureCallback                : TIM Input Capture Callback.
-    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
-    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
-    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
-    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
-    (+) ErrorCallback                     : TIM Error Callback.
-
-  [..]
-By default, after the Init and when the state is HAL_TIM_STATE_RESET
-all interrupt callbacks are set to the corresponding weak functions:
-  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
-
-  [..]
-  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
-  functionalities in the Init / DeInit only when these callbacks are null
-  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
-    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
-
-  [..]
-    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
-    Exception done MspInit / MspDeInit that can be registered / unregistered
-    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
-    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
-
-  [..]
-      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registration feature is not available and all callbacks
-      are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
-  * @{
-  */
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
-static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
-                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
-/**
-  * @}
-  */
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
-  *  @brief    Time Base functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base.
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->Base_MspInitCallback == NULL)
-    {
-      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Base_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Base peripheral
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->Base_MspDeInitCallback == NULL)
-  {
-    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->Base_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim TIM Base handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Base MSP.
-  * @param  htim TIM Base handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Check the TIM state */
-  if (htim->State != HAL_TIM_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Check the TIM state */
-  if (htim->State != HAL_TIM_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Enable the TIM Update interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim TIM Base handle
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  if (htim->State == HAL_TIM_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->State == HAL_TIM_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the DMA Period elapsed callbacks */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-  /* Enable the DMA channel */
-  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
-                     Length) != HAL_OK)
-  {
-    /* Return error status */
-    return HAL_ERROR;
-  }
-
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
-  *  @brief    TIM Output Compare functions
-  *
-@verbatim
-  ==============================================================================
-                  ##### TIM Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare.
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the TIM Output Compare.
-    (+) Stop the TIM Output Compare.
-    (+) Start the TIM Output Compare and enable interrupt.
-    (+) Stop the TIM Output Compare and disable interrupt.
-    (+) Start the TIM Output Compare and enable DMA transfer.
-    (+) Stop the TIM Output Compare and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
-  * @param  htim TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->OC_MspInitCallback == NULL)
-    {
-      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->OC_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the Output Compare */
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->OC_MspDeInitCallback == NULL)
-  {
-    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->OC_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim TIM Output Compare handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim TIM Output Compare handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Set the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim TIM Output Compare handle
-  * @param  Channel TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
-  *  @brief    TIM PWM functions
-  *
-@verbatim
-  ==============================================================================
-                          ##### TIM PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM PWM.
-    (+) De-initialize the TIM PWM.
-    (+) Start the TIM PWM.
-    (+) Stop the TIM PWM.
-    (+) Start the TIM PWM and enable interrupt.
-    (+) Stop the TIM PWM and disable interrupt.
-    (+) Start the TIM PWM and enable DMA transfer.
-    (+) Stop the TIM PWM and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
-  * @param  htim TIM PWM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->PWM_MspInitCallback == NULL)
-    {
-      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->PWM_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM PWM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->PWM_MspDeInitCallback == NULL)
-  {
-    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->PWM_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim TIM PWM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim TIM PWM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim TIM handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The source Buffer address.
-  * @param  Length The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Set the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim TIM PWM handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
-  *  @brief    TIM Input Capture functions
-  *
-@verbatim
-  ==============================================================================
-              ##### TIM Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture.
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the TIM Input Capture.
-   (+) Stop the TIM Input Capture.
-   (+) Start the TIM Input Capture and enable interrupt.
-   (+) Stop the TIM Input Capture and disable interrupt.
-   (+) Start the TIM Input Capture and enable DMA transfer.
-   (+) Stop the TIM Input Capture and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
-  * @param  htim TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->IC_MspInitCallback == NULL)
-    {
-      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->IC_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the input capture */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->IC_MspDeInitCallback == NULL)
-  {
-    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->IC_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Change the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture MSP.
-  * @param  htim TIM Input Capture handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpsmcr;
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in DMA mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData The destination Buffer address.
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  uint32_t tmpsmcr;
-  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel state */
-  if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
-  {
-    if ((pData == NULL) && (Length > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-    {
-      __HAL_TIM_ENABLE(htim);
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in DMA mode.
-  * @param  htim TIM Input Capture handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
-  *  @brief    TIM One Pulse functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### TIM One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse.
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the TIM One Pulse.
-    (+) Stop the TIM One Pulse.
-    (+) Start the TIM One Pulse and enable interrupt.
-    (+) Stop the TIM One Pulse and disable interrupt.
-    (+) Start the TIM One Pulse and enable DMA transfer.
-    (+) Stop the TIM One Pulse and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
-  * @note   When the timer instance is initialized in One Pulse mode, timer
-  *         channels 1 and channel 2 are reserved and cannot be used for other
-  *         purpose.
-  * @param  htim TIM One Pulse handle
-  * @param  OnePulseMode Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->OnePulse_MspInitCallback == NULL)
-    {
-      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->OnePulse_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM One Pulse
-  * @param  htim TIM One Pulse handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->OnePulse_MspDeInitCallback == NULL)
-  {
-    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->OnePulse_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim TIM One Pulse handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim TIM One Pulse handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Check the TIM channels state */
-  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Check the TIM channels state */
-  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @note Though OutputChannel parameter is deprecated and ignored by the function
-  *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling
-  *       @ref HAL_TIM_OnePulse_ConfigChannel().
-  * @param  htim TIM One Pulse handle
-  * @param  OutputChannel See note above
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(OutputChannel);
-
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
-  *  @brief    TIM Encoder functions
-  *
-@verbatim
-  ==============================================================================
-                          ##### TIM Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder.
-    (+) De-initialize the TIM Encoder.
-    (+) Start the TIM Encoder.
-    (+) Stop the TIM Encoder.
-    (+) Start the TIM Encoder and enable interrupt.
-    (+) Stop the TIM Encoder and disable interrupt.
-    (+) Start the TIM Encoder and enable DMA transfer.
-    (+) Stop the TIM Encoder and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
-  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *         requires a timer reset to avoid unexpected direction
-  *         due to DIR bit readonly in center aligned mode.
-  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
-  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
-  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
-  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
-  * @note   When the timer instance is initialized in Encoder mode, timer
-  *         channels 1 and channel 2 are reserved and cannot be used for other
-  *         purpose.
-  * @param  htim TIM Encoder Interface handle
-  * @param  sConfig TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
-{
-  uint32_t tmpsmcr;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    TIM_ResetCallback(htim);
-
-    if (htim->Encoder_MspInitCallback == NULL)
-    {
-      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Encoder_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS and ECE bits */
-  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
-  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitializes the TIM Encoder interface
-  * @param  htim TIM Encoder Interface handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  if (htim->Encoder_MspDeInitCallback == NULL)
-  {
-    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  htim->Encoder_MspDeInitCallback(htim);
-#else
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim TIM Encoder Interface handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim TIM Encoder Interface handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-    }
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-  else
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-    }
-  }
-
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-    }
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1 The destination Buffer address for IC1.
-  * @param  pData2 The destination Buffer address for IC2.
-  * @param  Length The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
-                                            uint32_t *pData2, uint16_t Length)
-{
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
-    {
-      return HAL_BUSY;
-    }
-    else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
-    {
-      if ((pData1 == NULL) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
-    {
-      return HAL_BUSY;
-    }
-    else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
-    {
-      if ((pData2 == NULL) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
-        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
-    {
-      return HAL_BUSY;
-    }
-    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
-             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
-    {
-      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Input Capture DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-    }
-
-    case TIM_CHANNEL_ALL:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
-                         Length) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim TIM Encoder Interface handle
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if (Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel(s) state */
-  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
-  {
-    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
-  *  @brief    TIM IRQ handler management
-  *
-@verbatim
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================
-  [..]
-    This section provides Timer IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim TIM  handle
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-        /* Input capture event */
-        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->IC_CaptureCallback(htim);
-#else
-          HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-        }
-        /* Output compare event */
-        else
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->OC_DelayElapsedCallback(htim);
-          htim->PWM_PulseFinishedCallback(htim);
-#else
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      /* Output compare event */
-      else
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->PeriodElapsedCallback(htim);
-#else
-      HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM Trigger detection event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->TriggerCallback(htim);
-#else
-      HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
-  *  @brief    TIM Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-      (+) Configure External Clock source.
-      (+) Configure Master and the Slave synchronization.
-      (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim TIM Output Compare handle
-  * @param  sConfig TIM Output Compare configuration structure
-  * @param  Channel TIM Channels to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
-                                           TIM_OC_InitTypeDef *sConfig,
-                                           uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the TIM Channel 4 in Output Compare */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim TIM IC handle
-  * @param  sConfig TIM Input Capture configuration structure
-  * @param  Channel TIM Channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-    TIM_TI2_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-    TIM_TI3_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-    TIM_TI4_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim TIM PWM handle
-  * @param  sConfig TIM PWM configuration structure
-  * @param  Channel TIM Channels to be configured
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            TIM_OC_InitTypeDef *sConfig,
-                                            uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-      break;
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim TIM One Pulse handle
-  * @param  sConfig TIM One Pulse configuration structure
-  * @param  OutputChannel TIM output channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel TIM input Channel to configure
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @note  To output a waveform with a minimum delay user can enable the fast
-  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
-  *        output is forced in response to the edge detection on TIx input,
-  *        without taking in account the comparison.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
-                                                 uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  TIM_OC_InitTypeDef temp1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if (OutputChannel != InputChannel)
-  {
-    /* Process Locked */
-    __HAL_LOCK(htim);
-
-    htim->State = HAL_TIM_STATE_BUSY;
-
-    /* Extract the Output compare configuration from sConfig structure */
-    temp1.OCMode = sConfig->OCMode;
-    temp1.Pulse = sConfig->Pulse;
-    temp1.OCPolarity = sConfig->OCPolarity;
-
-    switch (OutputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-        TIM_OC1_SetConfig(htim->Instance, &temp1);
-        break;
-      }
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_OC2_SetConfig(htim->Instance, &temp1);
-        break;
-      }
-      default:
-        break;
-    }
-
-    switch (InputChannel)
-    {
-      case TIM_CHANNEL_1:
-      {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                          sConfig->ICSelection, sConfig->ICFilter);
-
-        /* Reset the IC1PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-        break;
-      }
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                          sConfig->ICSelection, sConfig->ICFilter);
-
-        /* Reset the IC2PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-        break;
-      }
-
-      default:
-        break;
-    }
-
-    htim->State = HAL_TIM_STATE_READY;
-
-    __HAL_UNLOCK(htim);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
-{
-  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                          ((BurstLength) >> 8U) + 1U);
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @param  DataLength Data length. This parameter can be one value
-  *         between 1 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
-                                                   uint32_t  BurstLength,  uint32_t  DataLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
-  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
-  {
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callbacks */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA compare callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA trigger callbacks */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    default:
-      break;
-  }
-
-  /* Configure the DMA Burst Mode */
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode
-  * @param  htim TIM handle
-  * @param  BurstRequestSrc TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
-      break;
-    }
-    default:
-      break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                         ((BurstLength) >> 8U) + 1U);
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim TIM handle
-  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMABASE_CR1
-  *            @arg TIM_DMABASE_CR2
-  *            @arg TIM_DMABASE_SMCR
-  *            @arg TIM_DMABASE_DIER
-  *            @arg TIM_DMABASE_SR
-  *            @arg TIM_DMABASE_EGR
-  *            @arg TIM_DMABASE_CCMR1
-  *            @arg TIM_DMABASE_CCMR2
-  *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT
-  *            @arg TIM_DMABASE_PSC
-  *            @arg TIM_DMABASE_ARR
-  *            @arg TIM_DMABASE_CCR1
-  *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3
-  *            @arg TIM_DMABASE_CCR4
-  *            @arg TIM_DMABASE_OR
-  * @param  BurstRequestSrc TIM DMA Request sources
-  *         This parameter can be one of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer The Buffer address.
-  * @param  BurstLength DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
-  * @param  DataLength Data length. This parameter can be one value
-  *         between 1 and 0xFFFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
-                                                  uint32_t  BurstLength, uint32_t  DataLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
-
-  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
-  {
-    if ((BurstBuffer == NULL) && (BurstLength > 0U))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callbacks */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA capture callbacks */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA trigger callbacks */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
-      {
-        /* Return error status */
-        return HAL_ERROR;
-      }
-      break;
-    }
-    default:
-      break;
-  }
-
-  /* Configure the DMA Burst Mode */
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA burst reading
-  * @param  htim TIM handle
-  * @param  BurstRequestSrc TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch (BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
-      break;
-    }
-    case TIM_DMA_CC1:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-      break;
-    }
-    case TIM_DMA_CC2:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
-      break;
-    }
-    case TIM_DMA_CC3:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
-      break;
-    }
-    case TIM_DMA_CC4:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
-      break;
-    }
-    case TIM_DMA_TRIGGER:
-    {
-      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
-      break;
-    }
-    default:
-      break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim TIM handle
-  * @param  EventSource specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
-  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
-  * @note   Basic timers can only generate an update event.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim TIM handle
-  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
-                                           uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (sClearInputConfig->ClearInputSource)
-  {
-    case TIM_CLEARINPUTSOURCE_NONE:
-    {
-      /* Clear the OCREF clear selection bit and the the ETR Bits */
-      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
-      break;
-    }
-    case TIM_CLEARINPUTSOURCE_OCREFCLR:
-    {
-      /* Clear the OCREF clear selection bit */
-      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-    }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_ETR:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
-      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
-      {
-        htim->State = HAL_TIM_STATE_READY;
-        __HAL_UNLOCK(htim);
-        return HAL_ERROR;
-      }
-
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClearInputConfig->ClearInputPrescaler,
-                        sClearInputConfig->ClearInputPolarity,
-                        sClearInputConfig->ClearInputFilter);
-
-      /* Set the OCREF clear selection bit */
-      SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 1 */
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 1 */
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 2 */
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 2 */
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_3:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 3 */
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 3 */
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_4:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 4 */
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 4 */
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-      }
-      break;
-    }
-    default:
-      break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim TIM handle
-  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
-  uint32_t tmpsmcr;
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-
-  switch (sClockSourceConfig->ClockSource)
-  {
-    case TIM_CLOCKSOURCE_INTERNAL:
-    {
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr = htim->Instance->SMCR;
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
-      /* Check ETR input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI1:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI2:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI2 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_TI1ED:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-      break;
-    }
-
-    case TIM_CLOCKSOURCE_ITR0:
-    case TIM_CLOCKSOURCE_ITR1:
-    case TIM_CLOCKSOURCE_ITR2:
-    case TIM_CLOCKSOURCE_ITR3:
-      {
-        /* Check whether or not the timer instance supports internal trigger input */
-        assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
-        break;
-      }
-
-    default:
-      break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim TIM handle.
-  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim TIM handle.
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the Slave mode
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-    __HAL_UNLOCK(htim);
-    return HAL_ERROR;
-  }
-
-  /* Disable Trigger Interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim TIM handle.
-  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the Slave mode
-  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
-                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-    __HAL_UNLOCK(htim);
-    return HAL_ERROR;
-  }
-
-  /* Enable Trigger Interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
-  /* Disable Trigger DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim TIM handle.
-  * @param  Channel TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0U;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Return the capture 1 value */
-      tmpreg =  htim->Instance->CCR1;
-
-      break;
-    }
-    case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Return the capture 2 value */
-      tmpreg =   htim->Instance->CCR2;
-
-      break;
-    }
-
-    case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Return the capture 3 value */
-      tmpreg =   htim->Instance->CCR3;
-
-      break;
-    }
-
-    case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Return the capture 4 value */
-      tmpreg =   htim->Instance->CCR4;
-
-      break;
-    }
-
-    default:
-      break;
-  }
-
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
-  *  @brief    TIM Callbacks functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================
- [..]
-   This section provides TIM callback functions:
-   (+) TIM Period elapsed callback
-   (+) TIM Output Compare callback
-   (+) TIM Input capture callback
-   (+) TIM Trigger callback
-   (+) TIM Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Period elapsed half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Output Compare callback in non-blocking mode
-  * @param  htim TIM OC handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Input Capture callback in non-blocking mode
-  * @param  htim TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Input Capture half complete callback in non-blocking mode
-  * @param  htim TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection half complete callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
-  * @param htim tim handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
-  *          @param pCallback pointer to the callback function
-  *          @retval status
-  */
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
-                                           pTIM_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(htim);
-
-  if (htim->State == HAL_TIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback               = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback                 = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback                  = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback                = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback             = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback              = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback            = pCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
-        htim->PeriodElapsedCallback                = pCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
-        htim->PeriodElapsedHalfCpltCallback        = pCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_CB_ID :
-        htim->TriggerCallback                      = pCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_HALF_CB_ID :
-        htim->TriggerHalfCpltCallback              = pCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_CB_ID :
-        htim->IC_CaptureCallback                   = pCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
-        htim->IC_CaptureHalfCpltCallback           = pCallback;
-        break;
-
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
-        htim->OC_DelayElapsedCallback              = pCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
-        htim->PWM_PulseFinishedCallback            = pCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
-        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
-        break;
-
-      case HAL_TIM_ERROR_CB_ID :
-        htim->ErrorCallback                        = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback       = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback           = pCallback;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback         = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback          = pCallback;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback        = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback     = pCallback;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback   = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback      = pCallback;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback    = pCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister a TIM callback
-  *         TIM callback is redirected to the weak predefined callback
-  * @param htim tim handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
-  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
-  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
-  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
-  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
-  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
-  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
-  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
-  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
-  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
-  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
-  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
-  *          @retval status
-  */
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(htim);
-
-  if (htim->State == HAL_TIM_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        /* Legacy weak Base MspInit Callback */
-        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        /* Legacy weak Base Msp DeInit Callback */
-        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        /* Legacy weak IC Msp Init Callback */
-        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        /* Legacy weak IC Msp DeInit Callback */
-        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        /* Legacy weak OC Msp Init Callback */
-        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        /* Legacy weak OC Msp DeInit Callback */
-        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        /* Legacy weak PWM Msp Init Callback */
-        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        /* Legacy weak PWM Msp DeInit Callback */
-        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        /* Legacy weak One Pulse Msp Init Callback */
-        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        /* Legacy weak One Pulse Msp DeInit Callback */
-        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        /* Legacy weak Encoder Msp Init Callback */
-        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        /* Legacy weak Encoder Msp DeInit Callback */
-        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
-        /* Legacy weak Period Elapsed Callback */
-        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
-        break;
-
-      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
-        /* Legacy weak Period Elapsed half complete Callback */
-        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_CB_ID :
-        /* Legacy weak Trigger Callback */
-        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
-        break;
-
-      case HAL_TIM_TRIGGER_HALF_CB_ID :
-        /* Legacy weak Trigger half complete Callback */
-        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_CB_ID :
-        /* Legacy weak IC Capture Callback */
-        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
-        break;
-
-      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
-        /* Legacy weak IC Capture half complete Callback */
-        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
-        break;
-
-      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
-        /* Legacy weak OC Delay Elapsed Callback */
-        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
-        /* Legacy weak PWM Pulse Finished Callback */
-        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
-        break;
-
-      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
-        /* Legacy weak PWM Pulse Finished half complete Callback */
-        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
-        break;
-
-      case HAL_TIM_ERROR_CB_ID :
-        /* Legacy weak Error Callback */
-        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (htim->State == HAL_TIM_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_TIM_BASE_MSPINIT_CB_ID :
-        /* Legacy weak Base MspInit Callback */
-        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
-        break;
-
-      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        /* Legacy weak Base Msp DeInit Callback */
-        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
-        break;
-
-      case HAL_TIM_IC_MSPINIT_CB_ID :
-        /* Legacy weak IC Msp Init Callback */
-        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
-        break;
-
-      case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        /* Legacy weak IC Msp DeInit Callback */
-        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
-        break;
-
-      case HAL_TIM_OC_MSPINIT_CB_ID :
-        /* Legacy weak OC Msp Init Callback */
-        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
-        break;
-
-      case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        /* Legacy weak OC Msp DeInit Callback */
-        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
-        break;
-
-      case HAL_TIM_PWM_MSPINIT_CB_ID :
-        /* Legacy weak PWM Msp Init Callback */
-        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
-        break;
-
-      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        /* Legacy weak PWM Msp DeInit Callback */
-        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        /* Legacy weak One Pulse Msp Init Callback */
-        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
-        break;
-
-      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        /* Legacy weak One Pulse Msp DeInit Callback */
-        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        /* Legacy weak Encoder Msp Init Callback */
-        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
-        break;
-
-      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        /* Legacy weak Encoder Msp DeInit Callback */
-        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
-        break;
-
-      default :
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return status;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
-  *  @brief   TIM Peripheral State functions
-  *
-@verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base handle state.
-  * @param  htim TIM Base handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC handle state.
-  * @param  htim TIM Output Compare handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM handle state.
-  * @param  htim TIM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture handle state.
-  * @param  htim TIM IC handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode handle state.
-  * @param  htim TIM OPM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode handle state.
-  * @param  htim TIM Encoder Interface handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode handle state.
-  * @param  htim TIM handle
-  * @retval Active channel
-  */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
-{
-  return htim->Channel;
-}
-
-/**
-  * @brief  Return actual state of the TIM channel.
-  * @param  htim TIM handle
-  * @param  Channel TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  *            @arg TIM_CHANNEL_5: TIM Channel 5
-  *            @arg TIM_CHANNEL_6: TIM Channel 6
-  * @retval TIM Channel state
-  */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
-{
-  HAL_TIM_ChannelStateTypeDef channel_state;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
-  return channel_state;
-}
-
-/**
-  * @brief  Return actual state of a DMA burst operation.
-  * @param  htim TIM handle
-  * @retval DMA burst state
-  */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
-  return htim->DMABurstState;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-
-/**
-  * @brief  TIM DMA error callback
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-  }
-  else
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->ErrorCallback(htim);
-#else
-  HAL_TIM_ErrorCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PWM_PulseFinishedCallback(htim);
-#else
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PWM_PulseFinishedHalfCpltCallback(htim);
-#else
-  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Capture complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->IC_CaptureCallback(htim);
-#else
-  HAL_TIM_IC_CaptureCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Capture half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-  else
-  {
-    /* nothing to do */
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->IC_CaptureHalfCpltCallback(htim);
-#else
-  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PeriodElapsedCallback(htim);
-#else
-  HAL_TIM_PeriodElapsedCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Period Elapse half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->PeriodElapsedHalfCpltCallback(htim);
-#else
-  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Trigger callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
-  {
-    htim->State = HAL_TIM_STATE_READY;
-  }
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->TriggerCallback(htim);
-#else
-  HAL_TIM_TriggerCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  TIM DMA Trigger half complete callback.
-  * @param  hdma pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-  htim->TriggerHalfCpltCallback(htim);
-#else
-  HAL_TIM_TriggerHalfCpltCallback(htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx TIM peripheral
-  * @param  Structure TIM Base configuration structure
-  * @retval None
-  */
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1;
-  tmpcr1 = TIMx->CR1;
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  /* Set the auto-reload preload */
-  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
-
-  /* Set the Prescaler value */
-  TIMx->PSC = Structure->Prescaler;
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter (only for advanced timer) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Timer Output Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Timer Output Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12U);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Slave Timer configuration function
-  * @param  htim TIM handle
-  * @param  sSlaveConfig Slave timer configuration
-  * @retval None
-  */
-static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
-{
-  uint32_t tmpsmcr;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-    case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sSlaveConfig->TriggerPrescaler,
-                        sSlaveConfig->TriggerPolarity,
-                        sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
-      {
-        return HAL_ERROR;
-      }
-
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;
-
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;
-      break;
-    }
-
-    case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-      break;
-    }
-
-    case TIM_TS_ITR0:
-    case TIM_TS_ITR1:
-    case TIM_TS_ITR2:
-    case TIM_TS_ITR3:
-      {
-        /* Check the parameter */
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-        break;
-      }
-
-    default:
-      break;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
-  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  }
-  else
-  {
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4U);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
-  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8U);
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4U);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
-  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
-  *        protected against un-initialized filter and polarity values.
-  * @retval None
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                              uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8U);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  InputTriggerSource The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
-  uint32_t tmpsmcr;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the TS Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source and the slave mode*/
-  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
-  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
-  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
-  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
-  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
-  * @param  ExtTRGFilter External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
-                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
-  * @retval None
-  */
-static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */
-  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
-}
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
-  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval None
-  */
-void TIM_ResetCallback(TIM_HandleTypeDef *htim)
-{
-  /* Reset the TIM callback to the legacy weak callbacks */
-  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
-  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
-  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
-  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
-  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
-  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
-  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
-  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
-  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
-  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
-}
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c
deleted file mode 100644
index 5fb13e7c0ca..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer Extended peripheral:
-  *           + Time Master and Slave synchronization configuration
-  *           + Time OCRef clear configuration
-  *           + Timer remapping capabilities configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..]
-    The Timer Extended features include:
-    (#) Synchronization circuit to control the timer with external signals and to
-        interconnect several timers together.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx TIMEx
-  * @brief TIM Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
-  * @{
-  */
-/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  * @brief    Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-      (+) Configure Master synchronization.
-      (+) Configure timer remapping capabilities.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim TIM handle.
-  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave
-  *         mode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig)
-{
-  uint32_t tmpcr2;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  /* Change the handler state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the MMS Bits */
-  tmpcr2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
-
-  /* Update TIMx CR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    /* Reset the MSM Bit */
-    tmpsmcr &= ~TIM_SMCR_MSM;
-    /* Set master mode */
-    tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
-    /* Update TIMx SMCR */
-    htim->Instance->SMCR = tmpsmcr;
-  }
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIMx Remapping input capabilities.
-  * @param  htim TIM handle.
-  * @param  Remap specifies the TIM remapping source.
-  *
-  *         For TIM2, the parameter can have the following values:(see note)
-  *            @arg TIM_TIM2_ITR1_TIM10_OC:      TIM2 ITR1 input is connected to TIM10 OC
-  *            @arg TIM_TIM2_ITR1_TIM5_TGO:      TIM2 ITR1 input is connected to TIM5 TGO
-  *
-  *         For TIM3, the parameter can have the following values:(see note)
-  *            @arg TIM_TIM3_ITR2_TIM11_OC:      TIM3 ITR2 input is connected to TIM11 OC
-  *            @arg TIM_TIM3_ITR2_TIM5_TGO:      TIM3 ITR2 input is connected to TIM5 TGO
-  *
-  *         For TIM9, the parameter is a combination of 2 fields (field1 | field2):
-  *
-  *                   field1 can have the following values:(see note)
-  *            @arg TIM_TIM9_ITR1_TIM3_TGO:      TIM9 ITR1 input is connected to TIM3 TGO
-  *            @arg TIM_TIM9_ITR1_TS:            TIM9 ITR1 input is connected to touch sensing I/O
-  *
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM9_GPIO:               TIM9 Channel1 is connected to GPIO
-  *            @arg TIM_TIM9_LSE:                TIM9 Channel1 is connected to LSE internal clock
-  *            @arg TIM_TIM9_GPIO1:              TIM9 Channel1 is connected to GPIO
-  *            @arg TIM_TIM9_GPIO2:              TIM9 Channel1 is connected to GPIO
-  *
-  *         For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:(see note)
-  *            @arg TIM_TIM10_TI1RMP:            TIM10 Channel 1 depends on TI1_RMP
-  *            @arg TIM_TIM10_RI:                TIM10 Channel 1 is connected to RI
-  *
-  *                   field2 can have the following values:(see note)
-  *            @arg TIM_TIM10_ETR_LSE:           TIM10 ETR input is connected to LSE clock
-  *            @arg TIM_TIM10_ETR_TIM9_TGO:      TIM10 ETR input is connected to TIM9 TGO
-  *
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM10_GPIO:              TIM10 Channel1 is connected to GPIO
-  *            @arg TIM_TIM10_LSI:               TIM10 Channel1 is connected to LSI internal clock
-  *            @arg TIM_TIM10_LSE:               TIM10 Channel1 is connected to LSE internal clock
-  *            @arg TIM_TIM10_RTC:               TIM10 Channel1 is connected to RTC wakeup interrupt
-  *
-  *         For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *
-  *                   field1 can have the following values:(see note)
-  *            @arg TIM_TIM11_TI1RMP:            TIM11 Channel 1 depends on TI1_RMP
-  *            @arg TIM_TIM11_RI:                TIM11 Channel 1 is connected to RI
-  *
-  *                   field2 can have the following values:(see note)
-  *            @arg TIM_TIM11_ETR_LSE:           TIM11 ETR input is connected to LSE clock
-  *            @arg TIM_TIM11_ETR_TIM9_TGO:      TIM11 ETR input is connected to TIM9 TGO
-  *
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM11_GPIO:     TIM11 Channel1 is connected to GPIO
-  *            @arg TIM_TIM11_MSI:      TIM11 Channel1 is connected to MSI internal clock
-  *            @arg TIM_TIM11_HSE_RTC:  TIM11 Channel1 is connected to HSE_RTC clock
-  *            @arg TIM_TIM11_GPIO1:    TIM11 Channel1 is connected to GPIO
-  *
-  * @note   Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  __HAL_LOCK(htim);
-
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
-
-  /* Set the Timer remapping configuration */
-  WRITE_REG(htim->Instance->OR, Remap);
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_timebase_tim_template.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_timebase_tim_template.c
deleted file mode 100644
index 5a7406abbbd..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_timebase_tim_template.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_timebase_tim_template.c 
-  * @author  MCD Application Team
-  * @brief   HAL time base based on the hardware TIM Template.
-  *    
-  *          This file override the native HAL time base functions (defined as weak)
-  *          the TIM time base:
-  *           + Intializes the TIM peripheral to generate a Period elapsed Event each 1ms
-  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
-  * 
- @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    This file must be copied to the application folder and modified as follows:
-    (#) Rename it to 'stm32l1xx_hal_timebase_tim.c'
-    (#) Add this file and the TIM HAL driver files to your project and make sure
-       HAL_TIM_MODULE_ENABLED is defined in stm32l1xx_hal_conf.h 
-
-    [..]
-    (@) The application needs to ensure that the time base is always set to 1 millisecond
-       to have correct HAL operation.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL_TimeBase_TIM
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_HandleTypeDef        TimHandle;
-/* Private function prototypes -----------------------------------------------*/
-void TIM6_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  This function configures the TIM6 as a time base source. 
-  *         The time source is configured  to have 1ms time base with a dedicated 
-  *         Tick interrupt priority. 
-  * @note   This function is called  automatically at the beginning of program after
-  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
-  * @param  TickPriority Tick interrupt priority.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
-  RCC_ClkInitTypeDef    clkconfig;
-  uint32_t              uwTimclock, uwAPB1Prescaler = 0U;
-  uint32_t              uwPrescalerValue = 0U;
-  uint32_t              pFLatency;
-  HAL_StatusTypeDef     status = HAL_OK;
-
-  /* Enable TIM6 clock */
-  __HAL_RCC_TIM6_CLK_ENABLE();
-
-  /* Get clock configuration */
-  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
-  /* Get APB1 prescaler */
-  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
-
-  /* Compute TIM6 clock */
-  if (uwAPB1Prescaler == RCC_HCLK_DIV1) 
-  {
-    uwTimclock = HAL_RCC_GetPCLK1Freq();
-  }
-  else
-  {
-    uwTimclock = 2U * HAL_RCC_GetPCLK1Freq();
-  }
-
-  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
-  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
-
-  /* Initialize TIM6 */
-  TimHandle.Instance = TIM6;
-
-  /* Initialize TIMx peripheral as follow:
-  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
-  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
-  + ClockDivision = 0
-  + Counter direction = Up
-  */
-  TimHandle.Init.Period = (1000000U / 1000U) - 1U;
-  TimHandle.Init.Prescaler = uwPrescalerValue;
-  TimHandle.Init.ClockDivision = 0U;
-  TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
-  status = HAL_TIM_Base_Init(&TimHandle);
-  if (status == HAL_OK)
-  {
-    /* Start the TIM time Base generation in interrupt mode */
-    status = HAL_TIM_Base_Start_IT(&TimHandle);
-    if (status == HAL_OK)
-    {
-      /* Enable the TIM6 global Interrupt */
-      HAL_NVIC_EnableIRQ(TIM6_IRQn);
-
-      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-      {
-        /*Configure the TIM6 IRQ priority */
-        HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0);
-        uwTickPrio = TickPriority;
-      }
-      else
-      {
-        status = HAL_ERROR;
-      }
-    }
-  }
-  
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Suspend Tick increment.
-  * @note   Disable the tick increment by disabling TIM6 update interrupt.
-  * @param  None
-  * @retval None
-  */
-void HAL_SuspendTick(void)
-{
-  /* Disable TIM6 update interrupt */
-  __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
-  * @brief  Resume Tick increment.
-  * @note   Enable the tick increment by enabling TIM6 update interrupt.
-  * @param  None
-  * @retval None
-  */
-void HAL_ResumeTick(void)
-{
-  /* Enable TIM6 update interrupt */
-  __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
-  * @brief  Period elapsed callback in non blocking mode
-  * @note   This function is called  when TIM6 interrupt took place, inside
-  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
-  * a global variable "uwTick" used as application time base.
-  * @param  htim  TIM handle
-  * @retval None
-  */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  HAL_IncTick();
-}
-
-/**
-  * @brief  This function handles TIM interrupt request.
-  * @param  None
-  * @retval None
-  */
-void TIM6_IRQHandler(void)
-{
-  HAL_TIM_IRQHandler(&TimHandle);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c
deleted file mode 100644
index 4d0309c9bb1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c
+++ /dev/null
@@ -1,3718 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_uart.c
-  * @author  MCD Application Team
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-
-    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure the UART TX/RX pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required
-                  Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete
-                  interrupt on the DMA Tx/Rx channel.
-            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
-                  (used for last byte sending completion detection in DMA non circular mode)
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-
-    (#) For the UART Half duplex mode, initialize the UART registers by calling
-        the HAL_HalfDuplex_Init() API.
-
-    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-
-    (#) For the Multi-Processor mode, initialize the UART registers by calling
-        the HAL_MultiProcessor_Init() API.
-
-     [..]
-       (@) The specific UART interrupts (Transmission complete interrupt,
-            RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
-            and receive process.
-
-     [..]
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
-            HAL_UART_MspInit() API.
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
-    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-
-    [..]
-    For specific callback RxEventCallback, use dedicated registration/reset functions:
-    respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
-
-    [..]
-    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
-    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
-    or @ref HAL_UART_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-     [..]
-        Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
-
-    [..] This subsection also provides a set of additional functions providing enhanced reception
-    services to user. (For example, these functions allow application to handle use cases
-    where number of data to be received is unknown).
-
-    (#) Compared to standard reception services which only consider number of received
-        data elements as reception completion criteria, these functions also consider additional events
-        as triggers for updating reception status to caller :
-       (+) Detection of inactivity period (RX line has not been active for a given period).
-          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
-               for 1 frame time, after last received byte.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
-           or till IDLE event occurs. Reception is handled only during function execution.
-           When function exits, no data reception could occur. HAL status and number of actually received data elements,
-           are returned by function after finishing transfer.
-       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
-           These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
-           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
-
-    (#) Blocking mode API:
-        (+) HAL_UARTEx_ReceiveToIdle()
-
-    (#) Non-Blocking mode API with Interrupt:
-        (+) HAL_UARTEx_ReceiveToIdle_IT()
-
-    (#) Non-Blocking mode API with DMA:
-        (+) HAL_UARTEx_ReceiveToIdle_DMA()
-
-
-     *** UART HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in UART HAL driver.
-
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral
-      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
-      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
-      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
-      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-
-     [..]
-       (@) You can refer to the UART HAL driver header file for more useful macros
-
-  @endverbatim
-     [..]
-       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible UART frame formats are as listed in the following table:
-    +-------------------------------------------------------------+
-    |   M bit |  PCE bit  |            UART frame                 |
-    |---------------------|---------------------------------------|
-    |    0    |    0      |    | SB | 8 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|-----------|---------------------------------------|
-    |    1    |    0      |    | SB | 9 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    +-------------------------------------------------------------+
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup UART_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions  UART Private Functions
-  * @{
-  */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void UART_SetConfig(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible UART frame formats.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
-    procedures (details for the procedures are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the UART mode according to the specified parameters in
-  *         the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* The hardware flow control is available only for USART1, USART2 and USART3 */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  }
-  else
-  {
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In half-duplex mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the LIN mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  BreakDetectLength Specifies the LIN break detection length.
-  *         This parameter can be one of the following values:
-  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
-  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the LIN UART instance */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
-  /* Check the Break detection length parameter */
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In LIN mode, the following bits must be kept cleared:
-     - CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
-  /* Set the USART LIN Break detection length. */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
-  SET_BIT(huart->Instance->CR2, BreakDetectLength);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the Multi-Processor mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Address USART address
-  * @param  WakeUpMethod specifies the USART wake-up method.
-  *         This parameter can be one of the following values:
-  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
-  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));
-
-  /* Check the Address & wake up method parameters */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-  assert_param(IS_UART_ADDRESS(Address));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In Multi-Processor mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Set the USART address node */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
-  SET_BIT(huart->Instance->CR2, Address);
-
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
-  SET_BIT(huart->Instance->CR1, WakeUpMethod);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the UART peripheral.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  if (huart->MspDeInitCallback == NULL)
-  {
-    huart->MspDeInitCallback = HAL_UART_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  huart->MspDeInitCallback(huart);
-#else
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_RESET;
-  huart->RxState = HAL_UART_STATE_RESET;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  UART MSP Init.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART MSP DeInit.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User UART Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an UART Callback
-  *         UART callaback is redirected to the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (HAL_UART_STATE_READY == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
-        break;
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_UART_STATE_RESET == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Register a User UART Rx Event Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart     Uart handle
-  * @param  pCallback Pointer to the Rx Event Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = pCallback;
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister the UART Rx Event Callback
-  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
-  * @param  huart     Uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-  return status;
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
-  *  @brief UART Transmit and Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two modes of transfer:
-       (+) Blocking mode: The communication is performed in polling mode.
-           The HAL status of all data processing is returned by the same function
-           after finishing transfer.
-       (+) Non-Blocking mode: The communication is performed using Interrupts
-           or DMA, these API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
-
-    (#) Blocking mode API's are :
-        (+) HAL_UART_Transmit()
-        (+) HAL_UART_Receive()
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_UART_Transmit_IT()
-        (+) HAL_UART_Receive_IT()
-        (+) HAL_UART_IRQHandler()
-
-    (#) Non-Blocking mode API's with DMA are :
-        (+) HAL_UART_Transmit_DMA()
-        (+) HAL_UART_Receive_DMA()
-        (+) HAL_UART_DMAPause()
-        (+) HAL_UART_DMAResume()
-        (+) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
-        (+) HAL_UART_TxHalfCpltCallback()
-        (+) HAL_UART_TxCpltCallback()
-        (+) HAL_UART_RxHalfCpltCallback()
-        (+) HAL_UART_RxCpltCallback()
-        (+) HAL_UART_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_UART_Abort()
-        (+) HAL_UART_AbortTransmit()
-        (+) HAL_UART_AbortReceive()
-        (+) HAL_UART_Abort_IT()
-        (+) HAL_UART_AbortTransmit_IT()
-        (+) HAL_UART_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_UART_AbortCpltCallback()
-        (+) HAL_UART_AbortTransmitCpltCallback()
-        (+) HAL_UART_AbortReceiveCpltCallback()
-
-    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
-        (+) HAL_UARTEx_RxEventCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
-           If user wants to abort it, Abort services should be called by user.
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-
-    -@- In the Half duplex communication, it is forbidden to run the transmit
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    while (huart->TxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
-        pdata16bits++;
-      }
-      else
-      {
-        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
-        pdata8bits++;
-      }
-      huart->TxXferCount--;
-    }
-
-    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Check the remain data to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
-        pdata16bits++;
-      }
-      else
-      {
-        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-        {
-          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-        }
-        pdata8bits++;
-      }
-      huart->RxXferCount--;
-    }
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit data register empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    return(UART_Start_Receive_IT(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in DMA mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the UART transmit DMA channel */
-    tmp = (uint32_t *)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in DMA mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    return(UART_Start_Receive_DMA(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  uint32_t dmarequest = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    /* Disable the UART DMA Tx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the UART DMA Rx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART DMA Rx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  uint32_t dmarequest = 0x00U;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel */
-    if (huart->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmatx);
-    }
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel */
-    if (huart->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmarx);
-    }
-    UART_EndRxTransfer(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   HAL_OK is returned if reception is completed (expected number of data has been received)
-  *         or if reception is stopped after IDLE event (less than the expected number of data has been received)
-  *         In this case, RxLen output parameter indicates number of data available in reception buffer.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart   UART handle.
-  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
-  * @param RxLen   Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
-  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize  = Size;
-    huart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    /* Initialize output number of received elements */
-    *RxLen = 0U;
-
-    /* as long as data have to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      /* Check if IDLE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
-      {
-        /* Clear IDLE flag in ISR */
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-
-        /* If Set, but no data ever received, clear flag without exiting loop */
-        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
-        if (*RxLen > 0U)
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_OK;
-        }
-      }
-
-      /* Check if RXNE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
-      {
-        if (pdata8bits == NULL)
-        {
-          *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-          pdata16bits++;
-        }
-        else
-        {
-           if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-           {
-             *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-           }
-           else
-           {
-             *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-           }
-
-          pdata8bits++;
-        }
-        /* Increment number of received elements */
-        *RxLen += 1U;
-        huart->RxXferCount--;
-      }
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set number of received elements in output parameter : RxLen */
-    *RxLen = huart->RxXferSize - huart->RxXferCount;
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *         to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
-  *         number of received data elements.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_IT(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *         to DMA services, transferring automatically received data elements in user reception buffer and
-  *         calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
-  *         reception phase as ended. In all cases, callback execution will indicate number of received data elements.
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_DMA(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->RxState and huart->gState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  huart->TxXferCount = 0x00U;
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  huart->RxXferCount = 0x00U;
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
-  uint32_t AbortCplt = 0x01U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (huart->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-    {
-      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
-    }
-    else
-    {
-      huart->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (huart->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
-    }
-    else
-    {
-      huart->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at UART level */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* UART Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        huart->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* UART Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        huart->hdmarx->XferAbortCallback = NULL;
-        AbortCplt = 0x01U;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (AbortCplt == 0x01U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    huart->TxXferCount = 0x00U;
-    huart->RxXferCount = 0x00U;
-
-    /* Reset ErrorCode */
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-    /* Restore huart->gState and huart->RxState to Ready */
-    huart->gState  = HAL_UART_STATE_READY;
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    huart->AbortCpltCallback(huart);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
-        huart->hdmatx->XferAbortCallback(huart->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      huart->TxXferCount = 0x00U;
-
-      /* Restore huart->gState to Ready */
-      huart->gState = HAL_UART_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      huart->AbortTransmitCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    huart->TxXferCount = 0x00U;
-
-    /* Restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    huart->AbortTransmitCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
-        huart->hdmarx->XferAbortCallback(huart->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      huart->RxXferCount = 0x00U;
-
-      /* Restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      huart->AbortReceiveCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    huart->RxXferCount = 0x00U;
-
-    /* Restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    huart->AbortReceiveCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles UART interrupt request.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  uint32_t isrflags   = READ_REG(huart->Instance->SR);
-  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
-  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
-  uint32_t errorflags = 0x00U;
-  uint32_t dmarequest = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if (errorflags == RESET)
-  {
-    /* UART in mode Receiver -------------------------------------------------*/
-    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      UART_Receive_IT(huart);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* UART parity error interrupt occurred ----------------------------------*/
-    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_PE;
-    }
-
-    /* UART noise error interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_NE;
-    }
-
-    /* UART frame error interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_FE;
-    }
-
-    /* UART Over-Run interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    }
-
-    /* Call UART Error Call back function if need be --------------------------*/
-    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
-    {
-      /* UART in mode Receiver -----------------------------------------------*/
-      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        UART_Receive_IT(huart);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Blocking error : transfer is aborted
-           Set the UART state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        UART_EndRxTransfer(huart);
-
-        /* Disable the UART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the UART DMA Rx channel */
-          if (huart->hdmarx != NULL)
-          {
-            /* Set the UART DMA Abort callback :
-               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-            /*Call registered error callback*/
-            huart->ErrorCallback(huart);
-#else
-            /*Call legacy weak error callback*/
-            HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-          /*Call registered error callback*/
-          huart->ErrorCallback(huart);
-#else
-          /*Call legacy weak error callback*/
-          HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered error callback*/
-        huart->ErrorCallback(huart);
-#else
-        /*Call legacy weak error callback*/
-        HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-        huart->ErrorCode = HAL_UART_ERROR_NONE;
-      }
-    }
-    return;
-  } /* End if some error occurs */
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : */
-  if (  (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      &&((isrflags & USART_SR_IDLE) != 0U)
-      &&((cr1its & USART_SR_IDLE) != 0U))
-  {
-    __HAL_UART_CLEAR_IDLEFLAG(huart);
-
-    /* Check if DMA mode is enabled in UART */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      /* DMA mode enabled */
-      /* Check received length : If all expected data are received, do nothing,
-         (DMA cplt callback will be called).
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
-      if (  (nb_remaining_rx_data > 0U)
-          &&(nb_remaining_rx_data < huart->RxXferSize))
-      {
-        /* Reception is not complete */
-        huart->RxXferCount = nb_remaining_rx_data;
-
-        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
-        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
-        {
-          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-             in the UART CR3 register */
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* At end of Rx process, restore huart->RxState to Ready */
-          huart->RxState = HAL_UART_STATE_READY;
-          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-          /* Last bytes received, so no need as the abort is immediate */
-          (void)HAL_DMA_Abort(huart->hdmarx);
-        }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif
-      }
-      return;
-    }
-    else
-    {
-      /* DMA mode not enabled */
-      /* Check received length : If all expected data are received, do nothing.
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
-      if (  (huart->RxXferCount > 0U)
-          &&(nb_rx_data > 0U) )
-      {
-        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        /* Rx process is completed, restore huart->RxState to Ready */
-        huart->RxState = HAL_UART_STATE_READY;
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxEventCallback(huart, nb_rx_data);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif
-      }
-      return;
-    }
-  }
-
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    UART_Transmit_IT(huart);
-    return;
-  }
-
-  /* UART in mode Transmitter end --------------------------------------------*/
-  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART error callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Receive Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
-  * @param  huart UART handle
-  * @param  Size  Number of data available in application reception buffer (indicates a position in
-  *               reception buffer until which, data are available)
-  * @retval None
-  */
-__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  UNUSED(Size);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the UART:
-    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
-    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
-    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
-    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
-    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits break characters.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Send break characters */
-  SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters the UART in mute mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Exits the UART mute mode: wake up software.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_TE;
-
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_RE;
-
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   UART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   UART communication process, return Peripheral Errors occurred during communication
-   process
-   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the UART state.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  uint32_t temp1 = 0x00U, temp2 = 0x00U;
-  temp1 = huart->gState;
-  temp2 = huart->RxState;
-
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the UART error code
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART.
-  * @retval UART Error Code
-  */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  huart UART handle.
-  * @retval none
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
-{
-  /* Init the UART Callback settings */
-  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
-
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @brief  DMA UART transmit process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode*/
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    huart->TxXferCount = 0x00U;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-  }
-  /* DMA Circular mode */
-  else
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Tx complete callback*/
-    huart->TxCpltCallback(huart);
-#else
-    /*Call legacy weak Tx complete callback*/
-    HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx complete callback*/
-  huart->TxHalfCpltCallback(huart);
-#else
-  /*Call legacy weak Tx complete callback*/
-  HAL_UART_TxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART receive process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode*/
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    huart->RxXferCount = 0U;
-
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
-       in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
-    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-    {
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-    }
-  }
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {  
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx complete callback*/
-    huart->RxCpltCallback(huart);
-#else
-    /*Call legacy weak Rx complete callback*/
-    HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART receive process half complete callback
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize/2U);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Half Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Half complete callback*/
-    huart->RxHalfCpltCallback(huart);
-#else
-    /*Call legacy weak Rx Half complete callback*/
-    HAL_UART_RxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  DMA UART communication error callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    huart->TxXferCount = 0x00U;
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    huart->RxXferCount = 0x00U;
-    UART_EndRxTransfer(huart);
-  }
-
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  This function handles UART Communication Timeout.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Flag specifies the UART flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        huart->gState  = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(huart);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in interrupt mode.
-  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  huart->pRxBuffPtr = pData;
-  huart->RxXferSize = Size;
-  huart->RxXferCount = Size;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  /* Enable the UART Parity Error Interrupt */
-  __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
-  /* Enable the UART Data Register not empty Interrupt */
-  __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in DMA mode.
-  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  huart->pRxBuffPtr = pData;
-  huart->RxXferSize = Size;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  /* Set the UART DMA transfer complete callback */
-  huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-  /* Set the UART DMA Half transfer complete callback */
-  huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-  /* Set the DMA error callback */
-  huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-  /* Set the DMA abort callback */
-  huart->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the DMA stream */
-  tmp = (uint32_t *)&pData;
-  HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
-
-  /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
-  __HAL_UART_CLEAR_OREFLAG(huart);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  /* Enable the UART Parity Error Interrupt */
-  SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-  in the UART CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-}
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-  }
-
-  /* At end of Rx process, restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-}
-
-/**
-  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  huart->RxXferCount = 0x00U;
-  huart->TxXferCount = 0x00U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmarx != NULL)
-  {
-    if (huart->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmatx != NULL)
-  {
-    if (huart->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->TxXferCount = 0x00U;
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  huart->AbortTransmitCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->RxXferCount = 0x00U;
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  huart->AbortReceiveCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t *tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      tmp = (uint16_t *) huart->pTxBuffPtr;
-      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      huart->pTxBuffPtr += 2U;
-    }
-    else
-    {
-      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
-    }
-
-    if (--huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Complete Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */
-  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
-  /* Tx process is ended, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx complete callback*/
-  huart->TxCpltCallback(huart);
-#else
-  /*Call legacy weak Tx complete callback*/
-  HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-
-  /* Check that a Rx process is ongoing */
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) huart->pRxBuffPtr;
-      *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-      huart->pRxBuffPtr += 2U;
-    }
-    else
-    {
-      pdata8bits = (uint8_t *) huart->pRxBuffPtr;
-      pdata16bits  = NULL;
-
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-      {
-        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-      }
-      huart->pRxBuffPtr += 1U;
-    }
-
-    if (--huart->RxXferCount == 0U)
-    {
-      /* Disable the UART Data Register not empty Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
-      /* Disable the UART Parity Error Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      /* Check current reception Mode :
-         If Reception till IDLE event has been selected : */
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        /* Set reception type to Standard */
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        /* Disable IDLE interrupt */
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-        /* Check if IDLE flag is set */
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
-        {
-          /* Clear IDLE flag in ISR */
-          __HAL_UART_CLEAR_IDLEFLAG(huart);
-        }
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
-      }
-      else
-      {
-       /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)		  
-       /*Call registered Rx complete callback*/
-       huart->RxCpltCallback(huart);
-#else
-       /*Call legacy weak Rx complete callback*/
-       HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configures the UART peripheral.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits
-     according to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the UART Word Length, Parity and mode:
-     Set the M bits according to huart->Init.WordLength value
-     Set PCE and PS bits according to huart->Init.Parity value
-     Set TE and RE bits according to huart->Init.Mode value
-     Set OVER8 bit according to huart->Init.OverSampling value */
-
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
-  MODIFY_REG(huart->Instance->CR1,
-             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-             tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
-
-
-  if((huart->Instance == USART1))
-  {
-    pclk = HAL_RCC_GetPCLK2Freq();
-  }
-  else
-  {
-    pclk = HAL_RCC_GetPCLK1Freq();
-  }
-
-  /*-------------------------- USART BRR Configuration ---------------------*/
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
-  }
-  else
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c
deleted file mode 100644
index 15b945e3373..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_usart.c
+++ /dev/null
@@ -1,2800 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_usart.c
-  * @author  MCD Application Team
-  * @brief   USART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
-  *          Peripheral (USART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The USART HAL driver can be used as follows:
-
-    (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
-    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) USART pins configuration:
-             (+++) Enable the clock for the USART GPIOs.
-             (+++) Configure the USART pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
-             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
-             (+++) Configure the USARTx interrupt priority.
-             (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
-             HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
-             (+++) Declare a DMA handle structure for the Tx/Rx channel.
-             (+++) Enable the DMAx interface clock.
-             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-             (+++) Configure the DMA Tx/Rx channel.
-             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
-             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-             (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
-                   (used for last byte sending completion detection in DMA non circular mode)
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the husart Init structure.
-
-    (#) Initialize the USART registers by calling the HAL_USART_Init() API:
-        (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized HAL_USART_MspInit(&husart) API.
-
-        -@@- The specific USART interrupts (Transmission complete interrupt,
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-
-    (#) Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
-       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_USART_ErrorCallback
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
-       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
-       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
-       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_USART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
-       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
-       (+) Stop the DMA Transfer using HAL_USART_DMAStop()
-
-     *** USART HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in USART HAL driver.
-
-       (+) __HAL_USART_ENABLE: Enable the USART peripheral
-       (+) __HAL_USART_DISABLE: Disable the USART peripheral
-       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
-       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
-       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
-       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-
-     [..]
-       (@) You can refer to the USART HAL driver header file for more useful macros
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
-    Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) MspInitCallback           : USART MspInit.
-    (+) MspDeInitCallback         : USART MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) MspInitCallback           : USART MspInit.
-    (+) MspDeInitCallback         : USART MspDeInit.
-
-    [..]
-    By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
-    and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
-    or @ref HAL_USART_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-  @endverbatim
-     [..]
-       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible USART frame formats are as listed in the following table:
-    +-------------------------------------------------------------+
-    |   M bit |  PCE bit  |            USART frame                 |
-    |---------------------|---------------------------------------|
-    |    0    |    0      |    | SB | 8 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|-----------|---------------------------------------|
-    |    1    |    0      |    | SB | 9 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    +-------------------------------------------------------------+
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup USART USART
-  * @brief HAL USART Synchronous module driver
-  * @{
-  */
-#ifdef HAL_USART_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup USART_Private_Constants
-  * @{
-  */
-#define DUMMY_DATA           0xFFFFU
-#define USART_TIMEOUT_VALUE  22000U
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup USART_Private_Functions
-  * @{
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-static void USART_SetConfig(USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USART
-  in asynchronous and in synchronous modes.
-  (+) For the asynchronous mode only these parameters can be configured:
-      (++) Baud Rate
-      (++) Word Length
-      (++) Stop Bit
-      (++) Parity: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           please refer to Reference manual for possible USART frame formats.
-      (++) USART polarity
-      (++) USART phase
-      (++) USART LastBit
-      (++) Receiver/transmitter modes
-
-  [..]
-    The HAL_USART_Init() function follows the USART  synchronous configuration
-    procedures (details for the procedures are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the USART mode according to the specified
-  *         parameters in the USART_InitTypeDef and initialize the associated handle.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
-  /* Check the USART handle allocation */
-  if (husart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  if (husart->State == HAL_USART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    husart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    USART_InitCallbacksToDefault(husart);
-
-    if (husart->MspInitCallback == NULL)
-    {
-      husart->MspInitCallback = HAL_USART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    husart->MspInitCallback(husart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_USART_MspInit(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-
-  husart->State = HAL_USART_STATE_BUSY;
-
-  /* Set the USART Communication parameters */
-  USART_SetConfig(husart);
-
-  /* In USART mode, the following bits must be kept cleared:
-     - LINEN bit in the USART_CR2 register
-     - HDSEL, SCEN and IREN bits in the USART_CR3 register */
-  CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
-  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Enable the Peripheral */
-  __HAL_USART_ENABLE(husart);
-
-  /* Initialize the USART state */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State = HAL_USART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the USART peripheral.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
-  /* Check the USART handle allocation */
-  if (husart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  husart->State = HAL_USART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_USART_DISABLE(husart);
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  if (husart->MspDeInitCallback == NULL)
-  {
-    husart->MspDeInitCallback = HAL_USART_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  husart->MspDeInitCallback(husart);
-#else
-  /* DeInit the low level hardware */
-  HAL_USART_MspDeInit(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State = HAL_USART_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USART MSP Init.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USART MSP DeInit.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User USART Callback
-  *         To be used instead of the weak predefined callback
-  * @param  husart usart handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-+  */
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(husart);
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
-        husart->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_TX_COMPLETE_CB_ID :
-        husart->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
-        husart->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_RX_COMPLETE_CB_ID :
-        husart->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_TX_RX_COMPLETE_CB_ID :
-        husart->TxRxCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_ERROR_CB_ID :
-        husart->ErrorCallback = pCallback;
-        break;
-
-      case HAL_USART_ABORT_COMPLETE_CB_ID :
-        husart->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (husart->State == HAL_USART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an USART Callback
-  *         USART callaback is redirected to the weak predefined callback
-  * @param  husart usart handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(husart);
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
-        husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
-        break;
-
-      case HAL_USART_TX_COMPLETE_CB_ID :
-        husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
-        break;
-
-      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
-        husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
-        break;
-
-      case HAL_USART_RX_COMPLETE_CB_ID :
-        husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
-        break;
-
-      case HAL_USART_TX_RX_COMPLETE_CB_ID :
-        husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback            */
-        break;
-
-      case HAL_USART_ERROR_CB_ID :
-        husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
-        break;
-
-      case HAL_USART_ABORT_COMPLETE_CB_ID :
-        husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
-        break;
-
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback           */
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (husart->State == HAL_USART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_USART_MSPINIT_CB_ID :
-        husart->MspInitCallback = HAL_USART_MspInit;
-        break;
-
-      case HAL_USART_MSPDEINIT_CB_ID :
-        husart->MspDeInitCallback = HAL_USART_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return status;
-}
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
-  *  @brief   USART Transmit and Receive functions
-  *
-@verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the USART synchronous
-    data transfers.
-
-  [..]
-    The USART supports master mode only: it cannot receive or send data related to an input
-    clock (SCLK is always an output).
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode.
-             The HAL status of all data processing is returned by the same function
-             after finishing transfer.
-        (++) No-Blocking mode: The communication is performed using Interrupts
-             or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
-             using DMA mode.
-             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
-              user callbacks
-             will be executed respectively at the end of the transmit or Receive process
-             The HAL_USART_ErrorCallback() user callback will be executed when a communication
-             error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_USART_Transmit() in simplex mode
-        (++) HAL_USART_Receive() in full duplex receive only
-        (++) HAL_USART_TransmitReceive() in full duplex mode
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_USART_Transmit_IT()in simplex mode
-        (++) HAL_USART_Receive_IT() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
-        (++) HAL_USART_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_USART_Transmit_DMA()in simplex mode
-        (++) HAL_USART_Receive_DMA() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
-        (++) HAL_USART_DMAPause()
-        (++) HAL_USART_DMAResume()
-        (++) HAL_USART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_USART_TxHalfCpltCallback()
-        (++) HAL_USART_TxCpltCallback()
-        (++) HAL_USART_RxHalfCpltCallback()
-        (++) HAL_USART_RxCpltCallback()
-        (++) HAL_USART_ErrorCallback()
-        (++) HAL_USART_TxRxCpltCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (++) HAL_USART_Abort()
-        (++) HAL_USART_Abort_IT()
-
-    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
-        (++) HAL_USART_AbortCpltCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-             and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
-             If user wants to abort it, Abort services should be called by user.
-        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-             Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Simplex Send an amount of data in blocking mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be sent.
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
-    }
-    else
-    {
-      ptxdata8bits  = pTxData;
-      ptxdata16bits = NULL;
-    }
-
-    while (husart->TxXferCount > 0U)
-    {
-      /* Wait for TXE flag in order to write data in DR */
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (ptxdata8bits == NULL)
-      {
-        husart->Instance->DR = (uint16_t)(*ptxdata16bits & (uint16_t)0x01FF);
-        ptxdata16bits++;
-      }
-      else
-      {
-        husart->Instance->DR = (uint8_t)(*ptxdata8bits & (uint8_t)0xFF);
-        ptxdata8bits++;
-      }
-
-      husart->TxXferCount--;
-    }
-
-    if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in blocking mode.
-  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be received.
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *prxdata8bits;
-  uint16_t *prxdata16bits;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      prxdata8bits  = NULL;
-      prxdata16bits = (uint16_t *) pRxData;
-    }
-    else
-    {
-      prxdata8bits  = pRxData;
-      prxdata16bits = NULL;
-    }
-
-    /* Check the remain data to be received */
-    while (husart->RxXferCount > 0U)
-    {
-      /* Wait until TXE flag is set to send dummy byte in order to generate the
-      * clock for the slave to send data.
-      * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
-      * can be written for all the cases. */
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x0FF);
-
-      /* Wait until RXNE flag is set to receive the byte */
-      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      if (prxdata8bits == NULL)
-      {
-        *prxdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-        prxdata16bits++;
-      }
-      else
-      {
-        if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE)))
-        {
-          *prxdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x0FF);
-        }
-        else
-        {
-          *prxdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x07F);
-        }
-        prxdata8bits++;
-      }
-      husart->RxXferCount--;
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send and Receive an amount of data in full-duplex mode (blocking mode).
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be sent (same amount to be received).
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *prxdata8bits;
-  uint16_t *prxdata16bits;
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
-  uint16_t rxdatacount;
-  uint32_t tickstart;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
-       handled through a u16 cast. */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
-      {
-        return  HAL_ERROR;
-      }
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    husart->RxXferSize = Size;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-    husart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      prxdata8bits  = NULL;
-      ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
-      prxdata16bits = (uint16_t *) pRxData;
-    }
-    else
-    {
-      prxdata8bits  = pRxData;
-      ptxdata8bits  = pTxData;
-      ptxdata16bits = NULL;
-      prxdata16bits = NULL;
-    }
-
-    /* Check the remain data to be received */
-    /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
-    rxdatacount = husart->RxXferCount;
-    while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
-    {
-      if (husart->TxXferCount > 0U)
-      {
-        /* Wait for TXE flag in order to write data in DR */
-        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        if (ptxdata8bits == NULL)
-        {
-          husart->Instance->DR = (uint16_t)(*ptxdata16bits & (uint16_t)0x01FF);
-          ptxdata16bits++;
-        }
-        else
-        {
-          husart->Instance->DR = (uint8_t)(*ptxdata8bits & (uint8_t)0xFF);
-          ptxdata8bits++; 
-        }
-
-        husart->TxXferCount--;
-      }
-
-      if (husart->RxXferCount > 0U)
-      {  
-        /* Wait for RXNE Flag */
-        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if (prxdata8bits == NULL)
-        {
-          *prxdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-          prxdata16bits++;
-        }
-        else
-        {
-          if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE)))
-          {
-            *prxdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x0FF);
-          }
-          else
-          {
-            *prxdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x07F);
-          }
-
-          prxdata8bits++;
-        }
-
-        husart->RxXferCount--;
-      }
-      rxdatacount = husart->RxXferCount;
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  * @note   The USART errors are not managed to avoid the overrun error.
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
-       are not managed by the USART transmit process to avoid the overrun interrupt
-       when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
-       to benefit for the frame error and noise interrupts the USART mode should be
-       configured only for transmit "USART_MODE_TX"
-       The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
-       Noise error interrupt */
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Transmit Data Register Empty Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode.
-  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Parity Error and Data Register not empty Interrupts */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Send dummy byte in order to generate the clock for the slave to send data */
-    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send and Receive an amount of data in full-duplex mode (non-blocking).
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be sent (same amount to be received).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
-{
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Data Register not empty Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
-    /* Enable the USART Parity Error Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the USART Transmit Data Register Empty Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Simplex Send an amount of data in DMA mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pTxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be sent.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* Set the USART DMA transfer complete callback */
-    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-    /* Set the DMA abort callback */
-    husart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the USART transmit DMA channel */
-    tmp = (uint32_t *)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in DMA mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pRxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pRxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Set the USART DMA Rx transfer complete callback */
-    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-    /* Set the USART DMA Rx transfer error callback */
-    husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-    /* Set the DMA abort callback */
-    husart->hdmarx->XferAbortCallback = NULL;
-
-    /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
-    is performed in DMA reception complete callback  */
-    husart->hdmatx->XferHalfCpltCallback = NULL;
-    husart->hdmatx->XferCpltCallback = NULL;
-
-    /* Set the DMA error callback */
-    husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-    /* Set the DMA AbortCpltCallback */
-    husart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the USART receive DMA channel */
-    tmp = (uint32_t *)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
-
-    /* Enable the USART transmit DMA channel: the transmit channel is used in order
-       to generate in the non-blocking mode the clock to the slave device,
-       this mode isn't a simplex receive mode but a full-duplex receive one */
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
-
-    /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Parity Error Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Transmit Receive an amount of data in DMA mode.
-  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
-  *         of u16 available through pTxData and through pRxData.
-  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
-  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
-  * @param  Size    Amount of data elements (u8 or u16) to be received/sent.
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_READY)
-  {
-    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    /* Set the USART DMA Rx transfer complete callback */
-    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-    /* Set the USART DMA Tx transfer complete callback */
-    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-    /* Set the USART DMA Tx transfer error callback */
-    husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-    /* Set the USART DMA Rx transfer error callback */
-    husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-    /* Set the DMA abort callback */
-    husart->hdmarx->XferAbortCallback = NULL;
-
-    /* Enable the USART receive DMA channel */
-    tmp = (uint32_t *)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
-
-    /* Enable the USART transmit DMA channel */
-    tmp = (uint32_t *)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-
-    /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Parity Error Interrupt */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
-  /* Process Locked */
-  __HAL_LOCK(husart);
-
-  /* Disable the USART DMA Tx request */
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
-  /* Process Locked */
-  __HAL_LOCK(husart);
-
-  /* Enable the USART DMA Tx request */
-  SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
-  uint32_t dmarequest = 0x00U;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
-     */
-
-  /* Stop USART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
-  if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
-  {
-    USART_EndTxTransfer(husart);
-
-    /* Abort the USART DMA Tx channel */
-    if (husart->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(husart->hdmatx);
-    }
-
-    /* Disable the USART Tx DMA request */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  /* Stop USART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
-  if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
-  {
-    USART_EndRxTransfer(husart);
-
-    /* Abort the USART DMA Rx channel */
-    if (husart->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(husart->hdmarx);
-    }
-
-    /* Disable the USART Rx DMA request */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfer (blocking mode).
-  * @param  husart USART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
-  *         as described by TransferType parameter) started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* Disable the USART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
-    if (husart->hdmatx != NULL)
-    {
-      /* Set the USART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      husart->hdmatx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(husart->hdmatx);
-    }
-  }
-
-  /* Disable the USART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
-    if (husart->hdmarx != NULL)
-    {
-      /* Set the USART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      husart->hdmarx->XferAbortCallback = NULL;
-
-      HAL_DMA_Abort(husart->hdmarx);
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  husart->TxXferCount = 0x00U;
-  husart->RxXferCount = 0x00U;
-
-  /* Restore husart->State to Ready */
-  husart->State  = HAL_USART_STATE_READY;
-
-  /* Reset Handle ErrorCode to No Error */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfer (Interrupt mode).
-  * @param  husart USART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
-  *         as described by TransferType parameter) started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable PPP Interrupts (depending of transfer direction)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
-{
-  uint32_t AbortCplt = 0x01U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (husart->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-    {
-      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
-    }
-    else
-    {
-      husart->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (husart->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-    {
-      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
-    }
-    else
-    {
-      husart->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the USART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at USART level */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
-    if (husart->hdmatx != NULL)
-    {
-      /* USART Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
-      {
-        husart->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* Disable the USART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-  {
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
-    if (husart->hdmarx != NULL)
-    {
-      /* USART Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
-      {
-        husart->hdmarx->XferAbortCallback = NULL;
-        AbortCplt = 0x01U;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (AbortCplt  == 0x01U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    husart->TxXferCount = 0x00U;
-    husart->RxXferCount = 0x00U;
-
-    /* Reset errorCode */
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-    /* Restore husart->State to Ready */
-    husart->State  = HAL_USART_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Complete Callback */
-    husart->AbortCpltCallback(husart);
-#else
-    /* Call legacy weak Abort Complete Callback */
-    HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles USART interrupt request.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
-  uint32_t isrflags = READ_REG(husart->Instance->SR);
-  uint32_t cr1its   = READ_REG(husart->Instance->CR1);
-  uint32_t cr3its   = READ_REG(husart->Instance->CR3);
-  uint32_t errorflags = 0x00U;
-  uint32_t dmarequest = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if (errorflags == RESET)
-  {
-    /* USART in mode Receiver -------------------------------------------------*/
-    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      if (husart->State == HAL_USART_STATE_BUSY_RX)
-      {
-        USART_Receive_IT(husart);
-      }
-      else
-      {
-        USART_TransmitReceive_IT(husart);
-      }
-      return;
-    }
-  }
-  /* If some errors occur */
-  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* USART parity error interrupt occurred ----------------------------------*/
-    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      husart->ErrorCode |= HAL_USART_ERROR_PE;
-    }
-
-    /* USART noise error interrupt occurred --------------------------------*/
-    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      husart->ErrorCode |= HAL_USART_ERROR_NE;
-    }
-
-    /* USART frame error interrupt occurred --------------------------------*/
-    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      husart->ErrorCode |= HAL_USART_ERROR_FE;
-    }
-
-    /* USART Over-Run interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      husart->ErrorCode |= HAL_USART_ERROR_ORE;
-    }
-
-    if (husart->ErrorCode != HAL_USART_ERROR_NONE)
-    {
-      /* USART in mode Receiver -----------------------------------------------*/
-      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        if (husart->State == HAL_USART_STATE_BUSY_RX)
-        {
-          USART_Receive_IT(husart);
-        }
-        else
-        {
-          USART_TransmitReceive_IT(husart);
-        }
-      }
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-      consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
-      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Set the USART state ready to be able to start again the process,
-        Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        USART_EndRxTransfer(husart);
-
-        /* Disable the USART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
-        {
-          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the USART DMA Rx channel */
-          if (husart->hdmarx != NULL)
-          {
-            /* Set the USART DMA Abort callback :
-            will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
-            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
-            if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              husart->hdmarx->XferAbortCallback(husart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-            /* Call registered Error Callback */
-            husart->ErrorCallback(husart);
-#else
-            /* Call legacy weak Error Callback */
-            HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-          /* Call registered Error Callback */
-          husart->ErrorCallback(husart);
-#else
-          /* Call legacy weak Error Callback */
-          HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Call user error callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-        /* Call registered Error Callback */
-        husart->ErrorCallback(husart);
-#else
-        /* Call legacy weak Error Callback */
-        HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-        husart->ErrorCode = HAL_USART_ERROR_NONE;
-      }
-    }
-    return;
-  }
-
-  /* USART in mode Transmitter -----------------------------------------------*/
-  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    if (husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      USART_Transmit_IT(husart);
-    }
-    else
-    {
-      USART_TransmitReceive_IT(husart);
-    }
-    return;
-  }
-
-  /* USART in mode Transmitter (transmission end) ----------------------------*/
-  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    USART_EndTransmit_IT(husart);
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_TxRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USART error callbacks.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_USART_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USART Abort Complete callback.
-  * @param  husart USART handle.
-  * @retval None
-  */
-__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(husart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_USART_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   USART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to return the State of
-    USART communication
-    process, return Peripheral Errors occurred during communication process
-     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
-         of the USART peripheral.
-     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
-         communication.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the USART state.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL state
-  */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
-  return husart->State;
-}
-
-/**
-  * @brief  Return the USART error code
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART.
-  * @retval USART Error Code
-  */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
-  return husart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
-
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  husart USART handle.
-  * @retval none
-  */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
-{
-  /* Init the USART Callback settings */
-  husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
-  husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-}
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
-  * @brief  DMA USART transmit process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    husart->TxXferCount = 0U;
-    if (husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      /* Disable the DMA transfer for transmit request by resetting the DMAT bit
-         in the USART CR3 register */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      /* Enable the USART Transmit Complete Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-    }
-  }
-  /* DMA Circular mode */
-  else
-  {
-    if (husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Complete Callback */
-      husart->TxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Complete Callback */
-      HAL_USART_TxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  DMA USART transmit process half complete callback
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx Half Complete Callback */
-  husart->TxHalfCpltCallback(husart);
-#else
-  /* Call legacy weak Tx Half Complete Callback */
-  HAL_USART_TxHalfCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART receive process complete callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode */
-  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  {
-    husart->RxXferCount = 0x00U;
-
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit
-         in the USART CR3 register */
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* The USART state is HAL_USART_STATE_BUSY_RX */
-    if (husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx Complete Callback */
-      husart->RxCpltCallback(husart);
-#else
-      /* Call legacy weak Rx Complete Callback */
-      HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
-    else
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Rx Complete Callback */
-      husart->TxRxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Rx Complete Callback */
-      HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    husart->State = HAL_USART_STATE_READY;
-  }
-  /* DMA circular mode */
-  else
-  {
-    if (husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx Complete Callback */
-      husart->RxCpltCallback(husart);
-#else
-      /* Call legacy weak Rx Complete Callback */
-      HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
-    else
-    {
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Rx Complete Callback */
-      husart->TxRxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Rx Complete Callback */
-      HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-/**
-  * @brief  DMA USART receive process half complete callback
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Rx Half Complete Callback */
-  husart->RxHalfCpltCallback(husart);
-#else
-  /* Call legacy weak Rx Half Complete Callback */
-  HAL_USART_RxHalfCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART communication error callback.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  husart->RxXferCount = 0x00U;
-  husart->TxXferCount = 0x00U;
-
-  /* Stop USART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
-  if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
-  {
-    USART_EndTxTransfer(husart);
-  }
-
-  /* Stop USART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
-  if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
-  {
-    USART_EndRxTransfer(husart);
-  }
-
-  husart->ErrorCode |= HAL_USART_ERROR_DMA;
-  husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Error Callback */
-  husart->ErrorCallback(husart);
-#else
-  /* Call legacy weak Error Callback */
-  HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  This function handles USART Communication Timeout.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  Flag specifies the USART flag to check.
-  * @param  Status The new Flag status (SET or RESET).
-  * @param  Tickstart Tick start value.
-  * @param  Timeout Timeout duration.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        /* Disable the USART Transmit Complete Interrupt */
-        CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
-        /* Disable the USART RXNE Interrupt */
-        CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
-        /* Disable the USART Parity Error Interrupt */
-        CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-        /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-        husart->State = HAL_USART_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(husart);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
-  * @param  husart USART handle.
-  * @retval None
-  */
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore husart->State to Ready */
-  husart->State = HAL_USART_STATE_READY;
-}
-
-/**
-  * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
-  * @param  husart USART handle.
-  * @retval None
-  */
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
-{
-  /* Disable RXNE, PE and ERR interrupts */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  /* At end of Rx process, restore husart->State to Ready */
-  husart->State = HAL_USART_STATE_READY;
-}
-
-/**
-  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  husart->RxXferCount = 0x00U;
-  husart->TxXferCount = 0x00U;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Error Callback */
-  husart->ErrorCallback(husart);
-#else
-  /* Call legacy weak Error Callback */
-  HAL_USART_ErrorCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  husart->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (husart->hdmarx != NULL)
-  {
-    if (husart->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  husart->TxXferCount = 0x00U;
-  husart->RxXferCount = 0x00U;
-
-  /* Reset errorCode */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  /* Restore husart->State to Ready */
-  husart->State  = HAL_USART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Complete Callback */
-  husart->AbortCpltCallback(husart);
-#else
-  /* Call legacy weak Abort Complete Callback */
-  HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA USART Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma DMA handle.
-  * @retval None
-  */
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  husart->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (husart->hdmatx != NULL)
-  {
-    if (husart->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  husart->TxXferCount = 0x00U;
-  husart->RxXferCount = 0x00U;
-
-  /* Reset errorCode */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-
-  /* Restore husart->State to Ready */
-  husart->State  = HAL_USART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Complete Callback */
-  husart->AbortCpltCallback(husart);
-#else
-  /* Call legacy weak Abort Complete Callback */
-  HAL_USART_AbortCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  * @note   The USART errors are not managed to avoid the overrun error.
-  */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
-  uint16_t *tmp;
-
-  if (husart->State == HAL_USART_STATE_BUSY_TX)
-  {
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      tmp = (uint16_t *) husart->pTxBuffPtr;
-      husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      husart->pTxBuffPtr += 2U;
-    }
-    else
-    {
-      husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
-    }
-
-    if (--husart->TxXferCount == 0U)
-    {
-      /* Disable the USART Transmit data register empty Interrupt */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
-      /* Enable the USART Transmit Complete Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
-  /* Disable the USART Transmit Complete Interrupt */
-  CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
-
-  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-  husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  /* Call registered Tx Complete Callback */
-  husart->TxCpltCallback(husart);
-#else
-  /* Call legacy weak Tx Complete Callback */
-  HAL_USART_TxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-
-  if (husart->State == HAL_USART_STATE_BUSY_RX)
-  {
-    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) husart->pRxBuffPtr;
-      *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-      husart->pRxBuffPtr += 2U;
-    }
-    else
-    {
-      pdata8bits = (uint8_t *) husart->pRxBuffPtr;
-      pdata16bits  = NULL;
-
-      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE)))
-      {
-        *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-      }
-
-      husart->pRxBuffPtr += 1U;
-    }
-
-    husart->RxXferCount--;
-
-    if (husart->RxXferCount == 0U)
-    {
-      /* Disable the USART RXNE Interrupt */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
-      /* Disable the USART Parity Error Interrupt */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      husart->State = HAL_USART_STATE_READY;
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Rx Complete Callback */
-      husart->RxCpltCallback(husart);
-#else
-      /* Call legacy weak Rx Complete Callback */
-      HAL_USART_RxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-      return HAL_OK;
-    }
-    else
-    {
-      /* Send dummy byte in order to generate the clock for the slave to send the next data.
-      * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
-      * can be written for all the cases. */
-      husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x0FF);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-
-  if (husart->State == HAL_USART_STATE_BUSY_TX_RX)
-  {
-    if (husart->TxXferCount != 0x00U)
-    {
-      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
-      {
-        if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-        {
-          pdata8bits  = NULL;
-          pdata16bits = (uint16_t *) husart->pTxBuffPtr;
-          husart->Instance->DR = (uint16_t)(*pdata16bits & (uint16_t)0x01FF);
-          husart->pTxBuffPtr += 2U;
-        }
-        else
-        {
-          husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
-        }
-
-        husart->TxXferCount--;
-
-        /* Check the latest data transmitted */
-        if (husart->TxXferCount == 0U)
-        {
-          CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-        }
-      }
-    }
-
-    if (husart->RxXferCount != 0x00U)
-    {
-      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
-      {
-        if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
-        {
-           pdata8bits  = NULL;
-           pdata16bits = (uint16_t *) husart->pRxBuffPtr;
-           *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-           husart->pRxBuffPtr += 2U;
-        }
-        else
-        {
-          pdata8bits = (uint8_t *) husart->pRxBuffPtr;
-          pdata16bits  = NULL;
-          if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE)))
-          {
-            *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-          }
-          else
-          {
-            *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-          }
-          husart->pRxBuffPtr += 1U;
-        }
-
-        husart->RxXferCount--;
-      }
-    }
-
-    /* Check the latest data received */
-    if (husart->RxXferCount == 0U)
-    {
-      /* Disable the USART RXNE Interrupt */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
-      /* Disable the USART Parity Error Interrupt */
-      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
-      husart->State = HAL_USART_STATE_READY;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-      /* Call registered Tx Rx Complete Callback */
-      husart->TxRxCpltCallback(husart);
-#else
-      /* Call legacy weak Tx Rx Complete Callback */
-      HAL_USART_TxRxCpltCallback(husart);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-      return HAL_OK;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configures the USART peripheral.
-  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-static void USART_SetConfig(USART_HandleTypeDef *husart)
-{
-  uint32_t tmpreg = 0x00U;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
-  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
-  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
-  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
-  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
-  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
-  assert_param(IS_USART_PARITY(husart->Init.Parity));
-  assert_param(IS_USART_MODE(husart->Init.Mode));
-
-  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
-     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
-  /*---------------------------- USART CR2 Configuration ---------------------*/
-  tmpreg = husart->Instance->CR2;
-  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP));
-  /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
-  /* Set CPOL bit according to husart->Init.CLKPolarity value */
-  /* Set CPHA bit according to husart->Init.CLKPhase value */
-  /* Set LBCL bit according to husart->Init.CLKLastBit value */
-  /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
-  tmpreg |= (uint32_t)(USART_CLOCK_ENABLE | husart->Init.CLKPolarity |
-                       husart->Init.CLKPhase | husart->Init.CLKLastBit | husart->Init.StopBits);
-  /* Write to USART CR2 */
-  WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = husart->Instance->CR1;
-
-  /* Clear M, PCE, PS, TE, RE and OVER8 bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-                                   USART_CR1_RE | USART_CR1_OVER8));
-
-  /* Configure the USART Word Length, Parity and mode:
-     Set the M bits according to husart->Init.WordLength value
-     Set PCE and PS bits according to husart->Init.Parity value
-     Set TE and RE bits according to husart->Init.Mode value
-     Force OVER8 bit to 1 in order to reach the max USART frequencies */
-  tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
-
-  /* Write to USART CR1 */
-  WRITE_REG(husart->Instance->CR1, (uint32_t)tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if (husart->Instance == USART1)
-  {
-    pclk = HAL_RCC_GetPCLK2Freq();
-    husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
-  }
-  else
-  {
-    pclk = HAL_RCC_GetPCLK1Freq();
-    husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c
deleted file mode 100644
index 147edff5905..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_wwdg.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_wwdg.c
-  * @author  MCD Application Team
-  * @brief   WWDG HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Window Watchdog (WWDG) peripheral:
-  *           + Initialization and Configuration functions
-  *           + IO operation functions
-  @verbatim
-  ==============================================================================
-                      ##### WWDG Specific features #####
-  ==============================================================================
-  [..]
-    Once enabled the WWDG generates a system reset on expiry of a programmed
-    time period, unless the program refreshes the counter (T[6;0] downcounter)
-    before reaching 0x3F value (i.e. a reset is generated when the counter
-    value rolls down from 0x40 to 0x3F).
-
-    (+) An MCU reset is also generated if the counter value is refreshed
-        before the counter has reached the refresh window value. This
-        implies that the counter must be refreshed in a limited window.
-    (+) Once enabled the WWDG cannot be disabled except by a system reset.
-    (+) If required by application, an Early Wakeup Interrupt can be triggered
-        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
-        (EWI) can be used if specific safety operations or data logging must
-        be performed before the actual reset is generated. When the downcounter
-        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
-        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
-        disabled except by a system reset.
-    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
-        reset occurs.
-    (+) The WWDG counter input clock is derived from the APB clock divided
-        by a programmable prescaler.
-    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
-    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
-        where T[5;0] are the lowest 6 bits of Counter.
-    (+) WWDG Counter refresh is allowed between the following limits :
-        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
-        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
-    (+) Typical values:
-        (++) Counter min (T[5;0] = 0x00) at 32MHz (PCLK1) with zero prescaler:
-             max timeout before reset: approximately 41.79�s
-        (++) Counter max (T[5;0] = 0x3F) at 32MHz (PCLK1) with prescaler
-             dividing by 8:
-             max timeout before reset: approximately 342.38ms
-
-                     ##### How to use this driver #####
-  ==============================================================================
-
-    *** Common driver usage ***
-    ===========================
-
-  [..]
-    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-    (+) Configure the WWDG prescaler, refresh window value, counter value and early
-        interrupt status using HAL_WWDG_Init() function. This will automatically
-        enable WWDG and start its downcounter. Time reference can be taken from 
-        function exit. Care must be taken to provide a counter value
-        greater than 0x40 to prevent generation of immediate reset.
-    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
-        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
-        triggered by the interrupt service routine, flag will be automatically
-        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
-        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
-    (+) Then the application program must refresh the WWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
-        HAL_WWDG_Refresh() function. This operation must occur only when
-        the counter is lower than the refresh window value already programmed.
-
-    *** Callback registration ***
-    =============================
-
-  [..]
-    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
-    the user to configure dynamically the driver callbacks. Use Functions
-    HAL_WWDG_RegisterCallback() to register a user callback.
-
-    (+) Function HAL_WWDG_RegisterCallback() allows to register following
-        callbacks:
-        (++) EwiCallback : callback for Early WakeUp Interrupt.
-        (++) MspInitCallback : WWDG MspInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
-    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
-    takes as parameters the HAL peripheral handle and the Callback ID.
-    This function allows to reset following callbacks:
-        (++) EwiCallback : callback for  Early WakeUp Interrupt.
-        (++) MspInitCallback : WWDG MspInit.
-
-    [..]
-    When calling HAL_WWDG_Init function, callbacks are reset to the
-    corresponding legacy weak (surcharged) functions:
-    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
-    not been registered before.
-
-    [..]
-    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registering feature is not available
-    and weak (surcharged) callbacks are used.
-
-    *** WWDG HAL driver macros list ***
-    ===================================
-    [..]
-      Below the list of available macros in WWDG HAL driver.
-      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
-      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
-      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
-      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-/** @defgroup WWDG WWDG
-  * @brief WWDG HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
-  *  @brief    Initialization and Configuration functions.
-  *
-@verbatim
-  ==============================================================================
-          ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-      (+) Initialize and start the WWDG according to the specified parameters
-          in the WWDG_InitTypeDef of associated handle.
-      (+) Initialize the WWDG MSP.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the WWDG according to the specified.
-  *         parameters in the WWDG_InitTypeDef of  associated handle.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Check the WWDG handle allocation */
-  if (hwwdg == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
-  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
-  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
-  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-  /* Reset Callback pointers */
-  if (hwwdg->EwiCallback == NULL)
-  {
-    hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
-  }
-
-  if (hwwdg->MspInitCallback == NULL)
-  {
-    hwwdg->MspInitCallback = HAL_WWDG_MspInit;
-  }
-
-  /* Init the low level hardware */
-  hwwdg->MspInitCallback(hwwdg);
-#else
-  /* Init the low level hardware */
-  HAL_WWDG_MspInit(hwwdg);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-  /* Set WWDG Counter */
-  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
-
-  /* Set WWDG Prescaler and Window */
-  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initialize the WWDG MSP.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @note   When rewriting this function in user file, mechanism may be added
-  *         to avoid multiple initialize when HAL_WWDG_Init function is called
-  *         again to change parameters.
-  * @retval None
-  */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_WWDG_MspInit could be implemented in the user file
-   */
-}
-
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User WWDG Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param  hwwdg WWDG handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
-  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
-                                            pWWDG_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    switch (CallbackID)
-    {
-      case HAL_WWDG_EWI_CB_ID:
-        hwwdg->EwiCallback = pCallback;
-        break;
-
-      case HAL_WWDG_MSPINIT_CB_ID:
-        hwwdg->MspInitCallback = pCallback;
-        break;
-
-      default:
-        status = HAL_ERROR;
-        break;
-    }
-  }
-
-  return status;
-}
-
-
-/**
-  * @brief  Unregister a WWDG Callback
-  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
-  * @param  hwwdg WWDG handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
-  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  switch (CallbackID)
-  {
-    case HAL_WWDG_EWI_CB_ID:
-      hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
-      break;
-
-    case HAL_WWDG_MSPINIT_CB_ID:
-      hwwdg->MspInitCallback = HAL_WWDG_MspInit;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
-  *  @brief    IO operation functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Refresh the WWDG.
-    (+) Handle WWDG interrupt request and associated function callback.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Refresh the WWDG.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Write to WWDG CR the WWDG Counter value to refresh with */
-  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle WWDG interrupt request.
-  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
-  *         or data logging must be performed before the actual reset is generated.
-  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
-  *         EWIMode set to WWDG_EWI_ENABLE.
-  *         When the downcounter reaches the value 0x40, and EWI interrupt is
-  *         generated and the corresponding Interrupt Service Routine (ISR) can
-  *         be used to trigger specific actions (such as communications or data
-  *         logging), before resetting the device.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval None
-  */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Check if Early Wakeup Interrupt is enable */
-  if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
-  {
-    /* Check if WWDG Early Wakeup Interrupt occurred */
-    if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
-    {
-      /* Clear the WWDG Early Wakeup flag */
-      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-      /* Early Wakeup registered callback */
-      hwwdg->EwiCallback(hwwdg);
-#else
-      /* Early Wakeup callback */
-      HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-    }
-  }
-}
-
-
-/**
-  * @brief  WWDG Early Wakeup callback.
-  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hwwdg);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_adc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_adc.c
deleted file mode 100644
index c674ab1ab0e..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_adc.c
+++ /dev/null
@@ -1,883 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_adc.c
-  * @author  MCD Application Team
-  * @brief   ADC LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_adc.h"
-#include "stm32l1xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (ADC1)
-
-/** @addtogroup ADC_LL ADC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* common to several ADC instances.                                           */
-#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
-  (   ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
-   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
-  )
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* ADC instance.                                                              */
-#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
-  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
-   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
-  )
-
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
-  (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
-   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
-  )
-
-#define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__)                            \
-  (   ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE)                             \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES)                 \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES)                \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES)                \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES)                \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES)               \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES)               \
-  )
-
-#define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__)                        \
-  (   ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE)                         \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE)                   \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE)               \
-   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES)         \
-  )
-
-#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)                           \
-  (   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \
-   || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE)                         \
-  )
-
-#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)                             \
-  (   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \
-   || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE)                              \
-  )
-
-#define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__)                             \
-  (   ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A)                          \
-   || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B)                          \
-  )
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* ADC group regular                                                          */
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
-  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2)                  \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO)                 \
-   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
-  )
-
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
-  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
-   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
-  )
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
-  (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
-   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
-   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
-  )
-
-#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__)           \
-  (   ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV)      \
-   || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV)       \
-  )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
-  (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
-   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
-  )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
-  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
-   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
-  )
-
-/* Check of parameters for configuration of ADC hierarchical scope:           */
-/* ADC group injected                                                         */
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
-  (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO)                 \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)                  \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1)                 \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
-   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
-  )
-
-#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
-  (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
-   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
-   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
-  )
-
-#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
-  (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
-   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
-  )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
-  (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
-   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
-   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
-   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
-  )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
-  (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
-   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of all ADC instances belonging to
-  *         the same ADC common instance to their default reset values.
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC common registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  
-  /* Force reset of ADC clock (core clock) */
-  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
-  
-  /* Release reset of ADC clock (core clock) */
-  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
-  
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize some features of ADC common parameters
-  *         (all ADC instances belonging to the same ADC common instance)
-  *         and multimode (for devices with several ADC instances available).
-  * @note   The setting of ADC common parameters is conditioned to
-  *         ADC instances state:
-  *         All ADC instances belonging to the same ADC common instance
-  *         must be disabled.
-  * @param  ADCxy_COMMON ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC common registers are initialized
-  *          - ERROR: ADC common registers are not initialized
-  */
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
-  
-  /* Note: Hardware constraint (refer to description of functions             */
-  /*       "LL_ADC_SetCommonXXX()":                                           */
-  /*       On this STM32 serie, setting of these features is conditioned to   */
-  /*       ADC state:                                                         */
-  /*       All ADC instances of the ADC common group must be disabled.        */
-  if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - common to several ADC                                               */
-    /*    (all ADC instances belonging to the same ADC common instance)       */
-    /*    - Set ADC clock (conversion clock)                                  */
-    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
-  }
-  else
-  {
-    /* Initialization error: One or several ADC instances belonging to        */
-    /* the same ADC common instance are not disabled.                         */
-    status = ERROR;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
-  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
-  *                              whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
-  /* Set ADC_CommonInitStruct fields to default values */
-  /* Set fields of ADC common */
-  /* (all ADC instances belonging to the same ADC common instance) */
-  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
-  
-}
-
-/**
-  * @brief  De-initialize registers of the selected ADC instance
-  *         to their default reset values.
-  * @note   To reset all ADC instances quickly (perform a hard reset),
-  *         use function @ref LL_ADC_CommonDeInit().
-  * @param  ADCx ADC instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are de-initialized
-  *          - ERROR: ADC registers are not de-initialized
-  */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
-  /* Disable ADC instance if not already disabled.                            */
-  if(LL_ADC_IsEnabled(ADCx) == 1U)
-  {
-    /* Set ADC group regular trigger source to SW start to ensure to not      */
-    /* have an external trigger event occurring during the conversion stop    */
-    /* ADC disable process.                                                   */
-    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-    
-    /* Set ADC group injected trigger source to SW start to ensure to not     */
-    /* have an external trigger event occurring during the conversion stop    */
-    /* ADC disable process.                                                   */
-    LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-    
-    /* Disable the ADC instance */
-    LL_ADC_Disable(ADCx);
-  }
-  
-  /* Check whether ADC state is compliant with expected state */
-  /* (hardware requirements of bits state to reset registers below) */
-  if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
-  {
-    /* ========== Reset ADC registers ========== */
-    /* Reset register SR */
-    CLEAR_BIT(ADCx->SR,
-              (  LL_ADC_FLAG_STRT
-               | LL_ADC_FLAG_JSTRT
-               | LL_ADC_FLAG_EOCS
-               | LL_ADC_FLAG_OVR
-               | LL_ADC_FLAG_JEOS
-               | LL_ADC_FLAG_AWD1 )
-             );
-    
-    /* Reset register CR1 */
-    CLEAR_BIT(ADCx->CR1,
-              (  ADC_CR1_OVRIE   | ADC_CR1_RES     | ADC_CR1_AWDEN
-               | ADC_CR1_JAWDEN  | ADC_CR1_PDI     | ADC_CR1_PDD
-               | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
-               | ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN
-               | ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE
-               | ADC_CR1_AWDCH                                     )
-             );
-    
-    /* Reset register CR2 */
-    #if defined(ADC_CR2_CFG)
-    CLEAR_BIT(ADCx->CR2,
-              (  ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL
-               | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
-               | ADC_CR2_ALIGN    | ADC_CR2_EOCS
-               | ADC_CR2_DDS      | ADC_CR2_DMA    | ADC_CR2_DELS
-               | ADC_CR2_CFG      | ADC_CR2_CONT   | ADC_CR2_ADON   )
-             );
-    #else
-    CLEAR_BIT(ADCx->CR2,
-              (  ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL
-               | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
-               | ADC_CR2_ALIGN    | ADC_CR2_EOCS
-               | ADC_CR2_DDS      | ADC_CR2_DMA    | ADC_CR2_DELS
-               | ADC_CR2_CONT     | ADC_CR2_ADON                    )
-             );
-    #endif /* ADC_CR2_CFG */
-    
-    /* Reset register SMPR1 */
-    /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available    */
-    /*       on all devices: only on STM32L1 Cat.4 and Cat.5.                 */
-    #if defined(ADC_SMPR0_SMP31)
-    CLEAR_BIT(ADCx->SMPR1,
-              (  ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27
-               | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24
-               | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21
-               | ADC_SMPR1_SMP20                                    )
-             );
-    #else
-    CLEAR_BIT(ADCx->SMPR1,
-              (  ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24
-               | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21
-               | ADC_SMPR1_SMP20                                    )
-             );
-    #endif /* ADC_SMPR0_SMP31 */
-    
-    /* Reset register SMPR2 */
-    CLEAR_BIT(ADCx->SMPR2,
-              (  ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
-               | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
-               | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
-               | ADC_SMPR2_SMP10                                    )
-             );
-    
-    /* Reset register SMPR3 */
-    CLEAR_BIT(ADCx->SMPR3,
-              (  ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7
-               | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4
-               | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1
-               | ADC_SMPR3_SMP0                                  )
-             );
-    
-    #if defined(ADC_SMPR0_SMP31)
-    /* Reset register SMPR0 */
-    CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30));
-    #endif /* ADC_SMPR0_SMP31 */
-    
-    /* Reset register JOFR1 */
-    CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
-    /* Reset register JOFR2 */
-    CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
-    /* Reset register JOFR3 */
-    CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
-    /* Reset register JOFR4 */
-    CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
-    
-    /* Reset register HTR */
-    SET_BIT(ADCx->HTR, ADC_HTR_HT);
-    /* Reset register LTR */
-    CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
-    
-    /* Reset register SQR1 */
-    CLEAR_BIT(ADCx->SQR1,
-              (  ADC_SQR1_L
-    #if defined(ADC_SQR1_SQ28)
-               | ADC_SQR1_SQ28 | ADC_SQR1_SQ27
-    #endif
-               | ADC_SQR1_SQ26 | ADC_SQR1_SQ25)
-             );
-    
-    /* Reset register SQR2 */
-    CLEAR_BIT(ADCx->SQR2,
-              (  ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22
-               | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19)
-             );
-    
-    /* Reset register SQR3 */
-    CLEAR_BIT(ADCx->SQR3,
-              (  ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16
-               | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13)
-             );
-    
-    /* Reset register SQR4 */
-    CLEAR_BIT(ADCx->SQR4,
-              (  ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10
-               | ADC_SQR4_SQ9  | ADC_SQR4_SQ8  | ADC_SQR4_SQ7 )
-             );
-    
-    /* Reset register SQR5 */
-    CLEAR_BIT(ADCx->SQR5,
-              (  ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4
-               | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )
-             );
-    
-    
-    /* Reset register JSQR */
-    CLEAR_BIT(ADCx->JSQR,
-              (  ADC_JSQR_JL
-               | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
-               | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  )
-             );
-    
-    /* Reset register DR */
-    /* bits in access mode read only, no direct reset applicable */
-    
-    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
-    /* bits in access mode read only, no direct reset applicable */
-    
-    /* Reset register CCR */
-    CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Initialize some features of ADC instance.
-  * @note   These parameters have an impact on ADC scope: ADC instance.
-  *         Affects both group regular and group injected (availability
-  *         of ADC group injected depends on STM32 families).
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  * @note   After using this function, some other features must be configured
-  *         using LL unitary functions.
-  *         The minimum configuration remaining to be done is:
-  *          - Set ADC group regular or group injected sequencer:
-  *            map channel on the selected sequencer rank.
-  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
-  *          - Set ADC channel sampling time
-  *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @param  ADCx ADC instance
-  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are initialized
-  *          - ERROR: ADC registers are not initialized
-  */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
-  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
-  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
-  /* Note: On STM32L1, low power feature is set by concatenating              */
-  /*       values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT                          */
-  /*       and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF.                           */
-  /*       Check of the parameter is done for each of group of values,        */
-  /*       by excluding the other group of values.                            */
-  assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD)));
-  assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS)));
-  assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
-  
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       ADC instance must be disabled.                                     */
-  if(LL_ADC_IsEnabled(ADCx) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - ADC instance                                                        */
-    /*    - Set ADC data resolution                                           */
-    /*    - Set ADC conversion data alignment                                 */
-    /*    - Set ADC low power mode                                            */
-    MODIFY_REG(ADCx->CR1,
-                 ADC_CR1_RES
-               | ADC_CR1_PDI
-               | ADC_CR1_PDD
-               | ADC_CR1_SCAN
-              ,
-                 ADC_InitStruct->Resolution
-               | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD))
-               | ADC_InitStruct->SequencersScanMode
-              );
-    
-    MODIFY_REG(ADCx->CR2,
-                 ADC_CR2_ALIGN
-               | ADC_CR2_DELS
-              ,
-                 ADC_InitStruct->DataAlignment
-               | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS)
-              );
-
-  }
-  else
-  {
-    /* Initialization error: ADC instance is not disabled. */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
-  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
-  *                        whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
-{
-  /* Set ADC_InitStruct fields to default values */
-  /* Set fields of ADC instance */
-  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
-  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
-  ADC_InitStruct->LowPowerMode  = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE);
-  
-  /* Enable scan mode to have a generic behavior with ADC of other            */
-  /* STM32 families, without this setting available:                          */
-  /* ADC group regular sequencer and ADC group injected sequencer depend      */
-  /* only of their own configuration.                                         */
-  ADC_InitStruct->SequencersScanMode      = LL_ADC_SEQ_SCAN_ENABLE;
-  
-}
-
-/**
-  * @brief  Initialize some features of ADC group regular.
-  * @note   These parameters have an impact on ADC scope: ADC group regular.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "REG").
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  * @note   After using this function, other features must be configured
-  *         using LL unitary functions.
-  *         The minimum configuration remaining to be done is:
-  *          - Set ADC group regular or group injected sequencer:
-  *            map channel on the selected sequencer rank.
-  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
-  *          - Set ADC channel sampling time
-  *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @param  ADCx ADC instance
-  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are initialized
-  *          - ERROR: ADC registers are not initialized
-  */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
-  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
-  if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
-  {
-    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
-  }
-  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
-  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
-
-  /* ADC group regular continuous mode and discontinuous mode                 */
-  /* can not be enabled simultenaeously                                       */
-  assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
-               || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
-
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       ADC instance must be disabled.                                     */
-  if(LL_ADC_IsEnabled(ADCx) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - ADC group regular                                                   */
-    /*    - Set ADC group regular trigger source                              */
-    /*    - Set ADC group regular sequencer length                            */
-    /*    - Set ADC group regular sequencer discontinuous mode                */
-    /*    - Set ADC group regular continuous mode                             */
-    /*    - Set ADC group regular conversion data transfer: no transfer or    */
-    /*      transfer by DMA, and DMA requests mode                            */
-    /* Note: On this STM32 serie, ADC trigger edge is set when starting       */
-    /*       ADC conversion.                                                  */
-    /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().      */
-    if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
-    {
-      MODIFY_REG(ADCx->CR1,
-                   ADC_CR1_DISCEN
-                 | ADC_CR1_DISCNUM
-                ,
-                   ADC_REG_InitStruct->SequencerLength
-                 | ADC_REG_InitStruct->SequencerDiscont
-                );
-    }
-    else
-    {
-      MODIFY_REG(ADCx->CR1,
-                   ADC_CR1_DISCEN
-                 | ADC_CR1_DISCNUM
-                ,
-                   ADC_REG_InitStruct->SequencerLength
-                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
-                );
-    }
-    
-    MODIFY_REG(ADCx->CR2,
-                 ADC_CR2_EXTSEL
-               | ADC_CR2_EXTEN
-               | ADC_CR2_CONT
-               | ADC_CR2_DMA
-               | ADC_CR2_DDS
-              ,
-                (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
-               | ADC_REG_InitStruct->ContinuousMode
-               | ADC_REG_InitStruct->DMATransfer
-              );
-
-    /* Set ADC group regular sequencer length and scan direction */
-    /* Note: Hardware constraint (refer to description of this function):     */
-    /* Note: If ADC instance feature scan mode is disabled                    */
-    /*       (refer to  ADC instance initialization structure                 */
-    /*       parameter @ref SequencersScanMode                                */
-    /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
-    /*       this parameter is discarded.                                     */
-    LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
-  }
-  else
-  {
-    /* Initialization error: ADC instance is not disabled. */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
-  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
-  *                            whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
-  /* Set ADC_REG_InitStruct fields to default values */
-  /* Set fields of ADC group regular */
-  /* Note: On this STM32 serie, ADC trigger edge is set when starting         */
-  /*       ADC conversion.                                                    */
-  /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().        */
-  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
-  ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
-  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
-  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
-  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
-}
-
-/**
-  * @brief  Initialize some features of ADC group injected.
-  * @note   These parameters have an impact on ADC scope: ADC group injected.
-  *         Refer to corresponding unitary functions into
-  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
-  *         (functions with prefix "INJ").
-  * @note   The setting of these parameters by function @ref LL_ADC_Init()
-  *         is conditioned to ADC state:
-  *         ADC instance must be disabled.
-  *         This condition is applied to all ADC features, for efficiency
-  *         and compatibility over all STM32 families. However, the different
-  *         features can be set under different ADC state conditions
-  *         (setting possible with ADC enabled without conversion on going,
-  *         ADC enabled with conversion on going, ...)
-  *         Each feature can be updated afterwards with a unitary function
-  *         and potentially with ADC in a different state than disabled,
-  *         refer to description of each function for setting
-  *         conditioned to ADC state.
-  * @note   After using this function, other features must be configured
-  *         using LL unitary functions.
-  *         The minimum configuration remaining to be done is:
-  *          - Set ADC group injected sequencer:
-  *            map channel on the selected sequencer rank.
-  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
-  *          - Set ADC channel sampling time
-  *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @param  ADCx ADC instance
-  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ADC registers are initialized
-  *          - ERROR: ADC registers are not initialized
-  */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
-  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
-  if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
-  {
-    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
-  }
-  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-  
-  /* Note: Hardware constraint (refer to description of this function):       */
-  /*       ADC instance must be disabled.                                     */
-  if(LL_ADC_IsEnabled(ADCx) == 0U)
-  {
-    /* Configuration of ADC hierarchical scope:                               */
-    /*  - ADC group injected                                                  */
-    /*    - Set ADC group injected trigger source                             */
-    /*    - Set ADC group injected sequencer length                           */
-    /*    - Set ADC group injected sequencer discontinuous mode               */
-    /*    - Set ADC group injected conversion trigger: independent or         */
-    /*      from ADC group regular                                            */
-    /* Note: On this STM32 serie, ADC trigger edge is set when starting       */
-    /*       ADC conversion.                                                  */
-    /*       Refer to function @ref LL_ADC_INJ_StartConversionExtTrig().      */
-    if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
-    {
-      MODIFY_REG(ADCx->CR1,
-                   ADC_CR1_JDISCEN
-                 | ADC_CR1_JAUTO
-                ,
-                   ADC_INJ_InitStruct->SequencerDiscont
-                 | ADC_INJ_InitStruct->TrigAuto
-                );
-    }
-    else
-    {
-      MODIFY_REG(ADCx->CR1,
-                   ADC_CR1_JDISCEN
-                 | ADC_CR1_JAUTO
-                ,
-                   LL_ADC_REG_SEQ_DISCONT_DISABLE
-                 | ADC_INJ_InitStruct->TrigAuto
-                );
-    }
-    
-    MODIFY_REG(ADCx->CR2,
-                 ADC_CR2_JEXTSEL
-               | ADC_CR2_JEXTEN
-              ,
-                (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
-              );
-    
-    /* Note: Hardware constraint (refer to description of this function):     */
-    /* Note: If ADC instance feature scan mode is disabled                    */
-    /*       (refer to  ADC instance initialization structure                 */
-    /*       parameter @ref SequencersScanMode                                */
-    /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
-    /*       this parameter is discarded.                                     */
-    LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
-  }
-  else
-  {
-    /* Initialization error: ADC instance is not disabled. */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
-  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
-  *                            whose fields will be set to default values.
-  * @retval None
-  */
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
-  /* Set ADC_INJ_InitStruct fields to default values */
-  /* Set fields of ADC group injected */
-  ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
-  ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
-  ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
-  ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ADC1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_comp.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_comp.c
deleted file mode 100644
index d0d694dca6c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_comp.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_comp.c
-  * @author  MCD Application Team
-  * @brief   COMP LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_comp.h"
-
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (COMP1) || defined (COMP2)
-
-/** @addtogroup COMP_LL COMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup COMP_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of COMP hierarchical scope:          */
-/* COMP instance.                                                             */
-
-#define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
-  (   ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
-   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
-  )
-
-/* Note: On this STM32 serie, comparator input plus parameters are            */
-/*       the different depending on COMP instances.                           */
-#if defined(RI_ASCR1_CH_31)
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO7)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO8)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO9)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO10)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO11)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO12)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO13)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO14)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO15)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO16)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO17)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO18)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO19)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO20)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO21)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO22)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO23)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO24)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO25)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO26)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO27)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO28)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO29)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO30)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO31)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO32)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO33)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_NONE)                        \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_NONE)                        \
-      )                                                                        \
-  )
-#else
-#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO7)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO8)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO9)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO10)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO11)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO12)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO13)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO14)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO15)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO16)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO17)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO18)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO19)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO20)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO21)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO22)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO23)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO24)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO25)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO26)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO27)                        \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO28)                        \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
-       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
-      )                                                                        \
-  )
-#endif
-
-/* Note: On this STM32 serie, comparator input minus parameters are           */
-/*       the different depending on COMP instances.                           */
-#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
-  (((__COMP_INSTANCE__) == COMP1)                                              \
-    ? (                                                                        \
-          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                  \
-       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                       \
-      )                                                                        \
-  )
-
-#define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__)                      \
-  (   ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE)                          \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4)                      \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCREFCLR)                 \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC4)                      \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCREFCLR)                 \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4)                      \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCREFCLR)                 \
-   || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM10_IC1)                     \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup COMP_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of the selected COMP instance
-  *         to their default reset values.
-  * @note   If comparator is locked, de-initialization by software is
-  *         not possible.
-  *         The only way to unlock the comparator is a device hardware reset.
-  * @param  COMPx COMP instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: COMP registers are de-initialized
-  *          - ERROR: COMP registers are not de-initialized
-  */
-ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-  
-    /* Note: On this STM32 serie, only COMP instance COMP2 has                */
-    /*       features settables: power mode, input minus selection            */
-    /*       and output selection.                                            */
-    /* Note: On this STM32 serie, setting COMP instance COMP2 input minus     */
-    /*       is enabling the comparator.                                      */
-    /*       Reset COMP2 input minus also disable the comparator.             */
-    /* Note: In case of de-initialization of COMP instance COMP1:             */
-    /*       Switch COMP_CSR_SW1 is not modified because can be used          */
-    /*       to connect OPAMP3 to ADC.                                        */
-    /*       Switches RI_ASCR1_VCOMP, RI_ASCR1_SCM are reset: let routing     */
-    /*       interface under control of ADC.                                  */
-    if(COMPx == COMP1)
-    {
-      CLEAR_BIT(COMP->CSR,
-                (  COMP_CSR_CMP1EN
-                 | COMP_CSR_10KPU
-                 | COMP_CSR_400KPU
-                 | COMP_CSR_10KPD
-                 | COMP_CSR_400KPD
-                ) 
-               );
-    }
-    else
-    {
-      CLEAR_BIT(COMP->CSR,
-                (  COMP_CSR_SPEED
-                 | COMP_CSR_INSEL
-                 | COMP_CSR_OUTSEL
-                ) 
-               );
-    }
-    
-    /* Set comparator input plus */
-    LL_COMP_SetInputPlus(COMPx, LL_COMP_INPUT_PLUS_NONE);
-    
-  return status;
-}
-
-/**
-  * @brief  Initialize some features of COMP instance.
-  * @note   This function configures features of the selected COMP instance.
-  *         Some features are also available at scope COMP common instance
-  *         (common to several COMP instances).
-  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
-  * @param  COMPx COMP instance
-  * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: COMP registers are initialized
-  *          - ERROR: COMP registers are not initialized
-  */
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
-  if(COMPx == COMP2)
-  {
-    assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
-    assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
-    assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
-  }
-  assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
-  
-  /* Configuration of comparator instance :                                 */
-  /*  - PowerMode                                                           */
-  /*  - InputPlus                                                           */
-  /*  - InputMinus                                                          */
-  /*  - OutputSelection                                                     */
-  /* Note: On this STM32 serie, only COMP instance COMP2 has                */
-  /*       features settables: power mode, input minus selection            */
-  /*       and output selection.                                            */
-  /* Note: On this STM32 serie, setting COMP instance COMP2 input minus     */
-  /*       is enabling the comparator.                                      */
-  if(COMPx == COMP2)
-  {
-    MODIFY_REG(COMP->CSR,
-                 COMP_CSR_SPEED
-               | COMP_CSR_INSEL
-               | COMP_CSR_OUTSEL
-              ,
-                 COMP_InitStruct->PowerMode
-               | COMP_InitStruct->InputMinus
-               | COMP_InitStruct->OutputSelection
-              );
-    
-    /* Set comparator input plus */
-    LL_COMP_SetInputPlus(COMPx, COMP_InitStruct->InputPlus);
-  }
-  else /* COMPx == COMP1 */
-  {
-    /* If window mode is enabled, COMP1 input plus is not used and therefore
-       not modified */
-    if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WNDWE) == COMP_CSR_WNDWE)
-    {
-      /* Set comparator input plus */
-      LL_COMP_SetInputPlus(COMPx, COMP_InitStruct->InputPlus);
-    }
-  }
-    
-  return status;
-}
-
-/**
-  * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
-  * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
-{
-  /* Set COMP_InitStruct fields to default values */
-  COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_ULTRALOWPOWER;
-  COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
-  COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
-  COMP_InitStruct->OutputSelection      = LL_COMP_OUTPUT_NONE;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* COMP1 || COMP2 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_crc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_crc.c
deleted file mode 100644
index 08ab425c3a6..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_crc.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_crc.c
-  * @author  MCD Application Team
-  * @brief   CRC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_crc.h"
-#include "stm32l1xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif/* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (CRC)
-
-/** @addtogroup CRC_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize CRC registers (Registers restored to their default values).
-  * @param  CRCx CRC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: CRC registers are de-initialized
-  *          - ERROR: CRC registers are not de-initialized
-  */
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
-
-  if (CRCx == CRC)
-  {
-    /* Force CRC reset */
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
-
-    /* Release CRC reset */
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (CRC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dac.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dac.c
deleted file mode 100644
index 8b692fc980c..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dac.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_dac.c
-  * @author  MCD Application Team
-  * @brief   DAC LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_dac.h"
-#include "stm32l1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(DAC1)
-
-/** @addtogroup DAC_LL DAC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup DAC_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)        \
-  (  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
-     || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
-  )
-
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
-  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM9_TRGO)                      \
-   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
-  )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)              \
-  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
-      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
-      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
-  )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)  \
-  ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
-     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                           \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                    \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                   \
-    )                                                                                                     \
-    ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                          \
-       && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                           \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                        \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                        \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                     \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                     \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                    \
-      )                                                                                                   \
-  )
-
-#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
-  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
-      || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                 \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of the selected DAC instance
-  *         to their default reset values.
-  * @param  DACx DAC instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DAC registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(DACx));
-
-  /* Force reset of DAC clock */
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
-
-  /* Release reset of DAC clock */
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize some features of DAC channel.
-  * @note   @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
-  *         Leaving it ready to be enabled and output:
-  *         a level by calling one of
-  *           @ref LL_DAC_ConvertData12RightAligned
-  *           @ref LL_DAC_ConvertData12LeftAligned
-  *           @ref LL_DAC_ConvertData8RightAligned
-  *         or one of the supported autogenerated wave.
-  * @note   This function allows configuration of:
-  *          - Output mode
-  *          - Trigger
-  *          - Wave generation
-  * @note   The setting of these parameters by function @ref LL_DAC_Init()
-  *         is conditioned to DAC state:
-  *         DAC channel must be disabled.
-  * @param  DACx DAC instance
-  * @param  DAC_Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DAC_CHANNEL_1
-  *         @arg @ref LL_DAC_CHANNEL_2
-  * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DAC registers are initialized
-  *          - ERROR: DAC registers are not initialized
-  */
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(DACx));
-  assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
-  assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
-  assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
-  if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
-  {
-    assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
-                                                  DAC_InitStruct->WaveAutoGenerationConfig));
-  }
-
-  /* Note: Hardware constraint (refer to description of this function)        */
-  /*       DAC instance must be disabled.                                     */
-  if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
-  {
-    /* Configuration of DAC channel:                                          */
-    /*  - TriggerSource                                                       */
-    /*  - WaveAutoGeneration                                                  */
-    /*  - OutputBuffer                                                        */
-    /*  - OutputMode                                                          */
-    if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
-    {
-      MODIFY_REG(DACx->CR,
-                 (DAC_CR_TSEL1
-                  | DAC_CR_WAVE1
-                  | DAC_CR_MAMP1
-                  | DAC_CR_BOFF1
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                 ,
-                 (DAC_InitStruct->TriggerSource
-                  | DAC_InitStruct->WaveAutoGeneration
-                  | DAC_InitStruct->WaveAutoGenerationConfig
-                  | DAC_InitStruct->OutputBuffer
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                );
-    }
-    else
-    {
-      MODIFY_REG(DACx->CR,
-                 (DAC_CR_TSEL1
-                  | DAC_CR_WAVE1
-                  | DAC_CR_BOFF1
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                 ,
-                 (DAC_InitStruct->TriggerSource
-                  | LL_DAC_WAVE_AUTO_GENERATION_NONE
-                  | DAC_InitStruct->OutputBuffer
-                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
-                );
-    }
-  }
-  else
-  {
-    /* Initialization error: DAC instance is not disabled.                    */
-    status = ERROR;
-  }
-  return status;
-}
-
-/**
-  * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
-  * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
-  *                       whose fields will be set to default values.
-  * @retval None
-  */
-void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
-{
-  /* Set DAC_InitStruct fields to default values */
-  DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
-  DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
-  /* Note: Parameter discarded if wave auto generation is disabled,           */
-  /*       set anyway to its default value.                                   */
-  DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
-  DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC1 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dma.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dma.c
deleted file mode 100644
index 8f5fa3e8183..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_dma.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_dma.h"
-#include "stm32l1xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
-                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
-
-
-#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA2)
-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
-                                                         (((INSTANCE) == DMA2) && \
-                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
-                                                         (((INSTANCE) == DMA2) && \
-                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                          ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                            ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#endif
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the DMA registers to their default reset values.
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  *         @arg @ref LL_DMA_CHANNEL_ALL
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are de-initialized
-  *          - ERROR: DMA registers are not de-initialized
-  */
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
-  ErrorStatus status = SUCCESS;
-
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
-
-  if (Channel == LL_DMA_CHANNEL_ALL)
-  {
-    if (DMAx == DMA1)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
-    }
-#if defined(DMA2)
-    else if (DMAx == DMA2)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
-    }
-#endif
-    else
-    {
-      status = ERROR;
-    }
-  }
-  else
-  {
-    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
-    /* Disable the selected DMAx_Channely */
-    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
-    /* Reset DMAx_Channely control register */
-    LL_DMA_WriteReg(tmp, CCR, 0U);
-
-    /* Reset DMAx_Channely remaining bytes register */
-    LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
-    /* Reset DMAx_Channely peripheral address register */
-    LL_DMA_WriteReg(tmp, CPAR, 0U);
-
-    /* Reset DMAx_Channely memory address register */
-    LL_DMA_WriteReg(tmp, CMAR, 0U);
-
-
-    if (Channel == LL_DMA_CHANNEL_1)
-    {
-      /* Reset interrupt pending bits for DMAx Channel1 */
-      LL_DMA_ClearFlag_GI1(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_2)
-    {
-      /* Reset interrupt pending bits for DMAx Channel2 */
-      LL_DMA_ClearFlag_GI2(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_3)
-    {
-      /* Reset interrupt pending bits for DMAx Channel3 */
-      LL_DMA_ClearFlag_GI3(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_4)
-    {
-      /* Reset interrupt pending bits for DMAx Channel4 */
-      LL_DMA_ClearFlag_GI4(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_5)
-    {
-      /* Reset interrupt pending bits for DMAx Channel5 */
-      LL_DMA_ClearFlag_GI5(DMAx);
-    }
-
-    else if (Channel == LL_DMA_CHANNEL_6)
-    {
-      /* Reset interrupt pending bits for DMAx Channel6 */
-      LL_DMA_ClearFlag_GI6(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_7)
-    {
-      /* Reset interrupt pending bits for DMAx Channel7 */
-      LL_DMA_ClearFlag_GI7(DMAx);
-    }
-    else
-    {
-      status = ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
-  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
-  *         @arg @ref __LL_DMA_GET_INSTANCE
-  *         @arg @ref __LL_DMA_GET_CHANNEL
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are initialized
-  *          - ERROR: Not applicable
-  */
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
-  /* Check the DMA parameters from DMA_InitStruct */
-  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
-  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
-  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
-  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
-  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
-  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
-  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
-  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
-  /*---------------------------- DMAx CCR Configuration ------------------------
-   * Configure DMAx_Channely: data transfer direction, data transfer mode,
-   *                          peripheral and memory increment mode,
-   *                          data size alignment and  priority level with parameters :
-   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
-   * - Mode:           DMA_CCR_CIRC bit
-   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
-   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
-   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
-   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
-   * - Priority:               DMA_CCR_PL[1:0] bits
-   */
-  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
-                        DMA_InitStruct->Mode                   | \
-                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
-                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
-                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
-                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
-                        DMA_InitStruct->Priority);
-
-  /*-------------------------- DMAx CMAR Configuration -------------------------
-   * Configure the memory or destination base address with parameter :
-   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
-   */
-  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
-  /*-------------------------- DMAx CPAR Configuration -------------------------
-   * Configure the peripheral or source base address with parameter :
-   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
-   */
-  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
-  /*--------------------------- DMAx CNDTR Configuration -----------------------
-   * Configure the peripheral base address with parameter :
-   * - NbData: DMA_CNDTR_NDT[15:0] bits
-   */
-  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
-  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval None
-  */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
-  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
-  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
-  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
-  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
-  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
-  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = 0x00000000U;
-  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_exti.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_exti.c
deleted file mode 100644
index 8b6c6ef057b..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_exti.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_exti.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
-#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the EXTI registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: EXTI registers are de-initialized
-  *          - ERROR: not applicable
-  */
-uint32_t LL_EXTI_DeInit(void)
-{
-  /* Interrupt mask register set to default reset values */
-  LL_EXTI_WriteReg(IMR,   0x00000000U);
-  /* Event mask register set to default reset values */
-  LL_EXTI_WriteReg(EMR,   0x00000000U);
-  /* Rising Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(RTSR,  0x00000000U);
-  /* Falling Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(FTSR,  0x00000000U);
-  /* Software interrupt event register set to default reset values */
-  LL_EXTI_WriteReg(SWIER, 0x00000000U);
-  /* Pending register clear */
-  LL_EXTI_WriteReg(PR,    0x00FFFFFFU);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
-  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: EXTI registers are initialized
-  *          - ERROR: not applicable
-  */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  /* Check the parameters */
-  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
-  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
-  /* ENABLE LineCommand */
-  if (EXTI_InitStruct->LineCommand != DISABLE)
-  {
-    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
-    /* Configure EXTI Lines in range from 0 to 31 */
-    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
-    {
-      switch (EXTI_InitStruct->Mode)
-      {
-        case LL_EXTI_MODE_IT:
-          /* First Disable Event on provided Lines */
-          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable IT on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_EVENT:
-          /* First Disable IT on provided Lines */
-          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable Event on provided Lines */
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_IT_EVENT:
-          /* Directly Enable IT & Event on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        default:
-          status = ERROR;
-          break;
-      }
-      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
-      {
-        switch (EXTI_InitStruct->Trigger)
-        {
-          case LL_EXTI_TRIGGER_RISING:
-            /* First Disable Falling Trigger on provided Lines */
-            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Rising Trigger on provided Lines */
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_FALLING:
-            /* First Disable Rising Trigger on provided Lines */
-            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Falling Trigger on provided Lines */
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_RISING_FALLING:
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          default:
-            status = ERROR;
-            break;
-        }
-      }
-    }
-  }
-  /* DISABLE LineCommand */
-  else
-  {
-    /* De-configure EXTI Lines in range from 0 to 31 */
-    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
-  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval None
-  */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
-  EXTI_InitStruct->LineCommand    = DISABLE;
-  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
-  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (EXTI) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c
deleted file mode 100644
index 58653fb6611..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_fsmc.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_fsmc.c
-  * @author  MCD Application Team
-  * @brief   FSMC Low Layer HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### FSMC peripheral features #####
-  ==============================================================================
-  [..] The Flexible memory controller (FSMC) includes following memory controllers:
-       (+) The NOR/PSRAM memory controller
-
-  [..] The FSMC functional block makes the interface with synchronous and asynchronous static
-       memories. Its main purposes are:
-       (+) to translate AHB transactions into the appropriate external device protocol
-       (+) to meet the access time requirements of the external memory devices
-
-  [..] All external memories share the addresses, data and control signals with the controller.
-       Each external device is accessed by means of a unique Chip Select. The FSMC performs
-       only one access at a time to an external device.
-       The main features of the FSMC controller are the following:
-        (+) Interface with static-memory mapped devices including:
-           (++) Static random access memory (SRAM)
-           (++) Read-only memory (ROM)
-           (++) NOR Flash memory/OneNAND Flash memory
-           (++) PSRAM (4 memory banks)
-        (+) Independent Chip Select control for each memory bank
-        (+) Independent configuration for each memory bank
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED)
-
-/** @defgroup FSMC_LL  FSMC Low Layer
-  * @brief FSMC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
-  * @{
-  */
-
-/* ----------------------- FSMC registers bit mask --------------------------- */
-
-#if defined(FSMC_BANK1)
-/* --- BCR Register ---*/
-/* BCR register clear mask */
-
-/* --- BTR Register ---*/
-/* BTR register clear mask */
-#define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
-                                      FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
-                                      FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
-                                      FSMC_BTRx_ACCMOD))
-
-/* --- BWTR Register ---*/
-/* BWTR register clear mask */
-#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
-                                      FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
-                                      FSMC_BWTRx_ACCMOD))
-#endif /* FSMC_BANK1 */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
-  * @{
-  */
-
-#if defined(FSMC_BANK1)
-
-/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
-  * @brief  NORSRAM Controller functions
-  *
-  @verbatim
-  ==============================================================================
-                   ##### How to use NORSRAM device driver #####
-  ==============================================================================
-
-  [..]
-    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
-    to run the NORSRAM external devices.
-
-    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
-    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
-    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
-    (+) FSMC NORSRAM bank extended timing configuration using the function
-        FSMC_NORSRAM_Extended_Timing_Init()
-    (+) FSMC NORSRAM bank enable/disable write operation using the functions
-        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
-
-@endverbatim
-  * @{
-  */
-
-/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-  @verbatim
-  ==============================================================================
-              ##### Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the FSMC NORSRAM interface
-    (+) De-initialize the FSMC NORSRAM interface
-    (+) Configure the FSMC clock and associated GPIOs
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the FSMC_NORSRAM device according to the specified
-  *         control parameters in the FSMC_NORSRAM_InitTypeDef
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  Init Pointer to NORSRAM Initialization structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
-                                    FSMC_NORSRAM_InitTypeDef *Init)
-{
-  uint32_t flashaccess;
-  uint32_t btcr_reg;
-  uint32_t mask;
-
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
-  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
-  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
-  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
-  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
-  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
-  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
-  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
-  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
-  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
-  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
-  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
-  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
-  assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
-
-  /* Disable NORSRAM Device */
-  __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
-
-  /* Set NORSRAM device control parameters */
-  if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
-  {
-    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
-  }
-  else
-  {
-    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
-  }
-
-  btcr_reg = (flashaccess                   | \
-              Init->DataAddressMux          | \
-              Init->MemoryType              | \
-              Init->MemoryDataWidth         | \
-              Init->BurstAccessMode         | \
-              Init->WaitSignalPolarity      | \
-              Init->WaitSignalActive        | \
-              Init->WriteOperation          | \
-              Init->WaitSignal              | \
-              Init->ExtendedMode            | \
-              Init->AsynchronousWait        | \
-              Init->WriteBurst);
-
-  btcr_reg |= Init->WrapMode;
-  btcr_reg |= Init->PageSize;
-
-  mask = (FSMC_BCRx_MBKEN                |
-          FSMC_BCRx_MUXEN                |
-          FSMC_BCRx_MTYP                 |
-          FSMC_BCRx_MWID                 |
-          FSMC_BCRx_FACCEN               |
-          FSMC_BCRx_BURSTEN              |
-          FSMC_BCRx_WAITPOL              |
-          FSMC_BCRx_WAITCFG              |
-          FSMC_BCRx_WREN                 |
-          FSMC_BCRx_WAITEN               |
-          FSMC_BCRx_EXTMOD               |
-          FSMC_BCRx_ASYNCWAIT            |
-          FSMC_BCRx_CBURSTRW);
-
-  mask |= FSMC_BCRx_WRAPMOD;
-  mask |= FSMC_BCRx_CPSIZE;
-
-  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
-
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitialize the FSMC_NORSRAM peripheral
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  ExDevice Pointer to NORSRAM extended mode device instance
-  * @param  Bank NORSRAM bank number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
-                                     FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
-  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
-  /* Disable the FSMC_NORSRAM device */
-  __FSMC_NORSRAM_DISABLE(Device, Bank);
-
-  /* De-initialize the FSMC_NORSRAM device */
-  /* FSMC_NORSRAM_BANK1 */
-  if (Bank == FSMC_NORSRAM_BANK1)
-  {
-    Device->BTCR[Bank] = 0x000030DBU;
-  }
-  /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
-  else
-  {
-    Device->BTCR[Bank] = 0x000030D2U;
-  }
-
-  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
-  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
-  *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  Timing Pointer to NORSRAM Timing structure
-  * @param  Bank NORSRAM bank number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
-                                          FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
-
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
-  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
-  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
-  /* Set FSMC_NORSRAM device timing parameters */
-  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
-                                                       ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
-                                                       ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
-                                                       ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
-                                                       (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
-                                                       (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
-                                                       (Timing->AccessMode)));
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
-  *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  Timing Pointer to NORSRAM Timing structure
-  * @param  Bank NORSRAM bank number
-  * @param  ExtendedMode FSMC Extended Mode
-  *          This parameter can be one of the following values:
-  *            @arg FSMC_EXTENDED_MODE_DISABLE
-  *            @arg FSMC_EXTENDED_MODE_ENABLE
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
-                                                   FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
-                                                   uint32_t ExtendedMode)
-{
-  /* Check the parameters */
-  assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
-
-  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-  if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
-  {
-    /* Check the parameters */
-    assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
-    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-    assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
-    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
-                                                     ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
-                                                     ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
-                                                     Timing->AccessMode                                          |
-                                                     ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
-  }
-  else
-  {
-    Device->BWTR[Bank] = 0x0FFFFFFFU;
-  }
-
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
-  *  @brief   management functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### FSMC_NORSRAM Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the FSMC NORSRAM interface.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables dynamically FSMC_NORSRAM write operation.
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  Bank NORSRAM bank number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
-  /* Enable write operation */
-  SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables dynamically FSMC_NORSRAM write operation.
-  * @param  Device Pointer to NORSRAM device instance
-  * @param  Bank NORSRAM bank number
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
-  /* Disable write operation */
-  CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* FSMC_BANK1 */
-
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_NOR_MODULE_ENABLED */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_gpio.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_gpio.c
deleted file mode 100644
index 1561e69d1a1..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_gpio.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_gpio.h"
-#include "stm32l1xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
-
-/** @addtogroup GPIO_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
-                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
-
-#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_15 ))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize GPIO registers (Registers restored to their default values).
-  * @param  GPIOx GPIO Port
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are de-initialized
-  *          - ERROR:   Wrong GPIO Port
-  */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
-  /* Force and Release reset on clock of GPIOx Port */
-  if (GPIOx == GPIOA)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
-  }
-#if defined(GPIOD)
-  else if (GPIOx == GPIOD)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
-  }
-#endif /* GPIOD */
-#if defined(GPIOE)
-  else if (GPIOx == GPIOE)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
-  }
-#endif /* GPIOE */
-#if defined(GPIOF)
-  else if (GPIOx == GPIOF)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
-  }
-#endif /* GPIOF */
-#if defined(GPIOG)
-  else if (GPIOx == GPIOG)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
-  }
-#endif /* GPIOG */
-#if defined(GPIOH)
-  else if (GPIOx == GPIOH)
-  {
-    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
-    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
-  }
-#endif /* GPIOH */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
-  * @param  GPIOx GPIO Port
-  * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
-  *         that contains the configuration information for the specified GPIO peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
-  *          - ERROR:   Not applicable
-  */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  uint32_t pinpos     = 0x00000000U;
-  uint32_t currentpin = 0x00000000U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
-  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
-  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
-  /* ------------------------- Configure the port pins ---------------- */
-  /* Initialize  pinpos on first pin set */
-  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
-
-  /* Configure the port pins */
-  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
-  {
-    /* Get current io position */
-    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
-
-    if (currentpin)
-    {
-
-      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
-      {
-        /* Check Speed mode parameters */
-        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
-        /* Speed mode configuration */
-        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
-
-        /* Check Output mode parameters */
-        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
-        /* Output mode configuration*/
-        LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
-      }
-
-      /* Pull-up Pull down resistor configuration*/
-      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
-      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
-      {
-        /* Check Alternate parameter */
-        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
-        /* Speed mode configuration */
-        if (POSITION_VAL(currentpin) < 0x00000008U)
-        {
-          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-        else
-        {
-          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-      }
-
-      /* Pin Mode configuration */
-      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-    }
-    pinpos++;
-  }
-
-  return (SUCCESS);
-}
-
-/**
-  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
-  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
-  *                          whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
-  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
-  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
-  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
-  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
-  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_i2c.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_i2c.c
deleted file mode 100644
index 470969d0806..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_i2c.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_i2c.c
-  * @author  MCD Application Team
-  * @brief   I2C LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_i2c.h"
-#include "stm32l1xx_ll_bus.h"
-#include "stm32l1xx_ll_rcc.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup I2C_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-
-#define IS_LL_I2C_CLOCK_SPEED(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
-
-#define IS_LL_I2C_DUTY_CYCLE(__VALUE__)            (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
-                                                 ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
-
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
-
-#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
-                                                 ((__VALUE__) == LL_I2C_NACK))
-
-#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
-                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the I2C registers to their default reset values.
-  * @param  I2Cx I2C Instance.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS  I2C registers are de-initialized
-  *          - ERROR  I2C registers are not de-initialized
-  */
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
-  }
-  else if (I2Cx == I2C2)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
-  * @param  I2Cx I2C Instance.
-  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS  I2C registers are initialized
-  *          - ERROR  Not applicable
-  */
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  LL_RCC_ClocksTypeDef rcc_clocks;
-
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  /* Check the I2C parameters from I2C_InitStruct */
-  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
-  assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
-  assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
-  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
-  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
-  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
-
-  /* Disable the selected I2Cx Peripheral */
-  LL_I2C_Disable(I2Cx);
-
-  /* Retrieve Clock frequencies */
-  LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
-  /*---------------------------- I2Cx SCL Clock Speed Configuration ------------
-   * Configure the SCL speed :
-   * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
-   *           and I2C_CCR_CCR[11:0] bits
-   * - DutyCycle: I2C_CCR_DUTY[7:0] bits
-   */
-  LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
-
-  /*---------------------------- I2Cx OAR1 Configuration -----------------------
-   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
-   * - OwnAddress1:  I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
-   * - OwnAddrSize:  I2C_OAR1_ADDMODE bit
-   */
-  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-
-  /*---------------------------- I2Cx MODE Configuration -----------------------
-  * Configure I2Cx peripheral mode with parameter :
-   * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
-   */
-  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
-
-  /* Enable the selected I2Cx Peripheral */
-  LL_I2C_Enable(I2Cx);
-
-  /*---------------------------- I2Cx CR2 Configuration ------------------------
-   * Configure the ACKnowledge or Non ACKnowledge condition
-   * after the address receive match code or next received byte with parameter :
-   * - TypeAcknowledge: I2C_CR2_NACK bit
-   */
-  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
-  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval None
-  */
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  /* Set I2C_InitStruct fields to default values */
-  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
-  I2C_InitStruct->ClockSpeed      = 5000U;
-  I2C_InitStruct->DutyCycle       = LL_I2C_DUTYCYCLE_2;
-  I2C_InitStruct->OwnAddress1     = 0U;
-  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
-  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_opamp.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_opamp.c
deleted file mode 100644
index 55699ea1d30..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_opamp.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_opamp.c
-  * @author  MCD Application Team
-  * @brief   OPAMP LL module driver
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_opamp.h"
-
-#ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
-#else
-  #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) 
-
-/** @addtogroup OPAMP_LL OPAMP
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup OPAMP_LL_Private_Macros
-  * @{
-  */
-
-/* Check of parameters for configuration of OPAMP hierarchical scope:         */
-/* OPAMP instance.                                                            */
-
-#define IS_LL_OPAMP_POWER_MODE(__POWER_MODE__)                                 \
-  (   ((__POWER_MODE__) == LL_OPAMP_POWERMODE_NORMAL)                          \
-   || ((__POWER_MODE__) == LL_OPAMP_POWERMODE_LOWPOWER))
-
-#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__)                       \
-  (   ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE)                      \
-   || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER)                        \
-  )
-
-/* Note: Comparator non-inverting inputs parameters are different             */
-/*       depending on OPAMP instance.                                         */
-#if defined(OPAMP3)
-#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)        \
-  (((__OPAMPX__) == OPAMP1)                                                       \
-    ? (                                                                           \
-          ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)              \
-       || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1)            \
-      )                                                                           \
-      :                                                                           \
-      (((__OPAMPX__) == OPAMP2)                                                   \
-        ? (                                                                       \
-              ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)          \
-           || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1)        \
-           || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH2)        \
-          )                                                                       \
-          :                                                                       \
-          (                                                                       \
-              ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)          \
-           || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH2_OPAMP3) \
-          )                                                                       \
-      )                                                                           \
-  )
-#else
-#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__)     \
-  (((__OPAMPX__) == OPAMP1)                                                    \
-    ? (                                                                        \
-          ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)           \
-       || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1)         \
-      )                                                                        \
-      :                                                                        \
-      (                                                                        \
-          ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0)           \
-       || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1)         \
-       || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH2)         \
-      )                                                                        \
-  )
-#endif
-
-/* Note: Comparator non-inverting inputs parameters are the same on all       */
-/*       OPAMP instances.                                                     */
-/*       However, comparator instance kept as macro parameter for             */
-/*       compatibility with other STM32 families.                             */
-#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__)           \
-  (   ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0)                     \
-   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1)                     \
-   || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO)              \
-  )
-
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMP_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup OPAMP_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize registers of the selected OPAMP instance
-  *         to their default reset values.
-  * @param  OPAMPx OPAMP instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: OPAMP registers are de-initialized
-  *          - ERROR: OPAMP registers are not de-initialized
-  */
-ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
-{
-  ErrorStatus status = SUCCESS;
-  
-  /* Check the parameters */
-  assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
-  
-  MODIFY_REG(OPAMP->CSR,
-               (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1LPM) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-             | (OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx)
-             | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx)) ,
-             (OPAMP_CSR_OPA1PD) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-            );
-  return status;
-}
-
-/**
-  * @brief  Initialize some features of OPAMP instance.
-  * @note   This function reset bit of calibration mode to ensure
-  *         to be in functional mode, in order to have OPAMP parameters
-  *         (inputs selection, ...) set with the corresponding OPAMP mode
-  *         to be effective.
-  * @note   This function configures features of the selected OPAMP instance.
-  *         Some features are also available at scope OPAMP common instance
-  *         (common to several OPAMP instances).
-  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.
-  * @param  OPAMPx OPAMP instance
-  * @param  OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: OPAMP registers are initialized
-  *          - ERROR: OPAMP registers are not initialized
-  */
-ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
-  assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode));
-  assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
-  assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
-  
-  /* Note: OPAMP inverting input can be used with OPAMP in mode standalone.   */
-  /*       Otherwise (OPAMP in mode follower), OPAMP inverting input is       */
-  /*       not used (not connected to GPIO pin).                              */
-  if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
-  {
-    assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
-  }
-  
-  /* Configuration of OPAMP instance :                                        */
-  /*  - PowerMode                                                             */
-  /*  - Functional mode                                                       */
-  /*  - Input non-inverting                                                   */
-  /*  - Input inverting                                                       */
-  /* Note: Bits OPAMP_CSR_OPAxCAL_y reset to ensure to be in functional mode  */
-  if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
-  {
-    MODIFY_REG(OPAMP->CSR,
-               ((
-                   OPAMP_CSR_OPA1LPM
-                 | OPAMP_CSR_S3SEL1
-                 | OPAMP_CSR_OPA1CAL_H
-                 | OPAMP_CSR_OPA1CAL_L
-                 | OPAMP_CSR_S5SEL1
-                 | OPAMP_CSR_S6SEL1
-                 | OPAMP_CSR_S4SEL1
-                ) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-               )
-               | ((OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx))
-               | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-              ,
-               ((
-                   (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
-                 | OPAMP_InitStruct->FunctionalMode
-                 | OPAMP_InitStruct->InputNonInverting
-                 | (OPAMP_InitStruct->InputInverting & OPAMP_CSR_S4SEL1)
-                ) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-               )
-               | ((OPAMP_InitStruct->InputInverting & OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx))
-               | ((OPAMP_InitStruct->InputNonInverting & OPAMP_CSR_S7SEL2) * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-              );
-  }
-  else
-  {
-    MODIFY_REG(OPAMP->CSR,
-               ((
-                   OPAMP_CSR_OPA1LPM
-                 | OPAMP_CSR_OPA1CAL_H
-                 | OPAMP_CSR_OPA1CAL_L
-                 | OPAMP_CSR_S5SEL1
-                 | OPAMP_CSR_S6SEL1
-                 | OPAMP_CSR_S4SEL1
-                ) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-               )
-               | ((OPAMP_CSR_ANAWSEL1) << __OPAMP_INSTANCE_DECIMAL(OPAMPx))
-               | (OPAMP_CSR_S7SEL2 * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-              ,
-               ((
-                   (OPAMP_InitStruct->PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)
-                 | OPAMP_InitStruct->FunctionalMode
-                 | OPAMP_InitStruct->InputNonInverting
-                 | OPAMP_CSR_S3SEL1
-                ) << __OPAMP_INSTANCE_BITOFFSET(OPAMPx)
-               )
-               | ((OPAMP_InitStruct->InputNonInverting & OPAMP_CSR_S7SEL2) * __OPAMP_IS_INSTANCE_OPAMP2(OPAMPx))
-              );
-  }
-  return SUCCESS;
-}
-
-/**
-  * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
-  * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
-{
-  /* Set OPAMP_InitStruct fields to default values */
-  OPAMP_InitStruct->PowerMode         = LL_OPAMP_POWERMODE_NORMAL;
-  OPAMP_InitStruct->FunctionalMode    = LL_OPAMP_MODE_FOLLOWER;
-  OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
-  /* Note: Parameter discarded if OPAMP in functional mode follower,          */
-  /*       set anyway to its default value.                                   */
-  OPAMP_InitStruct->InputInverting    = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* OPAMP1 || OPAMP2 || OPAMP3 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_pwr.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_pwr.c
deleted file mode 100644
index 75026243eee..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_pwr.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_pwr.h"
-#include "stm32l1xx_ll_bus.h"
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup PWR_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the PWR registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PWR registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_PWR_DeInit(void)
-{
-  /* Force reset of PWR clock */
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  /* Release reset of PWR clock */
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined(PWR) */
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rcc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rcc.c
deleted file mode 100644
index 8faee390f56..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rcc.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_rcc.h"
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
-  * @{
-  */
-static uint32_t RCC_GetSystemClockFreq(void);
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Reset the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *         - MSI  ON and used as system clock source
-  *         - HSE, HSI and PLL OFF
-  *         - AHB, APB1 and APB2 prescaler set to 1.
-  *         - CSS, MCO OFF
-  *         - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *         - Peripheral clocks
-  *         - LSI, LSE and RTC clocks
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RCC registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_RCC_DeInit(void)
-{
-  __IO uint32_t vl_mask;
-
-  /* Set MSION bit */
-  LL_RCC_MSI_Enable();
-
-  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
-  while (LL_RCC_MSI_IsReady() == 0U)
-  {
-    __NOP();
-  }
-
-  /* Set MSIRANGE default value */
-  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
-  /* Set MSITRIM bits to the reset value*/
-  LL_RCC_MSI_SetCalibTrimming(0U);
-
-  /* Set HSITRIM bits to the reset value*/
-  LL_RCC_HSI_SetCalibTrimming(0x10U);
-
-  /* Reset SW, HPRE, PPRE and MCOSEL bits */
-  vl_mask = 0xFFFFFFFFU;
-  CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
-  LL_RCC_WriteReg(CFGR, vl_mask);
-
-  /* Read CR register */
-  vl_mask = LL_RCC_ReadReg(CR);
-
-  /* Reset HSION, HSEON, CSSON, PLLON bits */
-  CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION));
-  LL_RCC_WriteReg(CR, vl_mask);
-
-  /* Reset HSEBYP bit */
-  LL_RCC_HSE_DisableBypass();
-
-  /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */
-  while(LL_RCC_PLL_IsReady() != 0U) {};
-
-  /* Reset CFGR register */
-  LL_RCC_WriteReg(CFGR, 0x00000000U);
-
-  /* Disable all interrupts */
-  LL_RCC_WriteReg(CIR, 0x00000000U);
-
-  /* Clear pending flags */
-#if defined(RCC_LSECSS_SUPPORT)
-  vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \
-             LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_LSECSSC | LL_RCC_CIR_CSSC);
-#else
-  vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | \
-             LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_MSIRDYC | LL_RCC_CIR_CSSC);
-#endif /* RCC_LSECSS_SUPPORT */
-  LL_RCC_WriteReg(CIR, vl_mask);
-
-  /* Clear reset flags */
-  LL_RCC_ClearResetFlags();
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
-  *         and different peripheral clocks available on the device.
-  * @note   If SYSCLK source is MSI, function returns values based on MSI clock(*)
-  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
-  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
-  * @note   If SYSCLK source is PLL, function returns values based on
-  *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
-  * @note   (*) MSI clock depends on the selected MSI range but the real value
-  *             may vary depending on the variations in voltage and temperature.
-  * @note   (**) HSI_VALUE is a defined constant but the real value may vary
-  *              depending on the variations in voltage and temperature.
-  * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
-  *               HSE_VALUE is same as the real frequency of the crystal used.
-  *               Otherwise, this function may have wrong result.
-  * @note   The result of this function could be incorrect when using fractional
-  *         value for HSE crystal.
-  * @note   This function can be used by the user application to compute the
-  *         baud-rate for the communication peripherals or configure other parameters.
-  * @{
-  */
-
-/**
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
-  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
-  *         must be called to update structure fields. Otherwise, any
-  *         configuration based on this function will be incorrect.
-  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
-  * @retval None
-  */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
-  /* Get SYSCLK frequency */
-  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
-  /* PCLK1 clock frequency */
-  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-
-  /* PCLK2 clock frequency */
-  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Return SYSTEM clock frequency
-  * @retval SYSTEM clock frequency (in Hz)
-  */
-static uint32_t RCC_GetSystemClockFreq(void)
-{
-  uint32_t frequency;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (LL_RCC_GetSysClkSource())
-  {
-    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
-      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
-      frequency = HSI_VALUE;
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
-      frequency = HSE_VALUE;
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
-      frequency = RCC_PLL_GetFreqDomain_SYS();
-      break;
-
-    default:
-      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
-      break;
-  }
-
-  return frequency;
-}
-
-/**
-  * @brief  Return HCLK clock frequency
-  * @param  SYSCLK_Frequency SYSCLK clock frequency
-  * @retval HCLK clock frequency (in Hz)
-  */
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
-  /* HCLK clock frequency */
-  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
-  * @brief  Return PCLK1 clock frequency
-  * @param  HCLK_Frequency HCLK clock frequency
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
-  /* PCLK1 clock frequency */
-  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-
-/**
-  * @brief  Return PCLK2 clock frequency
-  * @param  HCLK_Frequency HCLK clock frequency
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
-{
-  /* PCLK2 clock frequency */
-  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
-}
-
-/**
-  * @brief  Return PLL clock frequency used for system domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
-  uint32_t pllsource, pllinputfreq;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
-
-  /* Get PLL source */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSI:       /* HSI used as PLL clock source */
-      pllinputfreq = HSI_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rtc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rtc.c
deleted file mode 100644
index bf1078f1013..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_rtc.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_rtc.c
-  * @author  MCD Application Team
-  * @brief   RTC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_rtc.h"
-#include "stm32l1xx_ll_cortex.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined(RTC)
-
-/** @addtogroup RTC_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Constants
-  * @{
-  */
-/* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
-#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
-
-/* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
-                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
-
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
-
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
-
-#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
-                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))
-
-#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
-                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
-
-#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
-#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
-#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
-#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
-
-#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
-                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-
-#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
-
-#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
-
-#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
-
-#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
-                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
-
-#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
-                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
-
-
-#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
-                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
-                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
-
-
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-Initializes the RTC registers to their default reset values.
-  * @note   This function does not reset the RTC Clock source and RTC Backup Data
-  *         registers.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are de-initialized
-  *          - ERROR: RTC registers are not de-initialized
-  */
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Reset TR, DR and CR registers */
-    LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
-#if defined(RTC_WAKEUP_SUPPORT)
-    LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
-#endif /* RTC_WAKEUP_SUPPORT */
-    LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
-    /* Reset All CR bits except CR[2:0] */
-#if defined(RTC_WAKEUP_SUPPORT)
-    LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
-#else
-    LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
-#endif /* RTC_WAKEUP_SUPPORT */
-    LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
-    LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
-    LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
-#if defined(RTC_SHIFTR_ADD1S)
-    LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
-#endif /* RTC_SHIFTR_ADD1S */
-#if defined(RTC_SMOOTHCALIB_SUPPORT)
-    LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
-#endif /* RTC_SMOOTHCALIB_SUPPORT */
-#if defined(RTC_SUBSECOND_SUPPORT)
-    LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
-    LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
-#endif /* RTC_SUBSECOND_SUPPORT */
-
-    /* Reset ISR register and exit initialization mode */
-    LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
-
-    /* Reset Tamper and alternate functions configuration register */
-    LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
-
-    /* Wait till the RTC RSF flag is set */
-    status = LL_RTC_WaitForSynchro(RTCx);
-  }
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the RTC registers according to the specified parameters
-  *         in RTC_InitStruct.
-  * @param  RTCx RTC Instance
-  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
-  *         the configuration information for the RTC peripheral.
-  * @note   The RTC Prescaler register is write protected and can be written in
-  *         initialization mode only.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are initialized
-  *          - ERROR: RTC registers are not initialized
-  */
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
-  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
-  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Set Hour Format */
-    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
-
-    /* Configure Synchronous and Asynchronous prescaler factor */
-    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
-    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-    status = SUCCESS;
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
-  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
-{
-  /* Set RTC_InitStruct fields to default values */
-  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
-  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
-  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
-}
-
-/**
-  * @brief  Set the RTC current time.
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
-  *                        the time configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Time register is configured
-  *          - ERROR: RTC Time register is not configured
-  */
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
-    }
-    else
-    {
-      RTC_TimeStruct->TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
-    }
-    else
-    {
-      RTC_TimeStruct->TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
-    }
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Check the input parameters format */
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
-                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
-    }
-    else
-    {
-      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
-    }
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-#if defined(RTC_CR_BYPSHAD)
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
-    {
-      status = LL_RTC_WaitForSynchro(RTCx);
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-#else
-    status = SUCCESS;
-#endif /* RTC_CR_BYPSHAD */
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
-  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
-  /* Time = 00h:00min:00sec */
-  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
-  RTC_TimeStruct->Hours      = 0U;
-  RTC_TimeStruct->Minutes    = 0U;
-  RTC_TimeStruct->Seconds    = 0U;
-}
-
-/**
-  * @brief  Set the RTC current date.
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
-  *                         the date configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Day register is configured
-  *          - ERROR: RTC Day register is not configured
-  */
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
-  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
-  {
-    RTC_DateStruct->Month = ((RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU);
-  }
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
-    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
-    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
-  }
-  else
-  {
-    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
-    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
-    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
-  }
-  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Set Initialization mode */
-  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
-  {
-    /* Check the input parameters format */
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
-    }
-    else
-    {
-      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
-                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
-    }
-
-    /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTCx);
-
-#if defined(RTC_CR_BYPSHAD)
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
-    {
-      status = LL_RTC_WaitForSynchro(RTCx);
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-#else
-    status = SUCCESS;
-#endif /* RTC_CR_BYPSHAD */
-  }
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
-  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
-{
-  /* Monday, January 01 xx00 */
-  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
-  RTC_DateStruct->Day     = 1U;
-  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
-  RTC_DateStruct->Year    = 0U;
-}
-
-/**
-  * @brief  Set the RTC Alarm A.
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
-  *                         contains the alarm configuration parameters.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ALARMA registers are configured
-  *          - ERROR: ALARMA registers are not configured
-  */
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
-  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Select weekday selection */
-  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
-  {
-    /* Set the date for ALARM */
-    LL_RTC_ALMA_DisableWeekday(RTCx);
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-    }
-    else
-    {
-      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    /* Set the week day for ALARM */
-    LL_RTC_ALMA_EnableWeekday(RTCx);
-    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-  }
-
-  /* Configure the Alarm register */
-  if (RTC_Format != LL_RTC_FORMAT_BIN)
-  {
-    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
-                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
-  }
-  else
-  {
-    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
-  }
-  /* Set ALARM mask */
-  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the RTC Alarm B.
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (@ref LL_RTC_ALMB_Disable function).
-  * @param  RTCx RTC Instance
-  * @param  RTC_Format This parameter can be one of the following values:
-  *         @arg @ref LL_RTC_FORMAT_BIN
-  *         @arg @ref LL_RTC_FORMAT_BCD
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
-  *                         contains the alarm configuration parameters.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: ALARMB registers are configured
-  *          - ERROR: ALARMB registers are not configured
-  */
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
-  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
-
-  if (RTC_Format == LL_RTC_FORMAT_BIN)
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
-    }
-    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
-    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
-    {
-      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
-    }
-    else
-    {
-      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
-      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
-    }
-
-    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
-    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
-
-    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-    else
-    {
-      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
-    }
-  }
-
-  /* Disable the write protection for RTC registers */
-  LL_RTC_DisableWriteProtection(RTCx);
-
-  /* Select weekday selection */
-  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
-  {
-    /* Set the date for ALARM */
-    LL_RTC_ALMB_DisableWeekday(RTCx);
-    if (RTC_Format != LL_RTC_FORMAT_BIN)
-    {
-      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-    }
-    else
-    {
-      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    /* Set the week day for ALARM */
-    LL_RTC_ALMB_EnableWeekday(RTCx);
-    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
-  }
-
-  /* Configure the Alarm register */
-  if (RTC_Format != LL_RTC_FORMAT_BIN)
-  {
-    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
-                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
-  }
-  else
-  {
-    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
-                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
-  }
-  /* Set ALARM mask */
-  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
-
-  /* Enable the write protection for RTC registers */
-  LL_RTC_EnableWriteProtection(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
-  *         Day = 1st day of the month/Mask = all fields are masked).
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Alarm Time Settings : Time = 00h:00mn:00sec */
-  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
-  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
-  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
-  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
-
-  /* Alarm Day Settings : Day = 1st day of the month */
-  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
-  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
-
-  /* Alarm Masks Settings : Mask =  all fields are not masked */
-  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
-}
-
-/**
-  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
-  *         Day = 1st day of the month/Mask = all fields are masked).
-  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
-  * @retval None
-  */
-void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
-  /* Alarm Time Settings : Time = 00h:00mn:00sec */
-  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
-  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
-  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
-  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
-
-  /* Alarm Day Settings : Day = 1st day of the month */
-  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
-  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
-
-  /* Alarm Masks Settings : Mask =  all fields are not masked */
-  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
-}
-
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC is in Init mode
-  *          - ERROR: RTC is not in Init mode
-  */
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
-{
-  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
-  ErrorStatus status = SUCCESS;
-  uint32_t tmp;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Check if the Initialization mode is set */
-  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
-  {
-    /* Set the Initialization mode */
-    LL_RTC_EnableInitMode(RTCx);
-
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
-    while ((timeout != 0U) && (tmp != 1U))
-    {
-      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
-      {
-        timeout --;
-      }
-      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
-      if (timeout == 0U)
-      {
-        status = ERROR;
-      }
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Exit the RTC Initialization mode.
-  * @note   When the initialization sequence is complete, the calendar restarts
-  *         counting after 4 RTCCLK cycles.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC exited from in Init mode
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
-{
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Disable initialization mode */
-  LL_RTC_DisableInitMode(RTCx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the
-  *         @ref LL_RTC_DisableWriteProtection before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar
-  *         initialization, calendar update or after wakeup from low power modes
-  *         the software must first clear the RSF flag.
-  *         The software must then wait until it is set again before reading
-  *         the calendar, which means that the calendar registers have been
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
-  * @param  RTCx RTC Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are synchronised
-  *          - ERROR: RTC registers are not synchronised
-  */
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
-{
-  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
-  ErrorStatus status = SUCCESS;
-  uint32_t tmp;
-
-  /* Check the parameter */
-  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
-  /* Clear RSF flag */
-  LL_RTC_ClearFlag_RS(RTCx);
-
-  /* Wait the registers to be synchronised */
-  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-  while ((timeout != 0U) && (tmp != 1U))
-  {
-    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
-    {
-      timeout--;
-    }
-    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
-    if (timeout == 0U)
-    {
-      status = ERROR;
-    }
-  }
-
-  return (status);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RTC) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c
deleted file mode 100644
index a3b98477eac..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_sdmmc.c
+++ /dev/null
@@ -1,1547 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_sdmmc.c
-  * @author  MCD Application Team
-  * @brief   SDMMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the SDMMC peripheral:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                       ##### SDMMC peripheral features #####
-  ==============================================================================        
-    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
-         devices.
-    
-    [..] The SDMMC features include the following:
-         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
-             for three different databus modes: 1-bit (default), 4-bit and 8-bit
-         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
-         (+) Full compliance with SD Memory Card Specifications Version 2.0
-         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
-             different data bus modes: 1-bit (default) and 4-bit
-         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
-             Rev1.1)
-         (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers
-   
-                           ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a considered as a driver of service for external devices drivers 
-      that interfaces with the SDMMC peripheral.
-      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
-      is used in the device's driver to perform SDMMC operations and functionalities.
-   
-      This driver is almost transparent for the final user, it is only used to implement other
-      functionalities of the external device.
-   
-    [..]
-      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
-          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
-          PLL is well configured.
-          The SDMMC peripheral uses two clock signals:
-          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
-          (++) APB2 bus clock (PCLK2)
-       
-          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
-  
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
-          peripheral.
-
-      (+) Enable the Power ON State using the SDIO_PowerState_ON() 
-          function and disable it using the function SDIO_PowerState_OFF().
-                
-      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
-  
-      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() 
-          and __SDIO_DISABLE_IT() if you need to use interrupt mode. 
-  
-      (+) When using the DMA mode 
-          (++) Configure the DMA in the MSP layer of the external device
-          (++) Active the needed channel Request 
-          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
-               __SDIO_DMA_DISABLE().
-  
-      (+) To control the CPSM (Command Path State Machine) and send 
-          commands to the card use the SDIO_SendCommand(), 
-          SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
-          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
-          to the selected command to be sent.
-          The parameters that should be filled are:
-           (++) Command Argument
-           (++) Command Index
-           (++) Command Response type
-           (++) Command Wait
-           (++) CPSM Status (Enable or Disable).
-  
-          -@@- To check if the command is well received, read the SDIO_CMDRESP
-              register using the SDIO_GetCommandResponse().
-              The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
-              SDIO_GetResponse() function.
-  
-      (+) To control the DPSM (Data Path State Machine) and send/receive 
-           data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
-          SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
-  
-    *** Read Operations ***
-    =======================
-    [..]
-      (#) First, user has to fill the data structure (pointer to
-          SDIO_DataInitTypeDef) according to the selected data type to be received.
-          The parameters that should be filled are:
-           (++) Data TimeOut
-           (++) Data Length
-           (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDMMC)
-           (++) Data Transfer mode
-           (++) DPSM Status (Enable or Disable)
-                                     
-      (#) Configure the SDMMC resources to receive the data from the card
-          according to selected transfer mode (Refer to Step 8, 9 and 10).
-  
-      (#) Send the selected Read command (refer to step 11).
-                    
-      (#) Use the SDIO flags/interrupts to check the transfer status.
-  
-    *** Write Operations ***
-    ========================
-    [..]
-     (#) First, user has to fill the data structure (pointer to
-         SDIO_DataInitTypeDef) according to the selected data type to be received.
-         The parameters that should be filled are:
-          (++) Data TimeOut
-          (++) Data Length
-          (++) Data Block size
-          (++) Data Transfer direction:  should be to card (To CARD)
-          (++) Data Transfer mode
-          (++) DPSM Status (Enable or Disable)
-  
-     (#) Configure the SDMMC resources to send the data to the card according to 
-         selected transfer mode.
-                     
-     (#) Send the selected Write command.
-                    
-     (#) Use the SDIO flags/interrupts to check the transfer status.
-       
-    *** Command management operations ***
-    =====================================
-    [..]
-     (#) The commands used for Read/Write/Erase operations are managed in 
-         separate functions. 
-         Each function allows to send the needed command with the related argument,
-         then check the response.
-         By the same approach, you could implement a command and check the response.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#if defined(SDIO)
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
-  * @brief Low layer module for SD
-  * @{
-  */
-
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
-static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SDMMC according to the specified
-  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @param  Init: SDMMC initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
-  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); 
-  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
-  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
-  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
-  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
-  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
-  
-  /* Set SDMMC configuration parameters */
-  tmpreg |= (Init.ClockEdge           |\
-             Init.ClockBypass         |\
-             Init.ClockPowerSave      |\
-             Init.BusWide             |\
-             Init.HardwareFlowControl |\
-             Init.ClockDiv
-             ); 
-  
-  /* Write to SDMMC CLKCR */
-  MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
-
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### I/O operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the SDMMC data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
-{
-  /* Read data from Rx FIFO */ 
-  return (SDIOx->FIFO);
-}
-
-/**
-  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @param  pWriteData: pointer to data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
-{ 
-  /* Write data to FIFO */ 
-  SDIOx->FIFO = *pWriteData;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the SDMMC data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set SDMMC Power state to ON. 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
-{  
-  /* Set power state to ON */ 
-  SDIOx->POWER = SDIO_POWER_PWRCTRL;
-
-  /* 1ms: required power up waiting time before starting the SD initialization
-  sequence */
-  HAL_Delay(2);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set SDMMC Power state to OFF. 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
-{
-  /* Set power state to OFF */
-  SDIOx->POWER = (uint32_t)0x00000000;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get SDMMC Power state. 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @retval Power status of the controller. The returned value can be one of the 
-  *         following values:
-  *            - 0x00: Power OFF
-  *            - 0x02: Power UP
-  *            - 0x03: Power ON 
-  */
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)  
-{
-  return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
-}
-
-/**
-  * @brief  Configure the SDMMC command path according to the specified parameters in
-  *         SDIO_CmdInitTypeDef structure and send the command 
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @param  Command: pointer to a SDIO_CmdInitTypeDef structure that contains 
-  *         the configuration information for the SDMMC command
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
-  assert_param(IS_SDIO_RESPONSE(Command->Response));
-  assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
-  assert_param(IS_SDIO_CPSM(Command->CPSM));
-
-  /* Set the SDMMC Argument value */
-  SDIOx->ARG = Command->Argument;
-
-  /* Set SDMMC command parameters */
-  tmpreg |= (uint32_t)(Command->CmdIndex         |\
-                       Command->Response         |\
-                       Command->WaitForInterrupt |\
-                       Command->CPSM);
-  
-  /* Write to SDMMC CMD register */
-  MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Return the command index of last command for which response received
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @retval Command index of the last command response received
-  */
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
-{
-  return (uint8_t)(SDIOx->RESPCMD);
-}
-
-
-/**
-  * @brief  Return the response received from the card for the last command
-  * @param  SDIOx: Pointer to SDMMC register base    
-  * @param  Response: Specifies the SDMMC response register. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_RESP1: Response Register 1
-  *            @arg SDIO_RESP2: Response Register 2
-  *            @arg SDIO_RESP3: Response Register 3
-  *            @arg SDIO_RESP4: Response Register 4  
-  * @retval The Corresponding response register value
-  */
-uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
-{
-  uint32_t tmp;
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_RESP(Response));
-  
-  /* Get the response */
-  tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;
-  
-  return (*(__IO uint32_t *) tmp);
-}  
-
-/**
-  * @brief  Configure the SDMMC data path according to the specified 
-  *         parameters in the SDIO_DataInitTypeDef.
-  * @param  SDIOx: Pointer to SDIO register base  
-  * @param  Data : pointer to a SDIO_DataInitTypeDef structure 
-  *         that contains the configuration information for the SDMMC data.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
-  assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
-  assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
-  assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
-  assert_param(IS_SDIO_DPSM(Data->DPSM));
-
-  /* Set the SDMMC Data TimeOut value */
-  SDIOx->DTIMER = Data->DataTimeOut;
-
-  /* Set the SDMMC DataLength value */
-  SDIOx->DLEN = Data->DataLength;
-
-  /* Set the SDMMC data configuration parameters */
-  tmpreg |= (uint32_t)(Data->DataBlockSize |\
-                       Data->TransferDir   |\
-                       Data->TransferMode  |\
-                       Data->DPSM);
-  
-  /* Write to SDMMC DCTRL */
-  MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Returns number of remaining data bytes to be transferred.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Number of remaining data bytes to be transferred
-  */
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->DCOUNT);
-}
-
-/**
-  * @brief  Get the FIFO data
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval Data received
-  */
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->FIFO);
-}
-
-/**
-  * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDIOx: Pointer to SDIO register base   
-  * @param  SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
-  *          This parameter can be:
-  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
-  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
-  * @retval None
-  */
-HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
-{
-  /* Check the parameters */
-  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
-  /* Set SDMMC read wait mode */
-  MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                   ##### Commands management functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the needed commands.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Send the Data Block Length command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Read Single Block command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Read Multi Block command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Write Single Block command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Write Multi Block command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Start Address Erase command for SD and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the End Address Erase command for SD and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Start Address Erase command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the End Address Erase command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Erase command and check the response
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Set Block Size for Card */ 
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Stop Transfer command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Select Deselect command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  addr: Address of the card to be selected  
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
-  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Go Idle State command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_NO;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdError(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Operating Condition command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp7(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Application command to verify that that the next command 
-  *         is an application specific com-mand rather than a standard command
-  *         and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  Argument: Command Argument 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  /* If there is a HAL_ERROR, it is a MMC card, else
-  it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the command asking the accessed card to send its operating 
-  *         condition register (OCR)
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  Argument: Command Argument
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp3(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Bus Width command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  BusWidth: BusWidth
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Send SCR command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD51 SD_APP_SEND_SCR */
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Send CID command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD2 ALL_SEND_CID */
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp2(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Send CSD command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  Argument: Command Argument
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD9 SEND_CSD */
-  sdmmc_cmdinit.Argument         = Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp2(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Send CSD command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  pRCA: Card RCA  
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD3 SD_CMD_SET_REL_ADDR */
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Status command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @param  Argument: Command Argument
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Send the Status register command and check the response.
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = 0U;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Sends host capacity support information and activates the card's 
-  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @parame Argument: Argument used for the command
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  sdmmc_cmdinit.Argument         = Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp3(SDIOx);
-
-  return errorstate;
-}
-
-/**
-  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
-  * @param  SDIOx: Pointer to SDIO register base 
-  * @parame Argument: Argument used for the command
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-  
-  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
-  /* CMD Response: R1 */
-  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-  
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/* Private function ----------------------------------------------------------*/  
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-    
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
-{
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The SDIO_CMDTIMEOUT is expressed in ms */
-  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    
-  }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
-  
-  /* Clear all the static flags */
-  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
-  
-  return SDMMC_ERROR_NONE;
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index  
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
-{
-  uint32_t response_r1;
-  uint32_t sta_reg;
-  
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The Timeout is expressed in ms */
-  uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    sta_reg = SDIOx->STA;
-  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
-         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
-    
-  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-    
-    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
-  }
-  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-    
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-  
-  /* Clear all the static flags */
-  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
-  {
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
-  
-  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
-  {
-    return SDMMC_ERROR_NONE;
-  }
-  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
-  }
-  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
-  {
-    return SDMMC_ERROR_ADDR_MISALIGNED;
-  }
-  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
-  {
-    return SDMMC_ERROR_BLOCK_LEN_ERR;
-  }
-  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
-  {
-    return SDMMC_ERROR_ERASE_SEQ_ERR;
-  }
-  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
-  {
-    return SDMMC_ERROR_BAD_ERASE_PARAM;
-  }
-  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
-  {
-    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
-  }
-  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
-  }
-  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
-  {
-    return SDMMC_ERROR_COM_CRC_FAILED;
-  }
-  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
-  {
-    return SDMMC_ERROR_ILLEGAL_CMD;
-  }
-  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
-  {
-    return SDMMC_ERROR_CARD_ECC_FAILED;
-  }
-  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
-  {
-    return SDMMC_ERROR_CC_ERR;
-  }
-  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
-  {
-    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
-  }
-  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
-  }
-  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
-  {
-    return SDMMC_ERROR_CID_CSD_OVERWRITE;
-  }
-  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
-  {
-    return SDMMC_ERROR_WP_ERASE_SKIP;
-  }
-  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
-  {
-    return SDMMC_ERROR_CARD_ECC_DISABLED;
-  }
-  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
-  {
-    return SDMMC_ERROR_ERASE_RESET;
-  }
-  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
-  {
-    return SDMMC_ERROR_AKE_SEQ_ERR;
-  }
-  else
-  {
-    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
-  }
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
-{
-  uint32_t sta_reg;
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The SDIO_CMDTIMEOUT is expressed in ms */
-  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    sta_reg = SDIOx->STA;
-  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
-         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
-    
-  if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-    
-    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
-  }
-  else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-    
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  else
-  {
-    /* No error flag set */
-    /* Clear all the static flags */
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
-  }
-
-  return SDMMC_ERROR_NONE;
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
-{
-  uint32_t sta_reg;
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The SDIO_CMDTIMEOUT is expressed in ms */
-  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    sta_reg = SDIOx->STA;
-  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
-         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
-    
-  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-    
-    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
-  }
-  else
-  {  
-    /* Clear all the static flags */
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
-  }
-  
-  return SDMMC_ERROR_NONE;
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
-  *         address RCA   
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  uint32_t response_r1;
-  uint32_t sta_reg;
-
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The SDIO_CMDTIMEOUT is expressed in ms */
-  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    sta_reg = SDIOx->STA;
-  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
-         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
-    
-  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-    
-    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
-  }
-  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
-  {
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-    
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
-  {
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  
-  /* Clear all the static flags */
-  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
-  
-  /* We have received response, retrieve it.  */
-  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
-  
-  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
-  {
-    *pRCA = (uint16_t) (response_r1 >> 16);
-    
-    return SDMMC_ERROR_NONE;
-  }
-  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
-  {
-    return SDMMC_ERROR_ILLEGAL_CMD;
-  }
-  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
-  {
-    return SDMMC_ERROR_COM_CRC_FAILED;
-  }
-  else
-  {
-    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
-  }
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
-{
-  uint32_t sta_reg;
-  /* 8 is the number of required instructions cycles for the below loop statement.
-  The SDIO_CMDTIMEOUT is expressed in ms */
-  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-  
-  do
-  {
-    if (count-- == 0U)
-    {
-      return SDMMC_ERROR_TIMEOUT;
-    }
-    sta_reg = SDIOx->STA;
-  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
-         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
-    
-  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
-  {
-    /* Card is SD V2.0 compliant */
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-    
-    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
-  }
-  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
-  {
-    /* Card is SD V2.0 compliant */
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-    
-    return SDMMC_ERROR_CMD_CRC_FAIL;
-  }
-  else
-  {
-    /* Nothing to do */
-  }
-  
-  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
-  {
-    /* Card is SD V2.0 compliant */
-    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
-  }
-  
-  return SDMMC_ERROR_NONE;
-  
-}
-
-/**
-  * @brief  Send the Send EXT_CSD command and check the response.
-  * @param  SDIOx: Pointer to SDMMC register base
-  * @param  Argument: Command Argument
-  * @retval HAL status
-  */
-uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
-  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
-  uint32_t errorstate;
-
-  /* Send CMD9 SEND_CSD */
-  sdmmc_cmdinit.Argument         = Argument;
-  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
-  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
-  /* Check for error conditions */
-  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT);
-
-  return errorstate;
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* SDIO */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_spi.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_spi.c
deleted file mode 100644
index 128ee620b55..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_spi.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_spi.c
-  * @author  MCD Application Team
-  * @brief   SPI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_spi.h"
-#include "stm32l1xx_ll_bus.h"
-#include "stm32l1xx_ll_rcc.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @addtogroup SPI_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
-  * @{
-  */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
-                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
-                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
-                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
-                                            SPI_CR1_BIDIMODE)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
-  * @{
-  */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
-                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
-                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
-                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
-                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
-                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
-                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
-  if (SPIx == SPI1)
-  {
-    /* Force reset of SPI clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    /* Release reset of SPI clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    status = SUCCESS;
-  }
-#endif /* SPI1 */
-#if defined(SPI2)
-  if (SPIx == SPI2)
-  {
-    /* Force reset of SPI clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    /* Release reset of SPI clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    status = SUCCESS;
-  }
-#endif /* SPI2 */
-#if defined(SPI3)
-  if (SPIx == SPI3)
-  {
-    /* Force reset of SPI clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
-
-    /* Release reset of SPI clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
-
-    status = SUCCESS;
-  }
-#endif /* SPI3 */
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
-  */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the SPI Instance SPIx*/
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-  /* Check the SPI parameters from SPI_InitStruct*/
-  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
-  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
-  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
-  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
-  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
-  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
-  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
-  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
-  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
-  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx CR1 Configuration ------------------------
-     * Configure SPIx CR1 with parameters:
-     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
-     * - Master/Slave Mode:  SPI_CR1_MSTR bit
-     * - DataWidth:          SPI_CR1_DFF bit
-     * - ClockPolarity:      SPI_CR1_CPOL bit
-     * - ClockPhase:         SPI_CR1_CPHA bit
-     * - NSS management:     SPI_CR1_SSM bit
-     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
-     * - BitOrder:           SPI_CR1_LSBFIRST bit
-     * - CRCCalculation:     SPI_CR1_CRCEN bit
-     */
-    MODIFY_REG(SPIx->CR1,
-               SPI_CR1_CLEAR_MASK,
-               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
-               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
-               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
-               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
-    /*---------------------------- SPIx CR2 Configuration ------------------------
-     * Configure SPIx CR2 with parameters:
-     * - NSS management:     SSOE bit
-     */
-    MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
-
-    /*---------------------------- SPIx CRCPR Configuration ----------------------
-     * Configure SPIx CRCPR with parameters:
-     * - CRCPoly:            CRCPOLY[15:0] bits
-     */
-    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
-    {
-      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
-      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
-    }
-    status = SUCCESS;
-  }
-
-#if defined (SPI_I2S_SUPPORT)
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * whose fields will be set to default values.
-  * @retval None
-  */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  /* Set SPI_InitStruct fields to default values */
-  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
-  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
-  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
-  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
-  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
-  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
-  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
-  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
-  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
-  SPI_InitStruct->CRCPoly           = 7U;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
-  * @{
-  */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
-                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
-                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK               0x0002U
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
-  * @{
-  */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
-                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
-                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
-                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
-                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
-                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
-                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI/I2S registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_DeInit(SPIx);
-}
-
-/**
-  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are Initialized
-  *          - ERROR: SPI registers are not Initialized
-  */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  uint32_t i2sdiv = 2U;
-  uint32_t i2sodd = 0U;
-  uint32_t packetlength = 1U;
-  uint32_t tmp;
-  LL_RCC_ClocksTypeDef rcc_clocks;
-  uint32_t sourceclock;
-  ErrorStatus status = ERROR;
-
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
-  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
-  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
-  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
-  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
-  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
-  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx I2SCFGR Configuration --------------------
-     * Configure SPIx I2SCFGR with parameters:
-     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
-     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
-     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
-     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
-     */
-
-    /* Write to SPIx I2SCFGR */
-    MODIFY_REG(SPIx->I2SCFGR,
-               I2S_I2SCFGR_CLEAR_MASK,
-               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
-               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
-               SPI_I2SCFGR_I2SMOD);
-
-    /*---------------------------- SPIx I2SPR Configuration ----------------------
-     * Configure SPIx I2SPR with parameters:
-     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
-     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
-     */
-
-    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
-     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
-     */
-    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
-    {
-      /* Check the frame length (For the Prescaler computing)
-       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
-       */
-      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
-      {
-        /* Packet length is 32 bits */
-        packetlength = 2U;
-      }
-
-      /* I2S Clock source is System clock: Get System Clock frequency */
-      LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
-      /* Get the source clock value: based on System Clock value */
-      sourceclock = rcc_clocks.SYSCLK_Frequency;
-
-      /* Compute the Real divider depending on the MCLK output state with a floating point */
-      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
-      {
-        /* MCLK output is enabled */
-        tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-      else
-      {
-        /* MCLK output is disabled */
-        tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-
-      /* Remove the floating point */
-      tmp = tmp / 10U;
-
-      /* Check the parity of the divider */
-      i2sodd = (tmp & (uint16_t)0x0001U);
-
-      /* Compute the i2sdiv prescaler */
-      i2sdiv = ((tmp - i2sodd) / 2U);
-
-      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-      i2sodd = (i2sodd << 8U);
-    }
-
-    /* Test if the divider is 1 or 0 or greater than 0xFF */
-    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-    {
-      /* Set the default values */
-      i2sdiv = 2U;
-      i2sodd = 0U;
-    }
-
-    /* Write to SPIx I2SPR register the computed value */
-    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
-    status = SUCCESS;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  *         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  /*--------------- Reset I2S init structure parameters values -----------------*/
-  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
-  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
-  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
-  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
-  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
-  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
-}
-
-/**
-  * @brief  Set linear and parity prescaler.
-  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
-  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
-  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
-  /* Write to SPIx I2SPR */
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_tim.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_tim.c
deleted file mode 100644
index 0480ac51bf4..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_tim.c
+++ /dev/null
@@ -1,877 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_tim.c
-  * @author  MCD Application Team
-  * @brief   TIM LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_tim.h"
-#include "stm32l1xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
-
-/** @addtogroup TIM_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
-                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
-                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
-  * @{
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Set TIMx registers to their reset values.
-  * @param  TIMx Timer instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: invalid TIMx instance
-  */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
-  ErrorStatus result = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-
-  if (TIMx == TIM2)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
-  }
-#if defined(TIM3)
-  else if (TIMx == TIM3)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
-  }
-#endif /* TIM3 */
-#if defined(TIM4)
-  else if (TIMx == TIM4)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
-  }
-#endif /* TIM4 */
-#if defined(TIM5)
-  else if (TIMx == TIM5)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
-  }
-#endif /* TIM5 */
-#if defined(TIM6)
-  else if (TIMx == TIM6)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
-  }
-#endif /* TIM6 */
-#if defined(TIM7)
-  else if (TIMx == TIM7)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
-  }
-#endif /* TIM7 */
-#if defined(TIM9)
-  else if (TIMx == TIM9)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
-  }
-#endif /* TIM9 */
-#if defined(TIM10)
-  else if (TIMx == TIM10)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
-  }
-#endif /* TIM10 */
-#if defined(TIM11)
-  else if (TIMx == TIM11)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
-  }
-#endif /* TIM11 */
-  else
-  {
-    result = ERROR;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the time base unit configuration data structure
-  *         to their default values.
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
-  * @retval None
-  */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
-  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
-  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
-  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
-}
-
-/**
-  * @brief  Configure the TIMx time base unit.
-  * @param  TIMx Timer Instance
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
-  *         (TIMx time base unit configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  uint32_t tmpcr1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
-  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
-  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
-  }
-
-  /* Write to TIMx CR1 */
-  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
-  /* Set the Autoreload value */
-  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
-  /* Set the Prescaler value */
-  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter value (if applicable) immediately */
-  LL_TIM_GenerateEvent_UPDATE(TIMx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the fields of the TIMx output channel configuration data
-  *         structure to their default values.
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
-  *         (the output channel configuration data structure)
-  * @retval None
-  */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
-  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->CompareValue = 0x00000000U;
-  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
-}
-
-/**
-  * @brief  Configure the TIMx output channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
-  *         data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = OC1Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = OC2Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = OC3Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = OC4Config(TIMx, TIM_OC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the TIMx input channel configuration data
-  *         structure to their default values.
-  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
-  *         data structure)
-  * @retval None
-  */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the TIMx input channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
-  *         structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = IC1Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = IC2Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = IC3Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = IC4Config(TIMx, TIM_IC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Fills each TIM_EncoderInitStruct field with its default value
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
-  *         configuration data structure)
-  * @retval None
-  */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  /* Set the default configuration */
-  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
-  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
-  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the encoder interface of the timer instance.
-  * @param  TIMx Timer Instance
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
-  *         configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
-  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
-  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Configure TI1 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
-  /* Configure TI2 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
-  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
-  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
-  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Set encoder mode */
-  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
-  *  @brief   Private functions
-  * @{
-  */
-/**
-  * @brief  Configure the TIMx output channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
-  /* Set the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-
-/**
-  * @brief  Configure the TIMx input channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC1E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
-             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
-             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC3E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
-             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
-             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
-  return SUCCESS;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usart.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usart.c
deleted file mode 100644
index 297eca0b2aa..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usart.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_usart.c
-  * @author  MCD Application Team
-  * @brief   USART LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_usart.h"
-#include "stm32l1xx_ll_rcc.h"
-#include "stm32l1xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @addtogroup USART_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
-  * @{
-  */
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- *              divided by the smallest oversampling used on the USART (i.e. 8)    */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U)
-
-/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
-                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
-                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
-                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
-                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
-                                    || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
-                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
-                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
-                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
-                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
-                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
-                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
-                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
-                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
-                                      || ((__VALUE__) == LL_USART_STOPBITS_2))
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
-                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
-                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
-                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup USART_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize USART registers (Registers restored to their default values).
-  * @param  USARTx USART Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are de-initialized
-  *          - ERROR: USART registers are not de-initialized
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-
-  if (USARTx == USART1)
-  {
-    /* Force reset of USART clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
-
-    /* Release reset of USART clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
-  }
-  else if (USARTx == USART2)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
-  }
-  else if (USARTx == USART3)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
-  }
-#if defined(UART4)
-  else if (USARTx == UART4)
-  {
-    /* Force reset of UART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
-
-    /* Release reset of UART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
-  }
-#endif /* UART4 */
-#if defined(UART5)
-  else if (USARTx == UART5)
-  {
-    /* Force reset of UART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
-
-    /* Release reset of UART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
-  }
-#endif /* UART5 */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize USART registers according to the specified
-  *         parameters in USART_InitStruct.
-  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
-  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
-  * @param  USARTx USART Instance
-  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
-  *         that contains the configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
-  ErrorStatus status = ERROR;
-  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-  LL_RCC_ClocksTypeDef rcc_clocks;
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
-  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
-  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
-  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
-  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
-  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
-  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /*---------------------------- USART CR1 Configuration -----------------------
-     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
-     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
-     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
-     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
-     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
-     */
-    MODIFY_REG(USARTx->CR1,
-               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
-                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
-                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-
-    /*---------------------------- USART CR2 Configuration -----------------------
-     * Configure USARTx CR2 (Stop bits) with parameters:
-     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
-     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
-     */
-    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
-    /*---------------------------- USART CR3 Configuration -----------------------
-     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
-     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
-     */
-    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
-    /*---------------------------- USART BRR Configuration -----------------------
-     * Retrieve Clock frequency used for USART Peripheral
-     */
-    LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-    if (USARTx == USART1)
-    {
-      periphclk = rcc_clocks.PCLK2_Frequency;
-    }
-    else if (USARTx == USART2)
-    {
-      periphclk = rcc_clocks.PCLK1_Frequency;
-    }
-    else if (USARTx == USART3)
-    {
-      periphclk = rcc_clocks.PCLK1_Frequency;
-    }
-#if defined(UART4)
-    else if (USARTx == UART4)
-    {
-      periphclk = rcc_clocks.PCLK1_Frequency;
-    }
-#endif /* UART4 */
-#if defined(UART5)
-    else if (USARTx == UART5)
-    {
-      periphclk = rcc_clocks.PCLK1_Frequency;
-    }
-#endif /* UART5 */
-    else
-    {
-      /* Nothing to do, as error code is already assigned to ERROR value */
-    }
-
-    /* Configure the USART Baud Rate :
-       - valid baud rate value (different from 0) is required
-       - Peripheral clock as returned by RCC service, should be valid (different from 0).
-    */
-    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
-        && (USART_InitStruct->BaudRate != 0U))
-    {
-      status = SUCCESS;
-      LL_USART_SetBaudRate(USARTx,
-                           periphclk,
-                           USART_InitStruct->OverSampling,
-                           USART_InitStruct->BaudRate);
-
-      /* Check BRR is greater than or equal to 16d */
-      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-    }
-  }
-  /* Endif (=> USART not in Disabled state => return ERROR) */
-
-  return (status);
-}
-
-/**
-  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
-  * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
-  /* Set USART_InitStruct fields to default values */
-  USART_InitStruct->BaudRate            = 9600U;
-  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
-  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
-  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
-  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
-  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
-  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
-}
-
-/**
-  * @brief  Initialize USART Clock related settings according to the
-  *         specified parameters in the USART_ClockInitStruct.
-  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
-  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  USARTx USART Instance
-  * @param  USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *         that contains the Clock configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check USART Instance and Clock signal output parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /*---------------------------- USART CR2 Configuration -----------------------*/
-    /* If Clock signal has to be output */
-    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
-    {
-      /* Deactivate Clock signal delivery :
-       * - Disable Clock Output:        USART_CR2_CLKEN cleared
-       */
-      LL_USART_DisableSCLKOutput(USARTx);
-    }
-    else
-    {
-      /* Ensure USART instance is USART capable */
-      assert_param(IS_USART_INSTANCE(USARTx));
-
-      /* Check clock related parameters */
-      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
-      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
-      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
-      /*---------------------------- USART CR2 Configuration -----------------------
-       * Configure USARTx CR2 (Clock signal related bits) with parameters:
-       * - Enable Clock Output:         USART_CR2_CLKEN set
-       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
-       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
-       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
-       */
-      MODIFY_REG(USARTx->CR2,
-                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
-                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
-                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
-    }
-  }
-  /* Else (USART not in Disabled state => return ERROR */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
-  * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *                              whose fields will be set to default values.
-  * @retval None
-  */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  /* Set LL_USART_ClockInitStruct fields with default values */
-  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
-  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usb.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usb.c
deleted file mode 100644
index 6405adafbbc..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_usb.c
+++ /dev/null
@@ -1,859 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_usb.c
-  * @author  MCD Application Team
-  * @brief   USB Low Layer HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
-      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
-      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_LL_USB_DRIVER
-  * @{
-  */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-#if defined (USB)
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/**
-  * @brief  Initializes the USB Core
-  * @param  USBx USB Instance
-  * @param  cfg pointer to a USB_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-  UNUSED(cfg);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EnableGlobalInt
-  *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
-{
-  uint32_t winterruptmask;
-
-  /* Clear pending interrupts */
-  USBx->ISTR = 0U;
-
-  /* Set winterruptmask variable */
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
-                   USB_CNTR_RESETM;
-
-  /* Set interrupt mask */
-  USBx->CNTR = (uint16_t)winterruptmask;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DisableGlobalInt
-  *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
-{
-  uint32_t winterruptmask;
-
-  /* Set winterruptmask variable */
-  winterruptmask = USB_CNTR_CTRM  | USB_CNTR_WKUPM |
-                   USB_CNTR_SUSPM | USB_CNTR_ERRM |
-                   USB_CNTR_SOFM | USB_CNTR_ESOFM |
-                   USB_CNTR_RESETM;
-
-  /* Clear interrupt mask */
-  USBx->CNTR &= (uint16_t)(~winterruptmask);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetCurrentMode Set functional mode
-  * @param  USBx Selected device
-  * @param  mode current core mode
-  *          This parameter can be one of the these values:
-  *            @arg USB_DEVICE_MODE Peripheral mode
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-  UNUSED(mode);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevInit Initializes the USB controller registers
-  *         for device mode
-  * @param  USBx Selected device
-  * @param  cfg  pointer to a USB_CfgTypeDef structure that contains
-  *         the configuration information for the specified USBx peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(cfg);
-
-  /* Init Device */
-  /* CNTR_FRES = 1 */
-  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
-  /* CNTR_FRES = 0 */
-  USBx->CNTR = 0U;
-
-  /* Clear pending interrupts */
-  USBx->ISTR = 0U;
-
-  /*Set Btable Address*/
-  USBx->BTABLE = BTABLE_ADDRESS;
-
-  return HAL_OK;
-}
-
-#if defined (HAL_PCD_MODULE_ENABLED)
-/**
-  * @brief  Activate and configure an endpoint
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  HAL_StatusTypeDef ret = HAL_OK;
-  uint16_t wEpRegVal;
-
-  wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
-
-  /* initialize Endpoint */
-  switch (ep->type)
-  {
-    case EP_TYPE_CTRL:
-      wEpRegVal |= USB_EP_CONTROL;
-      break;
-
-    case EP_TYPE_BULK:
-      wEpRegVal |= USB_EP_BULK;
-      break;
-
-    case EP_TYPE_INTR:
-      wEpRegVal |= USB_EP_INTERRUPT;
-      break;
-
-    case EP_TYPE_ISOC:
-      wEpRegVal |= USB_EP_ISOCHRONOUS;
-      break;
-
-    default:
-      ret = HAL_ERROR;
-      break;
-  }
-
-  PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
-
-  PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
-
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      /*Set the endpoint Transmit buffer address */
-      PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-      else
-      {
-        /* Configure TX Endpoint to disabled state */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      }
-    }
-    else
-    {
-      /*Set the endpoint Receive buffer address */
-      PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
-
-      /*Set the endpoint Receive buffer counter*/
-      PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure VALID status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-    }
-  }
-  /*Double Buffer*/
-  else
-  {
-    /* Set the endpoint as double buffered */
-    PCD_SET_EP_DBUF(USBx, ep->num);
-
-    /* Set buffer address for double buffered mode */
-    PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
-
-    if (ep->is_in == 0U)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT */
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT */
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-      else
-      {
-        /* Configure TX Endpoint to disabled state */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      }
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-
-  return ret;
-}
-
-/**
-  * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-  /*Double Buffer*/
-  else
-  {
-    if (ep->is_in == 0U)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      /* Reset value of the data toggle bits for the endpoint out*/
-      PCD_TX_DTOG(USBx, ep->num);
-
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-      PCD_RX_DTOG(USBx, ep->num);
-
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPStartXfer setup and starts a transfer over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  uint32_t len;
-  uint16_t pmabuffer;
-  uint16_t wEPVal;
-
-  /* IN endpoint */
-  if (ep->is_in == 1U)
-  {
-    /*Multi packet transfer*/
-    if (ep->xfer_len > ep->maxpacket)
-    {
-      len = ep->maxpacket;
-    }
-    else
-    {
-      len = ep->xfer_len;
-    }
-
-    /* configure and validate Tx endpoint */
-    if (ep->doublebuffer == 0U)
-    {
-      USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
-      PCD_SET_EP_TX_CNT(USBx, ep->num, len);
-    }
-    else
-    {
-      /* double buffer bulk management */
-      if (ep->type == EP_TYPE_BULK)
-      {
-        if (ep->xfer_len_db > ep->maxpacket)
-        {
-          /* enable double buffer */
-          PCD_SET_EP_DBUF(USBx, ep->num);
-
-          /* each Time to write in PMA xfer_len_db will */
-          ep->xfer_len_db -= len;
-
-          /* Fill the two first buffer in the Buffer0 & Buffer1 */
-          if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
-          {
-            /* Set the Double buffer counter for pmabuffer1 */
-            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr1;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-            ep->xfer_buff += len;
-
-            if (ep->xfer_len_db > ep->maxpacket)
-            {
-              ep->xfer_len_db -= len;
-            }
-            else
-            {
-              len = ep->xfer_len_db;
-              ep->xfer_len_db = 0U;
-            }
-
-            /* Set the Double buffer counter for pmabuffer0 */
-            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr0;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-          else
-          {
-            /* Set the Double buffer counter for pmabuffer0 */
-            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr0;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-            ep->xfer_buff += len;
-
-            if (ep->xfer_len_db > ep->maxpacket)
-            {
-              ep->xfer_len_db -= len;
-            }
-            else
-            {
-              len = ep->xfer_len_db;
-              ep->xfer_len_db = 0U;
-            }
-
-            /* Set the Double buffer counter for pmabuffer1 */
-            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr1;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-        }
-        /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
-        else
-        {
-          len = ep->xfer_len_db;
-
-          /* disable double buffer mode */
-          PCD_CLEAR_EP_DBUF(USBx, ep->num);
-
-          /* Set Tx count with nbre of byte to be transmitted */
-          PCD_SET_EP_TX_CNT(USBx, ep->num, len);
-          pmabuffer = ep->pmaaddr0;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-        }
-      }/* end if bulk double buffer */
-
-      /* manage isochronous double buffer IN mode */
-      else
-      {
-        /* enable double buffer */
-        PCD_SET_EP_DBUF(USBx, ep->num);
-
-        /* each Time to write in PMA xfer_len_db will */
-        ep->xfer_len_db -= len;
-
-        /* Fill the data buffer */
-        if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
-        {
-          /* Set the Double buffer counter for pmabuffer1 */
-          PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-          pmabuffer = ep->pmaaddr1;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          ep->xfer_buff += len;
-
-          if (ep->xfer_len_db > ep->maxpacket)
-          {
-            ep->xfer_len_db -= len;
-          }
-          else
-          {
-            len = ep->xfer_len_db;
-            ep->xfer_len_db = 0U;
-          }
-
-          if (len > 0U)
-          {
-            /* Set the Double buffer counter for pmabuffer0 */
-            PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr0;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-        }
-        else
-        {
-          /* Set the Double buffer counter for pmabuffer0 */
-          PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
-          pmabuffer = ep->pmaaddr0;
-
-          /* Write the user buffer to USB PMA */
-          USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          ep->xfer_buff += len;
-
-          if (ep->xfer_len_db > ep->maxpacket)
-          {
-            ep->xfer_len_db -= len;
-          }
-          else
-          {
-            len = ep->xfer_len_db;
-            ep->xfer_len_db = 0U;
-          }
-
-          if (len > 0U)
-          {
-            /* Set the Double buffer counter for pmabuffer1 */
-            PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
-            pmabuffer = ep->pmaaddr1;
-
-            /* Write the user buffer to USB PMA */
-            USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
-          }
-        }
-      }
-    }
-
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
-  }
-  else /* OUT endpoint */
-  {
-    if (ep->doublebuffer == 0U)
-    {
-      /* Multi packet transfer */
-      if (ep->xfer_len > ep->maxpacket)
-      {
-        len = ep->maxpacket;
-        ep->xfer_len -= len;
-      }
-      else
-      {
-        len = ep->xfer_len;
-        ep->xfer_len = 0U;
-      }
-      /* configure and validate Rx endpoint */
-      PCD_SET_EP_RX_CNT(USBx, ep->num, len);
-    }
-    else
-    {
-      /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
-      /* Set the Double buffer counter */
-      if (ep->type == EP_TYPE_BULK)
-      {
-        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
-
-        /* Coming from ISR */
-        if (ep->xfer_count != 0U)
-        {
-          /* update last value to check if there is blocking state */
-          wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
-
-          /*Blocking State */
-          if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
-              (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
-          {
-            PCD_FreeUserBuffer(USBx, ep->num, 0U);
-          }
-        }
-      }
-      /* iso out double */
-      else if (ep->type == EP_TYPE_ISOC)
-      {
-        /* Multi packet transfer */
-        if (ep->xfer_len > ep->maxpacket)
-        {
-          len = ep->maxpacket;
-          ep->xfer_len -= len;
-        }
-        else
-        {
-          len = ep->xfer_len;
-          ep->xfer_len = 0U;
-        }
-        PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
-      }
-      else
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-  }
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  USB_EPSetStall set a stall condition over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->is_in != 0U)
-  {
-    PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
-  }
-  else
-  {
-    PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_EPClearStall Clear a stall condition over an EP
-  * @param  USBx Selected device
-  * @param  ep pointer to endpoint structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
-  if (ep->doublebuffer == 0U)
-  {
-    if (ep->is_in != 0U)
-    {
-      PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
-      if (ep->type != EP_TYPE_ISOC)
-      {
-        /* Configure NAK status for the Endpoint */
-        PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
-      }
-    }
-    else
-    {
-      PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
-      /* Configure VALID status for the Endpoint */
-      PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
-    }
-  }
-
-  return HAL_OK;
-}
-#endif
-
-/**
-  * @brief  USB_StopDevice Stop the usb device mode
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
-{
-  /* disable all interrupts and force USB reset */
-  USBx->CNTR = (uint16_t)USB_CNTR_FRES;
-
-  /* clear interrupt status register */
-  USBx->ISTR = 0U;
-
-  /* switch-off device */
-  USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_SetDevAddress Stop the usb device mode
-  * @param  USBx Selected device
-  * @param  address new device address to be assigned
-  *          This parameter can be a value from 0 to 255
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
-{
-  if (address == 0U)
-  {
-    /* set device address and enable function */
-    USBx->DADDR = (uint16_t)USB_DADDR_EF;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevConnect(USB_TypeDef *USBx)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  USB_DevDisconnect(USB_TypeDef *USBx)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(USBx);
-
-  /* NOTE : - This function is not required by USB Device FS peripheral, it is used
-              only by USB OTG FS peripheral.
-            - This function is added to ensure compatibility across platforms.
-   */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_ReadInterrupts return the global USB interrupt status
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-uint32_t  USB_ReadInterrupts(USB_TypeDef *USBx)
-{
-  uint32_t tmpreg;
-
-  tmpreg = USBx->ISTR;
-  return tmpreg;
-}
-
-/**
-  * @brief  USB_ActivateRemoteWakeup : active remote wakeup signalling
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
-{
-  USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
-  * @param  USBx Selected device
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
-{
-  USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx USB peripheral instance register address.
-  * @param   pbUsrBuf pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
-  uint32_t BaseAddr = (uint32_t)USBx;
-  uint32_t i, temp1, temp2;
-  __IO uint16_t *pdwVal;
-  uint8_t *pBuf = pbUsrBuf;
-
-  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
-  for (i = n; i != 0U; i--)
-  {
-    temp1 = *pBuf;
-    pBuf++;
-    temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
-    *pdwVal = (uint16_t)temp2;
-    pdwVal++;
-
-#if PMA_ACCESS > 1U
-    pdwVal++;
-#endif
-
-    pBuf++;
-  }
-}
-
-/**
-  * @brief Copy data from packet memory area (PMA) to user memory buffer
-  * @param   USBx USB peripheral instance register address.
-  * @param   pbUsrBuf pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = (uint32_t)wNBytes >> 1;
-  uint32_t BaseAddr = (uint32_t)USBx;
-  uint32_t i, temp;
-  __IO uint16_t *pdwVal;
-  uint8_t *pBuf = pbUsrBuf;
-
-  pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
-
-  for (i = n; i != 0U; i--)
-  {
-    temp = *(__IO uint16_t *)pdwVal;
-    pdwVal++;
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
-    pBuf++;
-    *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
-    pBuf++;
-
-#if PMA_ACCESS > 1U
-    pdwVal++;
-#endif
-  }
-
-  if ((wNBytes % 2U) != 0U)
-  {
-    temp = *pdwVal;
-    *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
-  }
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB) */
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_utils.c b/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_utils.c
deleted file mode 100644
index baad913c3ca..00000000000
--- a/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/stm32l1xx_ll_utils.c
+++ /dev/null
@@ -1,580 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_utils.c
-  * @author  MCD Application Team
-  * @brief   UTILS LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_rcc.h"
-#include "stm32l1xx_ll_utils.h"
-#include "stm32l1xx_ll_system.h"
-#include "stm32l1xx_ll_pwr.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32L1xx_LL_Driver
-  * @{
-  */
-
-/** @addtogroup UTILS_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
-  * @{
-  */
-#define UTILS_MAX_FREQUENCY_SCALE1  32000000U        /*!< Maximum frequency for system clock at power scale1, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE2  16000000U        /*!< Maximum frequency for system clock at power scale2, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE3   4000000U        /*!< Maximum frequency for system clock at power scale3, in Hz */
-
-/* Defines used for PLL range */
-#define UTILS_PLLVCO_OUTPUT_SCALE1  96000000U        /*!< Frequency max for PLLVCO output at power scale1, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE2  48000000U        /*!< Frequency max for PLLVCO output at power scale2, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE3  24000000U        /*!< Frequency max for PLLVCO output at power scale3, in Hz  */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN      1000000U       /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX     24000000U       /*!< Frequency max for HSE frequency, in Hz   */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#define UTILS_SCALE1_LATENCY1_FREQ  16000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
-#define UTILS_SCALE2_LATENCY1_FREQ   8000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
-#define UTILS_SCALE3_LATENCY1_FREQ   2000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
-                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
-
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_16) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_24) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_32) \
-                                          || ((__VALUE__) == LL_RCC_PLL_MUL_48))
-
-#define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \
-                                             ((__VALUE__) == LL_RCC_PLL_DIV_4))
-
-#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \
-                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \
-                                             ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3)))
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
-                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
-                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)))
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
-                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
-  * @{
-  */
-static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
-                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UTILS_LL_EF_DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
-  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  HCLKFrequency HCLK frequency in Hz
-  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
-  * @retval None
-  */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
-  /* Use frequency provided in argument */
-  LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
-  * @brief  This function provides accurate delay (in milliseconds) based
-  *         on SysTick counter flag
-  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
-  *         and use rather osDelay service.
-  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
-  *         will configure Systick to 1ms
-  * @param  Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void LL_mDelay(uint32_t Delay)
-{
-  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
-  uint32_t tmpDelay = Delay;
-
-  /* Add this code to indicate that local variable is not used */
-  ((void)tmp);
-
-  /* Add a period to guaranty minimum wait */
-  if(tmpDelay < LL_MAX_DELAY)
-  {
-    tmpDelay++;
-  }
-
-  while (tmpDelay != 0U)
-  {
-    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
-    {
-      tmpDelay--;
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_EF_SYSTEM
-  *  @brief    System Configuration functions
-  *
-  @verbatim
- ===============================================================================
-           ##### System Configuration functions #####
- ===============================================================================
-    [..]
-         System, AHB and APB buses clocks configuration
-
-         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz.
-  @endverbatim
-  @internal
-             Depending on the device voltage range, the maximum frequency should be
-             adapted accordingly:
-             (++) +----------------------------------------------------------------+
-             (++) |  Wait states  |                HCLK clock frequency (MHz)      |
-             (++) |               |------------------------------------------------|
-             (++) |   (Latency)   |            voltage range       | voltage range |
-             (++) |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
-             (++) |               |----------------|---------------|---------------|
-             (++) |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
-             (++) |-------------- |----------------|---------------|---------------|
-             (++) |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
-             (++) |---------------|----------------|---------------|---------------|
-             (++) |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
-             (++) +----------------------------------------------------------------+
-  @endinternal
-  * @{
-  */
-
-/**
-  * @brief  This function sets directly SystemCoreClock CMSIS variable.
-  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @retval None
-  */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
-  /* HCLK clock frequency */
-  SystemCoreClock = HCLKFrequency;
-}
-
-/**
-  * @brief  Update number of Flash wait states in line with new frequency and current
-            voltage range.
-  * @param  Frequency  HCLK frequency
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Latency has been modified
-  *          - ERROR: Latency cannot be modified
-  */
-#if defined(FLASH_ACR_LATENCY)
-ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
-{
-  ErrorStatus status = SUCCESS;
-
-  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
-
-  /* Frequency cannot be equal to 0 or greater than max clock */
-  if ((Frequency == 0U) || (Frequency > UTILS_MAX_FREQUENCY_SCALE1))
-  {
-    status = ERROR;
-  }
-  else
-  {
-    if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
-    {
-      if (Frequency > UTILS_SCALE1_LATENCY1_FREQ)
-      {
-        /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */
-     }
-    else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
-    {
-      if (Frequency > UTILS_SCALE2_LATENCY1_FREQ)
-      {
-        /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */
-    }
-    else
-    {
-      if (Frequency > UTILS_SCALE3_LATENCY1_FREQ)
-      {
-        /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      /* else HCLK < 4MHz default LL_FLASH_LATENCY_0 0WS */
-    }
-
-    /* Latency cannot be set to 1WS only if 64-bit access bit is enabled */
-    if (latency == LL_FLASH_LATENCY_1)
-    {
-      LL_FLASH_Enable64bitAccess();
-    }
-
-    LL_FLASH_SetLatency(latency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-       memory by reading the FLASH_ACR register */
-    if (LL_FLASH_GetLatency() != latency)
-    {
-      status = ERROR;
-    }
-  }
-  return status;
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/**
-  * @brief  This function configures system clock with HSI as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv)
-  *         - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding
-  *           - 96 MHz as PLLVCO when the product is in range 1,
-  *           - 48 MHz as PLLVCO when the product is in range 2,
-  *           - 24 MHz when the product is in range 3
-  * @note   FLASH latency can be modified through this function.
-  * @note   If this latency increases to 1WS, FLASH 64-bit access will be automatically enabled.
-  *         A decrease of FLASH latency to 0WS will not disable 64-bit access. If needed, user should call
-  *         the following function @ref LL_FLASH_Disable64bitAccess.
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status;
-  uint32_t pllfreq;
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
-    /* Enable HSI if not enabled */
-    if (LL_RCC_HSI_IsReady() != 1U)
-    {
-      LL_RCC_HSI_Enable();
-      while (LL_RCC_HSI_IsReady() != 1U)
-      {
-        /* Wait for HSI ready */
-      }
-    }
-
-    /* Configure PLL */
-    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  This function configures system clock with HSE as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv)
-  *         - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding
-  *           - 96 MHz as PLLVCO when the product is in range 1,
-  *           - 48 MHz as PLLVCO when the product is in range 2,
-  *           - 24 MHz when the product is in range 3
-  * @note   FLASH latency can be modified through this function.
-  * @note   If this latency increases to 1WS, FLASH 64-bit access will be automatically enabled.
-  *         A decrease of FLASH latency to 0WS will not disable 64-bit access. If needed, user should call
-  *         the following function @ref LL_FLASH_Disable64bitAccess.
-  * @param  HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000
-  * @param  HSEBypass This parameter can be one of the following values:
-  *         @arg @ref LL_UTILS_HSEBYPASS_ON
-  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status;
-  uint32_t pllfreq;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
-  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
-    /* Enable HSE if not enabled */
-    if (LL_RCC_HSE_IsReady() != 1U)
-    {
-      /* Check if need to enable HSE bypass feature or not */
-      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
-      {
-        LL_RCC_HSE_EnableBypass();
-      }
-      else
-      {
-        LL_RCC_HSE_DisableBypass();
-      }
-
-      /* Enable HSE */
-      LL_RCC_HSE_Enable();
-      while (LL_RCC_HSE_IsReady() != 1U)
-      {
-        /* Wait for HSE ready */
-      }
-    }
-
-      /* Configure PLL */
-      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_LL_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Function to check that PLL can be modified
-  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @retval PLL output frequency (in Hz)
-  */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
-  uint32_t pllfreq;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-  assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-
-  /* Check different PLL parameters according to RM                          */
-  /* The application software must set correctly the PLL multiplication factor to avoid exceeding
-     96 MHz as PLLVCO when the product is in range 1,
-     48 MHz as PLLVCO when the product is in range 2,
-     24 MHz when the product is in range 3. */
-  pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_CFGR_PLLMUL_Pos]);
-  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
-
-  /* The application software must set correctly the PLL multiplication factor to avoid exceeding
-     maximum frequency 32000000 in range 1 */
-  pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U);
-  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
-  return pllfreq;
-}
-
-/**
-  * @brief  Function to check that PLL can be modified
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PLL modification can be done
-  *          - ERROR: PLL is busy
-  */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check if PLL is busy*/
-  if (LL_RCC_PLL_IsReady() != 0U)
-  {
-    /* PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Function to enable PLL and switch system clock to PLL
-  * @param  SYSCLK_Frequency SYSCLK frequency
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: No problem to switch system to PLL
-  *          - ERROR: Problem to switch system to PLL
-  */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  uint32_t hclk_frequency;
-
-  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
-  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
-  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
-
-  /* Calculate HCLK frequency */
-  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if (SystemCoreClock < hclk_frequency)
-  {
-    /* Set FLASH latency to highest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update system clock configuration */
-  if (status == SUCCESS)
-  {
-    /* Enable PLL */
-    LL_RCC_PLL_Enable();
-    while (LL_RCC_PLL_IsReady() != 1U)
-    {
-      /* Wait for PLL ready */
-    }
-
-    /* Sysclk activation on the main PLL */
-    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
-    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
-    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
-    {
-      /* Wait for system clock switch to PLL */
-    }
-
-    /* Set APB1 & APB2 prescaler*/
-    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
-    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if (SystemCoreClock > hclk_frequency)
-  {
-    /* Set FLASH latency to lowest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update SystemCoreClock variable */
-  if (status == SUCCESS)
-  {
-    LL_SetSystemCoreClock(hclk_frequency);
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/